CN206226392U - A kind of CMOS integrated monostable circuits of not reproducible triggering - Google Patents
A kind of CMOS integrated monostable circuits of not reproducible triggering Download PDFInfo
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- CN206226392U CN206226392U CN201621136814.9U CN201621136814U CN206226392U CN 206226392 U CN206226392 U CN 206226392U CN 201621136814 U CN201621136814 U CN 201621136814U CN 206226392 U CN206226392 U CN 206226392U
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Abstract
The utility model discloses a kind of integrated monostable circuits of CMOS of not reproducible triggering, includes input control circuit U1, resistance capacitance series network, latch, SECO network, reference current source IREF, voltage-regulator diode D1 and output phase inverter U6；The resistance capacitance series network includes resistance R1 and electric capacity C1；The input of the output termination output phase inverter U6 of the latch, wherein, latch includes nor gate U4, electric capacity C2, phase inverter U5 and level shift circuit Us 3；The utility model is charged using constant current source to electric capacity, and the temporary steady state time width of stabilization is realized in form on piece, it is to avoid is used big resistance, chip area is effectively reduced, while being substantially reduced influences of the PVT to discharge and recharge.Also, metal-oxide-semiconductor M1, metal-oxide-semiconductor M2 can carry out fast charging and discharging to node 1,2, it is equal to ensure the leaping voltage value at the electric capacity two ends in triggering next time to stablize this 2 points magnitude of voltage, so that constant charge time constant.
Description
Technical field
The utility model is related to monostable circuit art, refers in particular to a kind of integrated lists of CMOS of not reproducible triggering
Steady-state circuit.
Background technology
In existing digital monostable circuit, in order to obtain the time of long temporary stable state, one in specific design
As can use than larger resistance capacitance（RC）Network.In traditional design, typically realized by two schemes：One is with chip
The mode of external capacitor resistance, this scheme chips need to additionally introduce PIN, not only cause larger package dimension, increase
The manufacturing cost of pcb board level circuit, and external noise source can be introduced.In recent years, with the hair at full speed of semiconductor technology
Exhibition and the continuous continuity of Moore's Law cause that the inferior position of this method for designing is highlighted.Two is that resistance-capacitance network is integrated in into core
Inside piece, this scheme can cause chip area to significantly increase, and in actual chips production, due to semiconductor device parameter
By the influence of PVT (process, voltage, temperature), temporary steady state time length between different chips with set
There is larger difference in evaluation, therefore, this scheme cannot be applied has the meter compared with exact requirements in the time span to temporary stable state
When circuit in, for example：According to 1-wire protocol requirements, receiving that device needs in 15~60us after reset signal is received will be total
Line moves low level to.Accordingly, it would be desirable to monostable timing circuit of 15~60us realizes this function.But in PVT factors
Under the influence of, cannot all realize this requirement using traditional on chip designs.Especially because resistance R receives temperature, adulterate dense
The influence of the factors such as degree, lithographic accuracy, temporary steady state time change width is very big.
Utility model content
In view of this, the utility model in view of the existing deficiencies of the prior art, improves traditional monostable circuit, and its is main
Purpose is to provide a kind of integrated monostable circuits of CMOS of not reproducible triggering, and it has the more stable temporary steady-state pulse of timing
Width, is allowed to be influenceed to minimize by technique PVT changes.
To achieve the above object, the utility model is using following technical scheme：
A kind of integrated monostable circuits of CMOS of not reproducible triggering, include input control circuit U1, resistance capacitance string
Networking network, latch, SECO network, reference current source IREF, voltage-regulator diode D1 and output phase inverter U6；The resistance
Capacitances in series network includes resistance R1 and electric capacity C1, one end of the output termination capacitor C1 of input control circuit U1, electric capacity
One end of the other end connection resistance R1 of C1, the other end ground connection of resistance R1；
The input of the output termination output phase inverter U6 of the latch, wherein, latch includes nor gate U4, electric capacity
C2, phase inverter U5 and level-shift circuit U 3；One input of nor gate U4 connects the connection of resistance R1 and electric capacity C1
End, the output end of another input connection level-shift circuit Us 3 of nor gate U4, the output end connection electric capacity of nor gate U4
One end of C2, the other end of electric capacity C2 connects input, the anode of voltage-regulator diode D1 and the reference current source I of phase inverter U5REF
Positive pole, the negative electrode and reference current source I of voltage-regulator diode D1REFNegative pole connection supply voltage VDD, the output of phase inverter U5
The input of termination level-shift circuit Us 3；
The SECO network includes phase inverter U7, phase inverter U9, time delay buffer U8, master controller U2, metal-oxide-semiconductor
M1 and metal-oxide-semiconductor M2；Wherein master controller U2 has 4 interfaces：C terminals, d terminals, e terminals and f terminals, wherein c terminals with it is anti-
The output end of phase device U9 is connected, the output of input termination input signal in, the d terminal connection time delay buffer U8 of phase inverter U9
End, e terminals connection POR input signals end, the grid end of f terminals connection metal-oxide-semiconductor M1 and the grid end of metal-oxide-semiconductor M2；The metal-oxide-semiconductor M1's
The input of the source connection phase inverter U5 of drain terminal connection the supply voltage VDD, metal-oxide-semiconductor M1 of drain terminal and metal-oxide-semiconductor M2, metal-oxide-semiconductor M2
Source connection output phase inverter U6 input, the output end of the input termination output phase inverter U6 of phase inverter U7, phase inverter
The output end of U7 connects the input of U8 time delay buffers.
Used as a kind of preferred scheme, the level-shift circuit Us 3 are level shifting circuit, the reference electricity that it will be input into
Pressure VREFIt is converted into supply voltage VDD.
The utility model has clear advantage and beneficial effect compared with prior art, specifically, by above-mentioned technology
Scheme understands：
The utility model is charged using constant current source to electric capacity, realizes that the temporary steady state time of stabilization is wide in form on piece
Degree, it is to avoid use big resistance, chip area is effectively reduced, while being substantially reduced influences of the PVT to discharge and recharge.Also, metal-oxide-semiconductor
M1, metal-oxide-semiconductor M2 can carry out fast charging and discharging to node 1,2, stablize this 2 points magnitude of voltage to ensure the electric capacity in triggering next time
The leaping voltage value at two ends is consistent, so that constant charge time constant.
More clearly to illustrate architectural feature of the present utility model and effect, come right with specific embodiment below in conjunction with the accompanying drawings
The utility model is described in detail.
Brief description of the drawings
Fig. 1 is the structural representation of the preferred embodiment of the utility model；
Fig. 2 is the timing diagram of the preferred embodiment of the utility model.
Accompanying drawing identifier declaration：
10th, resistance capacitance series network 20, latch
30th, SECO network.
Specific embodiment
Refer to shown in Fig. 1 and Fig. 2, that show the concrete structure of the preferred embodiment of the utility model, include
Input control circuit U1, resistance capacitance series network 10, latch 20, SECO network 30, reference current source IREF, voltage stabilizing
Diode D1 and output phase inverter U6.
The resistance capacitance series network 10 includes resistance R1 and electric capacity C1, the output termination electricity of input control circuit U1
Hold one end of C1, one end of the other end connection resistance R1 of electric capacity C1, the other end ground connection of resistance R1.
The input of the output termination output phase inverter U6 of the latch 20, wherein, latch 20 include nor gate U4,
Electric capacity C2, phase inverter U5 and level-shift circuit U 3；One input of nor gate U4 connects the company of resistance R1 and electric capacity C1
Connect end, the output end of another input connection level-shift circuit Us 3 of nor gate U4, the output end connection electricity of nor gate U4
Hold one end of C2, input, the anode and reference current source of voltage-regulator diode D1 of the other end connection phase inverter U5 of electric capacity C2
IREFPositive pole, the negative electrode and reference current source I of voltage-regulator diode D1REFNegative pole connection supply voltage VDD, phase inverter U5's is defeated
Go out to terminate the input of level-shift circuit Us 3.In the present embodiment, the level-shift circuit Us 3 are level conversion
Circuit, its reference voltage V that will be input intoREFIt is converted into supply voltage VDD.
The SECO network 30 includes phase inverter U7, time delay buffer U8, master controller U2, metal-oxide-semiconductor M1 and MOS
Pipe M2；Wherein master controller U2 has 4 interfaces：C terminals, d terminals, e terminals and f terminals, wherein c terminals are with phase inverter U9's
Output end is connected, the output end of input connection input signal in, the d terminal connection time delay buffer U8 of phase inverter U9, e terminals
Connection POR input signals end, the grid end of f terminals connection metal-oxide-semiconductor M1 and the grid end of metal-oxide-semiconductor M2；The drain terminal of the metal-oxide-semiconductor M1 and
The input of the source connection phase inverter U5 of drain terminal connection the supply voltage VDD, metal-oxide-semiconductor M1 of metal-oxide-semiconductor M2, the source of metal-oxide-semiconductor M2
The input of connection output phase inverter U6, the output end of the input termination output phase inverter U6 of phase inverter U7, phase inverter U7's is defeated
Go out the input of end connection U8 time delay buffers.
During work, as shown in Fig. 2 the major function of the input control circuit U1 is to produce a short pulse signal to touch
Hair latch 20 below.And only when input control circuit U1 inputs are a trailing edge signals, its output can just be produced
Raw pulse.That is only when trailing edge occur in total input in signals, circuit can just enter temporary this monostable circuit
Lower state.This is a monostable circuit structure for edging trigger.
As shown in figure 1, the output of input control circuit U1 is made after producing a positive pulse by the coupling of electric capacity C1
Obtain node 4 and suddenly become high level, so that node 1 suddenly becomes low level, then cause that node 2 becomes by the coupling of electric capacity C2
Into low level.Another input for causing nor gate U4 eventually through phase inverter U5 becomes high level, now the quilt of latch 20
Locking is output as low level, and circuit enters temporary stable state.After node 2 suddenly becomes low level, reference current source IREFStart to section
Point 2 is charged, and when the voltage of node 2 reaches the threshold voltage vt h of phase inverter U5, output switching activity is low level, due to section
Point 4 is already discharged to low level in the charging process of node 2 by resistance R1, therefore when node 2 reaches Vth voltages,
Node 1 can be turned into high level, and by the coupling of electric capacity C2, the level of node 2 is up to VDD+Vth, so that latch
20 output node 1 is locked in high level, and circuit enters stable state.
As described above, when total input in signals are trailing edges, the master controller U2 in SECO network 30 will be defeated
Go out high level, now metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 is turned off.During temporary stable state, metal-oxide-semiconductor M1, metal-oxide-semiconductor M2 branch roads will not be to latching
Device 20 produces influence.When node 1 returns to stable state high level from the low level of temporary stable state, time delay buffer U8 will be produced on one
Rise makes main controller U2 export a low level along output, and metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 will be turned on and be caused that node 1,2 is rapid extensive
VDD level is arrived again to wait next triggering.
As described above, the major function of master controller U2 is：During c terminals input rising edge, output produces high level；D ends
During son input rising edge, output produces low level, and both are independent of each other.
As can be seen that in order to metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 do not influence latch 20 to enter the time of temporary stable state, input control
The transmission delay time of circuit U 1 must be than master controller U2 the transmission delay time it is long, i.e., in node 4 due to the coupling of electric capacity C1
Before conjunction becomes high level, node 3 must first become high level to turn off metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2.
The major function of the utility model circuit is the pulse signal for producing stabilization time length.The length master of pulse width
To depend on reference current source IREFSize, the capacitance size of electric capacity C2 and phase inverter U5 threshold voltage vt h size.For
Ensure the stability of the Vth under different voltages, the power supply of reverser U5 is by a reference power source VREFThere is provided.Metal-oxide-semiconductor M1, metal-oxide-semiconductor
The major function of M2 makes sure that the coupling of each electric capacity C2 all so that the level of node 2 is to jump to GND from VDD.
Especially under continuous quick triggering situation, the rapid jumping of the level of node 2 becomes especially important, because the level meeting of node 2
VDD+Vth is reached, due to reference current source IREFElectric current it is relative smaller can cause node 2 cannot Quick-return it is electric to VDD
Flat, if now input signal in carrys out a trailing edge triggering, node 2 will be unable to be coupled to GND, so as to influence the charging interval.
By above method can not only constant charge time constant, and the area of circuit can also reduce a lot.
The above, is only preferred embodiment of the present utility model, and not technical scope of the present utility model is made
Any limitation, therefore every any trickle amendment, equivalent change made to above example according to technical spirit of the present utility model
Change and modify, still fall within the range of technical solutions of the utility model.
Claims (2)
1. integrated monostable circuits of CMOS of a kind of not reproducible triggering, it is characterised in that：Include input control circuit U1, electricity
Resistance capacitances in series network, latch, SECO network, reference current source IREF, voltage-regulator diode D1 and output phase inverter
U6；The resistance capacitance series network includes resistance R1 and electric capacity C1, the output termination capacitor C1's of input control circuit U1
One end, one end of the other end connection resistance R1 of electric capacity C1, the other end ground connection of resistance R1；
The input of the output termination output phase inverter U6 of the latch, wherein, latch include nor gate U4, electric capacity C2,
Phase inverter U5 and level-shift circuit U 3；One input of nor gate U4 connects the connection end of resistance R1 and electric capacity C1, or
The output end of another input connection level-shift circuit Us 3 of not gate U4, the output end connection electric capacity C2's of nor gate U4
One end, the other end of electric capacity C2 connects input, the anode of voltage-regulator diode D1 and the reference current source I of phase inverter U5REFJust
Pole, the negative electrode and reference current source I of voltage-regulator diode D1REFNegative pole connection supply voltage VDD, phase inverter U5 output termination
The input of level-shift circuit Us 3；
The SECO network include phase inverter U7, phase inverter U9, time delay buffer U8, master controller U2, metal-oxide-semiconductor M1 and
Metal-oxide-semiconductor M2；Wherein master controller U2 has 4 interfaces：C terminals, d terminals, e terminals and f terminals, wherein c terminals and phase inverter
The output end of U9 is connected, the output end of input termination input signal in, the d terminal connection time delay buffer U8 of phase inverter U9, e ends
Son connection POR input signals end, the grid end of f terminals connection metal-oxide-semiconductor M1 and the grid end of metal-oxide-semiconductor M2；The drain terminal of the metal-oxide-semiconductor M1 and
The input of the source connection phase inverter U5 of drain terminal connection the supply voltage VDD, metal-oxide-semiconductor M1 of metal-oxide-semiconductor M2, the source of metal-oxide-semiconductor M2
The input of connection output phase inverter U6, the output end of the input termination output phase inverter U6 of phase inverter U7, phase inverter U7's is defeated
Go out the input that end connects time delay buffer U8.
2. integrated monostable circuits of CMOS of a kind of not reproducible triggering according to claim 1, it is characterised in that：It is described
Level-shift circuit Us 3 are level shifting circuit, its reference voltage V that will be input intoREFIt is converted into supply voltage VDD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621136814.9U CN206226392U (en) | 2016-10-19 | 2016-10-19 | A kind of CMOS integrated monostable circuits of not reproducible triggering |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621136814.9U CN206226392U (en) | 2016-10-19 | 2016-10-19 | A kind of CMOS integrated monostable circuits of not reproducible triggering |
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| Publication Number | Publication Date |
|---|---|
| CN206226392U true CN206226392U (en) | 2017-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621136814.9U Withdrawn - After Issue CN206226392U (en) | 2016-10-19 | 2016-10-19 | A kind of CMOS integrated monostable circuits of not reproducible triggering |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374886A (en) * | 2016-10-19 | 2017-02-01 | 加驰（厦门）微电子技术有限公司 | CMOS integrated monostable circuit with characteristic of repeated triggering prevention |
-
2016
- 2016-10-19 CN CN201621136814.9U patent/CN206226392U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374886A (en) * | 2016-10-19 | 2017-02-01 | 加驰（厦门）微电子技术有限公司 | CMOS integrated monostable circuit with characteristic of repeated triggering prevention |
| CN106374886B (en) * | 2016-10-19 | 2023-05-05 | 加驰（厦门）微电子股份有限公司 | Non-repeatable triggering CMOS integrated monostable circuit |
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Granted publication date: 20170606 Effective date of abandoning: 20230505 |
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| AV01 | Patent right actively abandoned |
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| AV01 | Patent right actively abandoned |