CN104282328A - Periodic signal generating device - Google Patents

Periodic signal generating device Download PDF

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Publication number
CN104282328A
CN104282328A CN201310285321.6A CN201310285321A CN104282328A CN 104282328 A CN104282328 A CN 104282328A CN 201310285321 A CN201310285321 A CN 201310285321A CN 104282328 A CN104282328 A CN 104282328A
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CN
China
Prior art keywords
little
reference voltage
phase inverter
limit reference
delay
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CN201310285321.6A
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Chinese (zh)
Inventor
黄乘黄
朱莎勤
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Ricoh Microelectronics Co Ltd
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Ricoh Co Ltd
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Priority to CN201310285321.6A priority Critical patent/CN104282328A/en
Priority to JP2014137750A priority patent/JP2015019362A/en
Publication of CN104282328A publication Critical patent/CN104282328A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses

Abstract

The invention relates to a periodic signal generating device for outputting slight oscillation signals. The periodic signal generating device comprises a slight oscillation reference voltage generating unit, a comparator unit and a wave-shaping and time-delay unit. The slight oscillation reference voltage generating unit outputs slight oscillation lower-limit reference voltage and slight oscillation upper-limit reference voltage, and the absolute value of the difference of the slight oscillation lower-limit reference voltage and slight oscillation upper-limit reference voltage is enough small so that the slight oscillation lower-limit reference voltage and slight oscillation upper-limit reference voltage are simultaneously logic low electrical levels or logic high electrical levels. One input end of the comparator unit is connected to an output end of the slight oscillation reference voltage generating unit and the other input end of the comparator unit is connected to a slight oscillation signal. An input end of the wave-shaping and time-delay unit is connected to an output end of the comparator unit and is used for outputting a slight oscillation signal and the slight oscillation signal periodically oscillates in a range from the slight oscillation lower-limit reference voltage to the slight oscillation upper-limit reference voltage.

Description

Cycle signal generator
Technical field
The present invention relates to a kind of cycle signal generator for exporting oscillator signal a little, particularly relating to the cycle signal generator being applied to the adjustable time-delay mechanism of delay time.
Background technology
For example, as shown in Figure 1, in the prior art, if need to carry out the adjustable time delay of delay time to the voltage jump of the DOUT pin had in the chip of six pins, traditional way is by increasing a pin by delay capacitor access chip.This is because the oscillator signal in the time-delay mechanism of prior art is periodically variable periodic signal between low level and high level, namely oscillator signal cannot maintain low level or high level (low level in the present invention and high level refer to low level in DLC (digital logic circuit) and high level before time delay arrives, and low level is 0 ~ 0.25V, high level is 3.5V ~ 5V), therefore the voltage jump of the uncontrollable DOUT pin of time delayed signal, as shown in Figure 2.Therefore, need two different signals respectively control DOUT pin voltage jump and the adjustable time delay of delay time is carried out to the voltage jump of DOUT pin.Due to needs increase pin, therefore need six pin chip packages to be replaced by eight pin chip packages to adapt to this seven pin circuitry newly, meanwhile, also need to change to adapt to eight new pin chips to chip internal circuits.Therefore, although achieve variable delay time, the increase of packaging cost can be caused.
Summary of the invention
The technical matters solved
The object of the invention is to solve in the prior art, if need to realize carrying out the adjustable time delay of delay time to echo signal, then need on the basis of primary circuit, have more a pin and carry out access delay device, in order to this pin had more then needs to change more expensive chip.And the circuit structure of primary circuit also needs to do corresponding modify to adapt to the chronotron accessed.This is not only consuming time, and cost can be made greatly to improve.
Technical scheme
The invention provides a kind of cycle signal generator for exporting oscillator signal a little, comprising, a little oscillation reference voltage generating unit, comparator unit and wholely involve delay unit.Oscillation reference voltage generating unit exports vibrate a little lower limit reference voltage and the upper limit reference voltage that vibrates a little a little, the absolute value of voltage difference of lower limit reference voltage and the upper limit reference voltage of vibrating a little of vibrating a little is enough little, with make to vibrate a little lower limit reference voltage and a little vibration upper limit reference voltage be logic low or simultaneously for logic high simultaneously; An input end of comparator unit is connected with the output terminal of oscillation reference voltage generating unit a little, and another input end of comparator unit is connected with oscillator signal a little; The output terminal of the whole input end and comparator unit that involve delay unit is connected, the whole output terminal involving delay unit is by the output terminal as cycle signal generator, for exporting oscillator signal a little, wherein, oscillator signal periodically vibrates at the lower limit reference voltage and vibrating a little between upper limit reference voltage of vibrating a little a little.
Oscillation reference voltage generating unit a little, comprising: vibrate lower limit reference voltage source a little, for generation of the lower limit reference voltage that vibrates a little; The upper limit of vibrating a little reference voltage source, for generation of the upper limit reference voltage that vibrates a little.And comparator unit is comparer, the source of comparer is connected with the upper limit reference voltage source that vibrates a little, and comparator unit exports the voltage compare result of vibrate a little lower limit reference voltage and the voltage of oscillator signal a little.Wherein, the upper limit reference voltage source that vibrates a little is the power supply of powering to cycle signal generator, and the upper limit reference voltage that vibrates a little is the voltage of power supply.
Wholely involve delay unit, comprising: constant time lag electronic circuit, the input end of constant time lag electronic circuit is connected, for generation of constant time lag by the output terminal as the whole input end and comparer that involve delay unit; Whole marble circuit, the input end of whole marble circuit is connected with the output terminal of constant time lag electronic circuit, carries out whole ripple for the signal exported constant time lag electronic circuit, and exports the signal after whole ripple; With adjustable delay electronic circuit, the input end of adjustable delay electronic circuit is connected with the output terminal of whole marble circuit, and the output terminal of adjustable delay electronic circuit by as the whole output terminal involving delay unit, for generation of adjustable delay, and exports oscillator signal a little.
Constant time lag electronic circuit, comprise: the first phase inverter, the input end of the first phase inverter is connected with the output terminal of comparer by as the input end of constant time lag electronic circuit, the output terminal of the first phase inverter by the output terminal as constant time lag electronic circuit, for exporting the first anti-phase result; First current source, via the first current source, the source of the first phase inverter is connected with the upper limit reference voltage source that vibrates a little; With constant time lag electric capacity, one end of constant time lag electric capacity is connected with the output terminal of the first phase inverter, the other end ground connection of constant time lag electric capacity.Wherein, the first phase inverter is formed by N number of inverter series, and N be more than or equal to 1 odd number.
Whole marble circuit, comprising: the second phase inverter, and the input end of the second phase inverter is connected with the output terminal of constant time lag electronic circuit by the input end as whole marble circuit, for exporting the second anti-phase result; With the 3rd phase inverter, the input end of the 3rd phase inverter is connected with the output terminal of the second phase inverter, and export the 3rd anti-phase result, the output terminal of the 3rd phase inverter is by the output terminal as whole marble circuit.Wherein, the second phase inverter and the 3rd phase inverter are formed by P, Q inverter series respectively, and P, Q are respectively the odd number being more than or equal to 1.
Adjustable delay electronic circuit, comprising: the second current source; First delay switch, the grid of the first delay switch is connected with the output terminal of whole marble circuit, and the source electrode of the first delay switch is connected with the upper limit reference voltage source that vibrates a little, and the drain electrode of the first delay switch is connected with oscillator signal a little; Second delay switch, the grid of the second delay switch is connected with the output terminal of whole marble circuit, and the source electrode of the second delay switch is connected to the ground via the second current source, and the drain electrode of the second delay switch is connected with oscillator signal a little; With adjustable delay electric capacity, one end of adjustable delay electric capacity is connected with the upper limit reference voltage source that vibrates a little, and the other end of adjustable delay electric capacity is connected with oscillator signal a little.Wherein, adjustable delay electric capacity is connected on the upper limit reference voltage source and a little between oscillator signal of vibrating a little removedly.
The invention provides a kind of cycle signal generator, this cycle signal generator performs following steps:
Constant time lag generating step, when oscillator signal a little voltage drop to lower than vibrate a little lower limit reference voltage time, constant time lag generating step starts, comparer exports high level to the first phase inverter, the output saltus step of the first phase inverter is low level, then, first current source is to constant time lag capacitor charging, the output of the first phase inverter is risen gradually from low level, now, second phase inverter exports high level, 3rd phase inverter output low level, and control the first delay switch conducting, second delay switch disconnects, the voltage of oscillator signal sports when the first delay switch conducting and vibrates upper limit reference voltage a little and maintain the upper limit reference voltage that vibrates a little a little, when the voltage of constant time lag electric capacity is risen gradually by the first current source charging and is arrived the threshold voltage of the second phase inverter, constant time lag generating step terminates,
First adjustable delay generating step, while constant time lag generating step terminates, first adjustable delay generating step starts, now, second phase inverter output low level, 3rd phase inverter exports high level, and control the first delay switch disconnection, second delay switch conducting, adjustable delay electric capacity slowly discharges via the second delay switch and the second current source, the voltage of oscillator signal slowly declines from the upper limit reference voltage that vibrates a little a little, when the voltage of oscillator signal a little slowly drop to lower than vibrate a little lower limit reference voltage time, first adjustable delay generating step terminates,
While the first adjustable delay generating step terminates, constant time lag generating step starts, and then, repetitive cycling performs constant time lag generating step and the first adjustable delay generating step, thus produces oscillator signal a little.
Wherein, the first delay switch is P channel-type metal-oxide-semiconductor; And the second delay switch is N channel-type metal-oxide-semiconductor.
Present invention also offers a kind of cycle signal generator, in this cycle signal generator, oscillation reference voltage generating unit is two limit reference voltage sources a little, and the signal for inputting based on the input end from two limit reference voltage source controls to export vibrate a little lower limit reference voltage or the upper limit reference voltage that vibrates a little.Comparator unit, comprising: the first phase inverter, and the output terminal of the first phase inverter is connected with the input end of two limit reference voltage source; With comparer electronic circuit, comparer electronic circuit is that input off-set voltage is variable, the output terminal of comparer electronic circuit is connected with the input end of the first phase inverter by the output terminal as comparator unit, an input end of comparer electronic circuit is connected with the output terminal of two limit reference voltage source by an input end as comparator unit, and another input end of comparer electronic circuit is connected with oscillator signal a little by another input end as comparator unit.Wherein, the first phase inverter is formed by M inverter series, and M be more than or equal to 1 odd number.
Wholely involve delay unit, comprising: whole marble circuit, the whole input end of marble circuit is connected with the output terminal of comparator unit, carries out whole ripple for the signal exported comparator unit, and exports the signal after whole ripple; With adjustable delay electronic circuit, the input end of adjustable delay electronic circuit is connected with the output terminal of whole marble circuit, and the output terminal of adjustable delay electronic circuit by as the whole output terminal involving delay unit, for generation of adjustable delay, and exports oscillator signal a little.
Comparer electronic circuit, comprising: comparer, and "+" input end of comparer is connected with the output terminal of two limit reference voltage source by an input end as comparer electronic circuit, and the output terminal of comparer is by the output terminal as comparer electronic circuit; Single-pole double-throw switch (SPDT), the not moved end of single-pole double-throw switch (SPDT) is connected with oscillator signal a little, and a moved end of single-pole double-throw switch (SPDT) is held with "-" of comparer and is connected; Input off-set voltage electronic circuit, one end of input off-set voltage electronic circuit is held with "-" of comparer and is connected, and the other end of input off-set voltage electronic circuit is connected with another moved end of single-pole double-throw switch (SPDT); 4th resistance, one end of the 4th resistance is connected with the output terminal of comparer; First electric capacity, one end of the first electric capacity is connected with the other end of the 4th resistance, the other end ground connection of the first electric capacity; Second phase inverter, the input end of the second phase inverter is connected with the tie point of the first electric capacity with the 4th resistance; With the 3rd phase inverter, the input end of the 3rd phase inverter is connected with the output terminal of the second phase inverter, the output terminal of the 3rd phase inverter is connected with the control end of single-pole double-throw switch (SPDT), and single-pole double-throw switch (SPDT) controls an access moved end of single-pole double-throw switch (SPDT) or another moved end of single-pole double-throw switch (SPDT) based on the output of the 3rd phase inverter.Wherein, the second phase inverter and the 3rd phase inverter are formed by R, S inverter series respectively, and R, S are respectively the odd number being more than or equal to 1.
Whole marble circuit comprises the 4th phase inverter, and the input end of the 4th phase inverter is by the input end as whole marble circuit, and the output terminal of the 4th phase inverter is by the output terminal as whole marble circuit.Wherein, the 4th phase inverter is formed by W inverter series, and W be more than or equal to 1 odd number.
Adjustable delay electronic circuit, comprising: the second current source; First delay switch, the grid of the first delay switch is connected with the output terminal of whole marble circuit, and the source electrode of the first delay switch is connected with power supply, and the drain electrode of the first delay switch is connected with oscillator signal a little; Second delay switch, the grid of the second delay switch is connected with the output terminal of whole marble circuit, and the source electrode of the second delay switch is connected to the ground via the second current source, and the drain electrode of the second delay switch is connected with oscillator signal a little; With adjustable delay electric capacity, one end of adjustable delay electric capacity is connected with power supply, and the other end of adjustable delay electric capacity is connected with oscillator signal a little.Wherein, adjustable delay electric capacity is connected on power supply and a little between oscillator signal removedly.
Cycle signal generator provided by the present invention performs the second adjustable delay generating step.Second adjustable delay generating step comprises the first time delay sub-step and the second time delay sub-step.
When oscillator signal a little voltage drop to lower than vibrate a little lower limit reference voltage time, first time delay sub-step starts, now, a moved end of single-pole double-throw switch (SPDT) is access in "-" end of comparer, comparer exports high level, at this moment, on the one hand, first phase inverter output low level is to two limit reference voltage source, thus control two limit reference voltage source exports the upper limit reference voltage that vibrates a little, on the one hand, first electric capacity charges via the 4th resistance, the voltage of the tie point of the 4th resistance and the first electric capacity is raised, when before threshold voltage higher than the second phase inverter of the voltage of the tie point of the 4th resistance and the first electric capacity, second phase inverter exports high level, 3rd phase inverter output low level thus control "-" end that a moved end of single-pole double-throw switch (SPDT) is access in comparer, when after the first capacitor charging to threshold voltage higher than the second phase inverter of the voltage of the tie point of the 4th resistance and the first electric capacity, second phase inverter output low level, 3rd phase inverter exports high level thus "-" that another moved end controlling single-pole double-throw switch (SPDT) is access in comparer via input off-set voltage electronic circuit holds, and before input off-set voltage electronic circuit is switched on, two limit reference voltage source has completed output and to have vibrated a little upper limit reference voltage, on the other hand, the 4th phase inverter output low level, thus control the first delay switch conducting, the second delay switch disconnection, make the voltage rise of oscillator signal a little.
When the voltage rise of oscillator signal is a little to the upper limit reference voltage that vibrates a little, the first time delay sub-step terminates, and the second time delay sub-step starts, comparer output low level.At this moment, on the one hand, comparer exports high level to two limit reference source, thus control two limit reference voltage source exports the lower limit reference voltage that vibrates a little, on the one hand, first electric capacity is via the 4th conductive discharge, the voltage of the tie point of the 4th resistance and described first electric capacity is reduced, when before threshold voltage lower than the second phase inverter of the voltage of the tie point of the 4th resistance and the first electric capacity, second phase inverter output low level, 3rd phase inverter exports high level thus "-" that another moved end controlling single-pole double-throw switch (SPDT) is access in comparer via input off-set voltage electronic circuit holds, when after threshold voltage lower than the second phase inverter of the voltage of the tie point of the 4th resistance and the first electric capacity, second phase inverter exports high level, 3rd phase inverter output low level thus control "-" end that a moved end of single-pole double-throw switch (SPDT) is access in comparer, and before input off-set voltage electronic circuit is disconnected, two limit reference voltage source has completed output and to have vibrated a little lower limit reference voltage, on the other hand, 4th phase inverter exports high level, thus control the first delay switch disconnection, the second delay switch conducting, adjustable delay electric capacity is via the second delay switch and the electric discharge of the second current source, the voltage of oscillator signal starts to decline a little, when oscillator signal a little voltage drop to lower than vibrate a little lower limit reference voltage time, the second time delay sub-step terminates, and the first time delay sub-step starts again.
Then, alternately perform the first time delay sub-step and the second time delay sub-step, thus produce oscillator signal a little.
Wherein, the first delay switch is P channel-type metal-oxide-semiconductor; And the second delay switch is N channel-type metal-oxide-semiconductor.
Two limit reference voltage source, comprise the first resistance, second resistance, first field effect transistor, 3rd resistance, two limit reference voltage source switch, amplifier and direct voltage source, first resistance and the second resistance form series circuit, one end near the first resistance of series circuit is connected with the power supply of powering to cycle signal generator, the other end near the second resistance of series circuit is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is connected with one end of the 3rd resistance, the other end ground connection of the 3rd resistance, the grid of the first field effect transistor is connected with the output terminal of amplifier, "+" input end of amplifier is connected with the positive pole of direct voltage source, the minus earth of direct voltage source, "-" ground connection of amplifier, the grid of two limit reference voltage source switch is connected with the output terminal of the first phase inverter, the source electrode of two limit reference voltage source switch is connected with power supply, the drain electrode of two limit reference voltage source switch is connected with the tie point of the first resistance with the second resistance, second resistance is limit the output terminal of reference voltage source to be connected with an input end of comparer electronic circuit with the tie point of the drain electrode of the first field effect transistor by as two.
Wherein, the first field effect transistor is N channel-type metal-oxide-semiconductor; And two limit reference voltage source switch is P channel-type metal-oxide-semiconductor.
Two limit reference voltage source, comprising: the 5th phase inverter, and the input end of the 5th phase inverter is connected with the output terminal of the first phase inverter; Single-chip microcomputer, first external interrupt input end of single-chip microcomputer is connected with the output terminal of the first phase inverter, being connected with the output terminal of the 5th phase inverter of second external interrupt input end of single-chip microcomputer, in the storage unit of single-chip microcomputer, store the value of vibrate a little lower limit reference voltage and vibration upper limit reference voltage a little with binary digital form; And digital to analog converter, the input end of digital to analog converter is connected with the output terminal of single-chip microcomputer, and the output terminal of digital to analog converter is by the output terminal as two limit reference voltage source.Wherein, when single-chip microcomputer responds the interruption of the first external interrupt input end, single-chip microcomputer exports the binary data of the value of the lower limit reference voltage that vibrates a little to digital to analog converter, and the value that the binary data of the value of the lower limit reference voltage that vibrates a little is converted to the lower limit reference voltage that vibrates a little by digital to analog converter exports to comparator unit; When single-chip microcomputer responds the interruption of the second external interrupt input end, single-chip microcomputer exports the binary data of the value of the upper limit reference voltage that vibrates a little to digital to analog converter, and the value that the binary data of the value of the upper limit reference voltage that vibrates a little is converted to the upper limit reference voltage that vibrates a little by digital to analog converter exports to comparator unit.
Beneficial effect
The periodic signal that cycle signal generator provided by the present invention produces periodically vibrates at the lower limit reference voltage and vibrating a little between upper limit reference voltage of vibrating a little, due in the present invention vibrate a little lower limit reference voltage and the difference of vibrating between upper limit reference voltage a little very little, make to vibrate a little lower limit reference voltage and the upper limit reference voltage that vibrates a little is low level or high level, and the periodic signal that namely cycle signal generator provided by the present invention produces remains at high level or remains on low level in oscillatory process.Employ the time-delay mechanism of cycle signal generator of the present invention, without the need to increasing extra pin, but on primary circuit, add the time-delay mechanism employing cycle signal generator of the present invention, by directly delay capacitor being accessed echo signal, the control signal of the voltage jump of control DOUT pin and time delayed signal is made to be combined into a composite signal.Thus, the adjustable time delay of delay time can not only be carried out by changing external delay capacitor to realize to the voltage jump of echo signal, but also delay time accurately can be realized.
Accompanying drawing explanation
Chip pin schematic diagram after Fig. 1 shows in prior art and accesses adjustable delay electric capacity;
Fig. 2 shows the integration schematic diagram of each signal in prior art;
Fig. 3 shows the chip pin schematic diagram after according to access adjustable delay electric capacity of the present invention;
Fig. 4 shows the schematic block diagram according to cycle signal generator of the present invention;
Fig. 5 shows the schematic block diagram according to the first embodiment of the present invention;
Fig. 6 shows the circuit diagram according to the first embodiment of the present invention;
Fig. 7 shows the oscillogram of the DOUT signal of the output according to the first embodiment of the present invention;
Fig. 8 shows DOUT voltage, a little vibration lower limit reference voltage, voltage comparator output voltage, the first inverter output voltage, the second inverter output voltage and the 3rd inverter output voltage time dependent simulation waveform respectively according to the first embodiment of the present invention;
Fig. 9 shows schematic block diagram according to a second embodiment of the present invention;
Figure 10 shows circuit diagram according to a second embodiment of the present invention;
Figure 11 shows the oscillogram of the DOUT signal of output according to a second embodiment of the present invention;
Figure 12 shows the oscillogram of the partial enlargement of the oscillogram of the DOUT signal of output according to a second embodiment of the present invention;
Figure 13 shows circuit diagram according to the third embodiment of the invention;
Figure 14 shows the schematic block diagram of example according to a modification of this invention;
Figure 15 shows the circuit diagram of example according to a modification of this invention; With
Figure 16 shows the DOUT signal of example and the oscillogram of logical signal X according to a modification of this invention.
Embodiment
Below with reference to the accompanying drawings specific embodiments of the invention are described in detail.
Fig. 3 shows the chip pin schematic diagram after according to access adjustable delay electric capacity of the present invention.As shown in Figure 3, adjustable delay electric capacity C2 is connected on DOUT and power supply V dDbetween, thus eliminate CCT pin as shown in Figure 1.
Fig. 4 shows the schematic block diagram according to cycle signal generator of the present invention.As shown in Figure 4, cycle signal generator according to the present invention comprises oscillation reference voltage generating unit, comparator unit and wholely involve delay unit a little.Oscillation reference voltage generating unit exports vibrate a little lower limit reference voltage and the upper limit reference voltage that vibrates a little a little, the absolute value of voltage difference of lower limit reference voltage and the upper limit reference voltage of vibrating a little of vibrating a little is enough little, with make to vibrate a little lower limit reference voltage and a little vibration upper limit reference voltage be logic low or simultaneously for logic high simultaneously; An input end of comparator unit is connected with the output terminal of oscillation reference voltage generating unit a little, and another input end of comparator unit is connected with oscillator signal a little; The output terminal of the whole input end and comparator unit that involve delay unit is connected, the whole output terminal involving delay unit is by the output terminal as cycle signal generator, for exporting oscillator signal a little, wherein, oscillator signal periodically vibrates at the lower limit reference voltage and vibrating a little between upper limit reference voltage of vibrating a little a little.
First embodiment
Fig. 5, Fig. 6, Fig. 7 and Fig. 8 respectively illustrate schematic block diagram according to the first embodiment of the present invention, circuit diagram, the oscillogram of DOUT signal of output and DOUT voltage, to vibrate lower limit reference voltage, voltage comparator output voltage, the first inverter output voltage, the second inverter output voltage and the 3rd inverter output voltage time dependent simulation waveform respectively a little.Describe in detail according to the first embodiment of the present invention below with reference to Fig. 5, Fig. 6, Fig. 7 and Fig. 8.
As shown in Figure 5, in the first embodiment of the present invention, in cycle signal generator, oscillation reference voltage generating unit a little, comprising: vibrate lower limit reference voltage source a little, for generation of the lower limit reference voltage that vibrates a little; The upper limit of vibrating a little reference voltage source, for generation of the upper limit reference voltage that vibrates a little.In the present embodiment, the upper limit reference voltage that vibrates a little is supply voltage V dD.And comparator unit is folded form comparer, the source of this folded form comparer is connected with the upper limit reference voltage source that vibrates a little, and this folded form comparer exports the voltage compare result of vibrate a little lower limit reference voltage and the voltage of oscillator signal a little.Wherein, the upper limit reference voltage source that vibrates a little is the power supply of powering to cycle signal generator, and the upper limit reference voltage that vibrates a little is the voltage of power supply.Wholely involve delay unit, comprising: constant time lag electronic circuit, the input end of this constant time lag electronic circuit is connected, for generation of constant time lag by the output terminal as the whole input end and comparer that involve delay unit; Whole marble circuit, the input end of whole marble circuit is connected with the output terminal of constant time lag electronic circuit, carries out whole ripple for the signal exported constant time lag electronic circuit, and exports the signal after whole ripple; With adjustable delay electronic circuit, the input end of this adjustable delay electronic circuit is connected with the output terminal of whole marble circuit, and the output terminal of adjustable delay electronic circuit by as the whole output terminal involving delay unit, for generation of adjustable delay, and exports oscillator signal a little.In the first embodiment of the present invention, delayed startup and halt circuit export start/stop signal oscillation reference voltage generating unit, folded form comparer and feedback counter extremely a little.When time delay starts, delayed startup and halt circuit export high level as start/stop signal.Then, cycle signal generator starts to produce oscillator signal a little.Meanwhile, folded form comparer exports Times of Feedback counter to, and the counting of Times of Feedback counter adds 1.The counts preset in the present invention is 300 times.If do not arrive 300 times after the counting of Times of Feedback counter adds 1, then delayed startup and halt circuit receive the output of Times of Feedback counter and export high level as start/stop signal, and feedback halt circuit receives the output of Times of Feedback counter and remains open state.Then, cycle signal generator produces again a unit and vibrates a little, and the counting of Times of Feedback counter adds 1.Above process constantly repeats, until the counting of Times of Feedback counter arrives 300 times after adding 1.Now, feedback halt circuit receives the output of Times of Feedback counter and is switched on, the signal that feedback halt circuit exports and a little oscillator signal compound, thus makes the level generation saltus step of oscillator signal a little.
Be illustrated in figure 6 the circuit diagram according to the first embodiment of the present invention.According in the time-delay mechanism of the present embodiment, constant time lag electronic circuit comprises: the first phase inverter, the input end of this first phase inverter is connected with the output terminal of comparer by as the input end of constant time lag electronic circuit, the output terminal of the first phase inverter by the output terminal as constant time lag electronic circuit, for exporting the first anti-phase result; First current source, via the first current source, the source of the first phase inverter is connected with the power supply of powering to this time-delay mechanism; With constant time lag electric capacity, one end of this constant time lag electric capacity is connected with the output terminal of the first phase inverter, the other end ground connection of constant time lag electric capacity.Wherein, the first phase inverter is formed by N number of inverter series, and N be more than or equal to 1 odd number.Whole marble circuit comprises: the second phase inverter, and the input end of this second phase inverter is connected with the output terminal of constant time lag electronic circuit by the input end as whole marble circuit, for exporting the second anti-phase result; With the 3rd phase inverter, the input end of the 3rd phase inverter is connected with the output terminal of the second phase inverter, and export the 3rd anti-phase result, the output terminal of the 3rd phase inverter is by the output terminal as whole marble circuit.Wherein, the second phase inverter and the 3rd phase inverter are formed by P, Q inverter series respectively, and P, Q are respectively the odd number being more than or equal to 1.Adjustable delay electronic circuit comprises: the second current source; First delay switch P1, this first delay switch P1 is P channel-type metal-oxide-semiconductor, the grid of this first delay switch P1 is connected with the output terminal of whole marble circuit, and the source electrode of the first delay switch is connected with the upper limit reference voltage source that vibrates a little, and the drain electrode of the first delay switch is connected with oscillator signal a little; Second delay switch N1, this second delay switch N1 is N channel-type metal-oxide-semiconductor, the grid of this second delay switch N1 is connected with the output terminal of whole marble circuit, and the source electrode of the second delay switch N1 is connected to the ground via the second current source, and the drain electrode of the second delay switch N1 is connected with oscillator signal a little; With adjustable delay electric capacity C2, one end of this adjustable delay electric capacity C2 is connected with the upper limit reference voltage source that vibrates a little, and the other end of adjustable delay electric capacity is connected with oscillator signal a little.Wherein, adjustable delay electric capacity is connected on the upper limit reference voltage source and a little between oscillator signal of vibrating a little removedly.
The principle of work of the time-delay mechanism according to the first embodiment of the present invention is described in detail below with reference to Fig. 6,7 and 8.When DOUT needs to become low level from high level, the control that delayed startup and halt circuit are subject to lithium battery protection circuit exports high level, and then, oscillation reference voltage generating unit, folded form comparer and Times of Feedback counter are started working a little.In invention, power supply V dDmagnitude of voltage V dD≈ 3.6V.In the present embodiment, the upper limit reference voltage that vibrates a little is supply voltage V dD, lower limit reference voltage V of vibrating a little rEFfor V dD-60mV ≈ 3.54V.
Now, the voltage of DOUT is V dD, higher than reference voltage V rEF, therefore, voltage comparator CMP output low level to the first phase inverter sum counter, and Times of Feedback counter is not triggered.Then, the first phase inverter exports high level to the second phase inverter, and the second phase inverter output low level is to the 3rd phase inverter, and the 3rd phase inverter exports the grid of high level to the first delay switch P1 and the second delay switch N1 respectively.Therefore, the first delay switch P1 turns off, the second delay switch N1 conducting.Then, because adjustable delay electric capacity C2 is via the second delay switch N1 and the second current source I s2slow electric discharge, therefore the voltage of DOUT is from V dDslow decline.
When the voltage of DOUT is from V dDslowly drop to lower than reference voltage V rEFtime, constant time lag t1 starts, and namely constant time lag generating step starts, folded form comparer exports high level to the first phase inverter and Times of Feedback counter, the output saltus step of the first phase inverter is low level, and Times of Feedback counter is triggered once, counts and becomes N+1 from N.If the counting N+1 of counter does not arrive preset times 300 times, then Times of Feedback counter output low level is to feedback halt circuit switch, and this feedback halt circuit switch remains open state.Then, the first current source I s1described constant time lag electric capacity C1 is charged, the output of the first phase inverter is risen gradually from low level, now, the second phase inverter exports high level to the 3rd phase inverter, the grid of the 3rd phase inverter difference output low level to the first delay switch P1 and the second delay switch N1.Therefore, the first delay switch P1 conducting, the second delay switch N1 turns off.The voltage of DOUT sports V when the first delay switch P1 conducting dDand maintain V dD.
When constant time lag electric capacity C1 is by the first current source I s1charge and rise to the threshold voltage V of the second phase inverter NMOS tube thNtime, constant time lag t1 terminates, and the first adjustable delay t2 starts, and namely constant time lag generating step terminates and the first adjustable delay step starts.And constant time lag t1=C1 × V thN/ I s1.In the present invention, delay time is set as 300ms.Preset times due to Times of Feedback counter is 300 times, and therefore unit delay time is 1ms.Due to C1=2pF, I s1≈ 10nA, V thN≈ 1V, therefore, constant time lag t1=C1 × V thN/ I s1≈ 200us.Second phase inverter output low level is to the 3rd phase inverter, and the 3rd phase inverter exports the grid of high level to the first delay switch P1 and the second delay switch N1 respectively.Therefore, the first delay switch P1 turns off, the second delay switch N1 conducting.Adjustable delay electric capacity C2 is via the second delay switch N1 and the second current source I s2slow electric discharge, DOUT is from V dDslow decline.
When DOUT is from V dDslowly drop to lower than reference voltage V rEFtime, the first adjustable delay t2 terminates, and constant time lag t1 starts, and namely the first adjustable delay generating step terminates and constant time lag generating step starts.In the present embodiment, due to C2=0.1uF, I s2≈ 6uA, therefore, adjustable delay t2=C2 × (V dD-V rEF)/I s2≈ 1ms.Unit delay time t unit=t1+t2 ≈ 1ms.Then, alternately repetitive cycling execution constant time lag generating step and the first adjustable delay generating step are until the counting N+1 of Times of Feedback counter arrives preset value 300 times, then Times of Feedback counter exports high level to feedback halt circuit switch, feedback halt circuit switch N2 conducting, then, DOUT is low level from high level saltus step, thus completes the time delay t to DOUT voltage jump delay=t unit× 300=(t1+t2) × 300 ≈ 300ms.So, just form the waveform as shown in Fig. 7 and Fig. 8.
According to time-delay mechanism of the present invention, arbitrary expect that the signal carrying out time delay to its voltage jump realizes the time delay to this signal voltage saltus step by being accessed by adjustable delay electric capacity C2.Further, by changing the electric capacity of adjustable delay electric capacity C2, the change to delay time can be realized.Further, can avoid because the operating rate of folded form comparer is slower than DOUT rise to V rapidly suddenly by introducing C1 dDtime speed and uncontrollable time delay of causing, and make t1 become controlled time delay, thus realize both adjustablely having time delay accurately.
Second embodiment
Describe according to a second embodiment of the present invention below with reference to Fig. 9,10,11 and 12.
Fig. 9 shows schematic block diagram according to a second embodiment of the present invention.Figure 10 shows circuit diagram according to a second embodiment of the present invention.As shown in Figures 9 and 10, in the second embodiment of the present invention, in cycle signal generator, oscillation reference voltage generating unit is two limit reference voltage sources a little, and the signal for inputting based on the input end from two limit reference voltage source controls to export lower limit reference voltage V of vibrating a little lOWERor upper limit reference voltage V of vibrating a little uPPER.This pair of limit reference voltage source comprises resistance R1, resistance R2, field effect transistor N3, resistance R3, two limit reference voltage source switch P 2, amplifier and direct voltage source LDO.
In the second embodiment of the present invention, delayed startup and halt circuit export start/stop signal oscillation reference voltage generating unit, comparer electronic circuit and feedback counter extremely a little.When time delay starts, delayed startup and halt circuit export high level as start/stop signal.Then, cycle signal generator starts to produce oscillator signal a little, and the voltage of DOUT starts to decline first.Afterwards, whenever comparer is from low transition to high level, the counting of Times of Feedback counter just adds 1.If do not arrive 300 times after the counting of Times of Feedback counter adds 1, then delayed startup and halt circuit receive the output of Times of Feedback counter and export high level as start/stop signal, and feedback halt circuit receives the output of Times of Feedback counter and remains open state.Then, cycle signal generator just creates a unit and vibrates a little.Above process constantly repeats, until the counting of Times of Feedback counter arrives 300 times after adding 1.Now, feedback halt circuit receives the output of Times of Feedback counter and is switched on, the level skip signal that feedback halt circuit exports and a little oscillator signal DOUT compound, thus makes the level generation saltus step of oscillator signal DOUT a little.
The principle of work of time-delay mechanism is according to a second embodiment of the present invention described in detail below with reference to Figure 10,11 and 12.In the present embodiment, the upper limit reference voltage that vibrates a little is V upper=VDD-20mV ≈ 3.58V, the lower limit reference voltage that vibrates a little is V lower=VDD-80mV ≈ 3.52V.A LDO structure is constituted with voltage reference Vref_lod and N3 pipe, and Vref_lod=0.6V, R1=1.38Mohm, R2=803Kohm, R3=13Mohm, thus ensure that when the non-place in circuit of R1, V rEF=3.58V, when R1 place in circuit, V rEF=3.52V.And R4=803Kohm, C3=1.5pF.4th phase inverter is that 3 phase inverters are connected successively.When DOUT needs become low level from high level and need to carry out time delay to this level saltus step; the control that delayed startup and halt circuit are subject to the control signal that lithium battery protection circuit produces exports high level to two limit reference voltage source, comparer and Times of Feedback counter, thus two limit reference voltage source, comparer and Times of Feedback counter are started working.Now, "+" input end V of comparer rEF=3.52V, the moved end b of single-pole double-throw switch (SPDT) is access in "-" input end of comparer, and the voltage of DOUT starts to decline.
When the voltage drop of DOUT is to during lower than 3.52V, the output of comparer is high level from low transition, the beginning of the first time delay sub-step of the second adjustable delay generating step, at this moment: on the one hand, first phase inverter output low level, the conducting of P2 pipe, resistance R1 is shorted, the ER effect flowing through N3 pipe is large, Vref uprises, and amplifier negative input end accepts the negative-feedback signal of R4 upper end, and amplifier output terminal regulates the grid voltage of N3 pipe, thus the electric current flowing through N3 pipe is diminished again, Vref becomes original size again.Two limit reference voltage source is regulated to export 3.58V "+" input end to comparer, on the one hand, electric capacity C3 charges via resistance R4, the voltage of the tie point of resistance R4 and electric capacity C3 rises from 0V, before the voltage of this tie point does not also rise to the threshold voltage of the second phase inverter, the output of the second phase inverter is high level, 3rd phase inverter output low level sel is to single-pole double-throw switch (SPDT), after the threshold voltage of voltage rise to the second phase inverter of this tie point, the output of the second phase inverter is low level, 3rd phase inverter exports high level sel to single-pole double-throw switch (SPDT), namely resistance R4 and electric capacity C3 produces a time delay to signal sel, make single-pole double-throw switch (SPDT) after an interval of delay just driven end b be switched to c, this is in order to ensure before single-pole double-throw switch (SPDT) switching, the P2 pipe of two limit reference voltage source, the voltage V of amplifier and output rEFswitching complete and settle out, namely completed export 3.58V, on the other hand, the 4th phase inverter output low level, the conducting of P1 pipe, N1 pipe disconnects, and DOUT signal is owing to managing and power supply V via P1 dDbe connected, the therefore voltage rise of DOUT.Because the moved end of single-pole double-throw switch (SPDT) is switched to c from b, therefore, DOUT signal to be held with "-" of comparer via input off-set voltage electronic circuit and is connected.Due to the effect of input off-set voltage electronic circuit, the voltage of DOUT the highest 3.58V of rising to time overturn immediately.
When the voltage rise of DOUT is to during higher than 3.58V, the output of comparer is low level from high level saltus step, and at this moment: on the one hand, the first phase inverter exports high level, P2 pipe disconnects, resistance R1 access circuit, the electric current flowing through N3 pipe diminishes, Vref step-down, amplifier negative input end accepts the negative-feedback signal of R4 upper end, amplifier output terminal regulates the grid voltage of N3 pipe, thus makes the electric current flowing through N3 pipe again become large, and Vref becomes original size again.Therefore two limit reference voltage source exports 3.52V "+" input end to comparer, on the one hand, electric capacity C3 discharges via resistance R4, the voltage of the tie point of resistance R4 and electric capacity C3 starts to decline, before the voltage of this tie point does not also drop to the threshold voltage of the second phase inverter, the output of the second phase inverter is low level, 3rd phase inverter exports high level sel to single-pole double-throw switch (SPDT), after the threshold voltage of voltage drop to the second phase inverter of this tie point, the output of the second phase inverter is high level, 3rd phase inverter output low level sel is to single-pole double-throw switch (SPDT), namely resistance R4 and electric capacity C3 produces a time delay to signal sel, make single-pole double-throw switch (SPDT) after an interval of delay just driven end c be switched to b, this is in order to ensure before single-pole double-throw switch (SPDT) switching, the P2 pipe of two limit reference voltage source, the voltage V of amplifier and output rEFswitching complete and settle out, namely completed export 3.52V, on the other hand, the 4th phase inverter exports high level, and P1 pipe disconnects, the conducting of N1 pipe, and adjustable delay electric capacity C2 is via N1 pipe and the second current source I s2electric discharge, the voltage of DOUT starts to decline, and the second time delay sub-step of the second adjustable delay generating step terminates, the first time delay sub-step.
Then, alternately repetitive cycling performs the first time delay sub-step and the second time delay sub-step to rolling counters forward reaches 300 times, thus produces the DOUT of oscillator signal a little expected.
In the present embodiment, the time delay t wished delay=t unit× 300=t2 × 300=C2 × (V uPPER-V lOWER)/I s2× 300 ≈ 300ms.So, just form the waveform as shown in Figure 11 and Figure 12.
3rd embodiment
Figure 13 shows circuit diagram according to the third embodiment of the invention.Because the difference of the third embodiment of the present invention and the second embodiment is only at two limit reference voltage source, therefore, omit the description to other parts of the third embodiment of the present invention and principle of work here.
Two limit reference voltage sources of the third embodiment of the present invention are described in detail below with reference to Figure 13.In the present embodiment, 8051 single-chip microprocessor MCU are used.In advance the value 3.52V of the value 3.58V of the upper limit reference voltage that vibrates a little and the lower limit reference voltage that vibrates a little is pre-stored in the storage unit of MCU with binary digital form.MCU has external interrupt INT0 and INT1, as shown in Figure 13.INT0 and INT1 can be set to level triggers form, also can be set to saltus step activation pattern.In the present embodiment, for saltus step activation pattern.
When the output of comparer is low level from high level saltus step, the output of the first phase inverter is high level from low transition, the output of the 5th phase inverter is low level from high level saltus step, therefore, MCU responds INT1 and interrupts, MCU exports the binary value of 3.52V to digital to analog converter DAC, and binary value is converted to simulation value and the 3.52V be converted to is exported to "+" input end of comparer by DAC.
When the output of comparer is high level from low transition, the output of the first phase inverter is low level from high level saltus step, the output of the 5th phase inverter is high level from low transition, therefore, MCU responds INT0 and interrupts, MCU exports the binary value of 3.58V to digital to analog converter DAC, and binary value is converted to simulation value and the 3.58V be converted to is exported to "+" input end of comparer by DAC.
Variation
Figure 14,15 and 16 respectively illustrates the schematic block diagram of example, the oscillogram of circuit diagram and DOUT signal and logical signal X according to a modification of this invention.Because the difference of variation of the present invention and the first embodiment is only at driving circuit and logical signal X circuit for generating, therefore, the description of other parts to variation example of the present invention and principle of work is omitted here.
As shown in figure 15, in this variation, before rolling counters forward reaches 300 times, counter is output low level always, and driving circuit switch N2 is in off-state, and the tie point of N2 and driving circuit resistance R1 is high level, because two input ends of logical AND gate are high level, therefore, export high level with door, logical signal X is in high level always.Once rolling counters forward reaches 300 times, counter just exports high level, driving circuit switch N2 conducting, the tie point of N2 and driving circuit resistance R1 becomes low level, two input ends one due to logical AND gate are high level one is low level, therefore, with door output low level, therefore, logical signal X saltus step is low level.The difference of this variation and the first embodiment is, desired having concurrently in the first embodiment is vibrated by this variation a little and the DOUT signal decomposition of the characteristic of generation saltus step is have the DOUT signal of oscillating characteristic a little and the logical signal X of the characteristic of generation saltus step when having in rolling counters forward to 300 time when rolling counters forward to 300 time.Thus the oscillogram of the DOUT signal created as shown in figure 16 and logical signal X.
The present invention is not limited to the embodiment of above-mentioned concrete announcement, such as, is also applicable to produce low level oscillator signal a little.Those skilled in the art without departing from the spirit and scope of the present invention, can carry out various change, replacement and change to it.

Claims (18)

1. for exporting a cycle signal generator for oscillator signal a little, comprising, a little oscillation reference voltage generating unit, comparator unit and wholely involve delay unit, it is characterized in that,
The described voltage generating unit of oscillation reference a little exports vibrate a little lower limit reference voltage and the upper limit reference voltage that vibrates a little, the absolute value of the voltage difference of described vibrate a little lower limit reference voltage and the described upper limit reference voltage of vibrating a little is enough little, with vibrate a little described in making lower limit reference voltage and the described upper limit reference voltage that vibrates a little simultaneously for logic low or simultaneously for logic high;
An input end of described comparator unit is connected with the output terminal of the described voltage generating unit of oscillation reference a little, and another input end of described comparator unit is connected with described oscillator signal a little;
The described whole input end involving delay unit is connected with the output terminal of described comparator unit, the described whole output terminal involving delay unit by the output terminal as described cycle signal generator, for oscillator signal a little described in exporting, wherein,
Described oscillator signal a little periodically vibrates described vibration a little between lower limit reference voltage and the described upper limit of vibration a little reference voltage.
2. cycle signal generator as claimed in claim 1, is characterized in that,
The described voltage generating unit of oscillation reference a little, comprises
Vibrate lower limit reference voltage source a little, for generation of the described lower limit reference voltage that vibrates a little, and
Vibrate upper limit reference voltage source a little, for generation of the described upper limit reference voltage that vibrates a little; And
Described comparator unit is comparer, and the source of described comparer is connected with the described upper limit reference voltage source that vibrates a little, the voltage compare result of the voltage of vibrate a little described in described comparator unit exports lower limit reference voltage and described oscillator signal a little, wherein,
The described upper limit reference voltage source that vibrates a little is the power supply of powering to described cycle signal generator, and the described upper limit reference voltage that vibrates a little is the voltage of described power supply.
3. cycle signal generator as claimed in claim 1 or 2, is characterized in that,
Describedly wholely involve delay unit, comprise
Constant time lag electronic circuit, the input end of described constant time lag electronic circuit is connected, for generation of constant time lag by the output terminal as the described whole input end and comparer that involve delay unit;
Whole marble circuit, the input end of described whole marble circuit is connected with the output terminal of described constant time lag electronic circuit, carries out whole ripple for the signal exported described constant time lag electronic circuit, and exports the signal after whole ripple; With
Adjustable delay electronic circuit, the input end of described adjustable delay electronic circuit is connected with the output terminal of described whole marble circuit, the output terminal of described adjustable delay electronic circuit by as the described whole output terminal involving delay unit, for generation of adjustable delay, and oscillator signal a little described in exporting.
4. cycle signal generator as claimed in claim 3, is characterized in that,
Described constant time lag electronic circuit, comprises
First phase inverter, the input end of described first phase inverter is connected with the output terminal of described comparer by the input end as described constant time lag electronic circuit, the output terminal of described first phase inverter by the output terminal as described constant time lag electronic circuit, for exporting the first anti-phase result;
First current source, via described first current source, the source of described first phase inverter is connected with the described upper limit reference voltage source that vibrates a little; With
Constant time lag electric capacity, one end of described constant time lag electric capacity is connected with the output terminal of described first phase inverter, the other end ground connection of described constant time lag electric capacity, wherein,
Described first phase inverter is formed by N number of inverter series, and N be more than or equal to 1 odd number.
5. cycle signal generator as claimed in claim 3, is characterized in that,
Described whole marble circuit, comprises
Second phase inverter, the input end of described second phase inverter is connected with the output terminal of described constant time lag electronic circuit by the input end as described whole marble circuit, for exporting the second anti-phase result; With
3rd phase inverter, the input end of described 3rd phase inverter is connected with the output terminal of described second phase inverter, export the 3rd anti-phase result, the output terminal of described 3rd phase inverter by the output terminal as described whole marble circuit, wherein,
Described second phase inverter and described 3rd phase inverter are formed by P, Q inverter series respectively, and P, Q are respectively the odd number being more than or equal to 1.
6. cycle signal generator as claimed in claim 3, is characterized in that,
Described adjustable delay electronic circuit, comprises
Second current source,
First delay switch, the grid of described first delay switch is connected with the output terminal of described whole marble circuit, the source electrode of described first delay switch is connected with the described upper limit reference voltage source that vibrates a little, and the drain electrode of described first delay switch is connected with described oscillator signal a little
Second delay switch, the grid of described second delay switch is connected with the output terminal of described whole marble circuit, the source electrode of described second delay switch is connected to the ground via described second current source, and the drain electrode of described second delay switch is connected with described oscillator signal a little, and
Adjustable delay electric capacity, one end of described adjustable delay electric capacity is connected with the described upper limit reference voltage source that vibrates a little, and the other end of described adjustable delay electric capacity is connected with described oscillator signal a little, wherein,
Vibrate described in described adjustable delay electric capacity is connected on removedly upper limit reference voltage source and described a little between oscillator signal a little.
7. the cycle signal generator according to any one of claim 4-6, is characterized in that, described cycle signal generator performs following steps:
Constant time lag generating step, when the voltage drop of described oscillator signal is a little to during lower than the described lower limit reference voltage of vibration a little, described constant time lag generating step starts, described comparer exports high level to described first phase inverter, the output saltus step of described first phase inverter is low level, then, described first current source is to described constant time lag capacitor charging, the output of described first phase inverter is risen gradually from low level, now, described second phase inverter exports high level, described 3rd phase inverter output low level, and control described first delay switch conducting, described second delay switch disconnects, vibrate described in the voltage of described oscillator signal a little sports when described first delay switch conducting upper limit reference voltage the upper limit reference voltage that vibrates a little described in maintaining a little, when the voltage of described constant time lag electric capacity is risen gradually by described first current source charging and is arrived the threshold voltage of described second phase inverter, described constant time lag generating step terminates,
First adjustable delay generating step, while described constant time lag generating step terminates, described first adjustable delay generating step starts, now, described second phase inverter output low level, described 3rd phase inverter exports high level, and control described first delay switch disconnection, described second delay switch conducting, described adjustable delay electric capacity slowly discharges via described second delay switch and described second current source, the voltage of described oscillator signal a little slowly declines from the described upper limit reference voltage that vibrates a little, when the voltage of described oscillator signal a little slowly drops to lower than the described lower limit reference voltage of vibration a little, described first adjustable delay generating step terminates,
While described first adjustable delay generating step terminates, described constant time lag generating step starts, and then, repetitive cycling performs described constant time lag generating step and described first adjustable delay generating step, thus oscillator signal a little described in producing.
8. cycle signal generator as claimed in claim 7, is characterized in that,
Described first delay switch is P channel-type metal-oxide-semiconductor; And
Described second delay switch is N channel-type metal-oxide-semiconductor.
9. cycle signal generator as claimed in claim 1, is characterized in that,
The described voltage generating unit of oscillation reference is a little pair limit reference voltage sources, for controlling based on the signal of the input end input from described two limit reference voltage source vibrate a little described in output lower limit reference voltage or the described upper limit reference voltage that vibrates a little;
Described comparator unit, comprises
First phase inverter, the output terminal of described first phase inverter limits the input end of reference voltage source to be connected with described pair, and
Comparer electronic circuit, described comparer electronic circuit is that input off-set voltage is variable, the output terminal of described comparer electronic circuit is connected with the input end of described first phase inverter by the output terminal as described comparator unit, an input end of described comparer electronic circuit is limit the output terminal of reference voltage source to be connected by an input end as described comparator unit with described pair, another input end of described comparer electronic circuit is connected with described oscillator signal a little by another input end as described comparator unit, wherein
Described first phase inverter is formed by M inverter series, and M be more than or equal to 1 odd number.
10. cycle signal generator as claimed in claim 1, is characterized in that,
Describedly wholely involve delay unit, comprise
Whole marble circuit, the input end of described whole marble circuit is connected with the output terminal of described comparator unit, carries out whole ripple for the signal exported described comparator unit, and exports the signal after whole ripple; With
Adjustable delay electronic circuit, the input end of described adjustable delay electronic circuit is connected with the output terminal of described whole marble circuit, the output terminal of described adjustable delay electronic circuit by as the described whole output terminal involving delay unit, for generation of adjustable delay, and oscillator signal a little described in exporting.
11. cycle signal generators as claimed in claim 9, is characterized in that,
Described comparer electronic circuit, comprises
Comparer, "+" input end of described comparer is limit the output terminal of reference voltage source to be connected by an input end as described comparer electronic circuit with described pair, and the output terminal of described comparer is by the output terminal as described comparer electronic circuit;
Single-pole double-throw switch (SPDT), the not moved end of described single-pole double-throw switch (SPDT) is connected with described oscillator signal a little, and a moved end of described single-pole double-throw switch (SPDT) is held with "-" of described comparer and is connected;
Input off-set voltage electronic circuit, one end of described input off-set voltage electronic circuit is held with "-" of described comparer and is connected, and the other end of described input off-set voltage electronic circuit is connected with another moved end of described single-pole double-throw switch (SPDT);
4th resistance, one end of described 4th resistance is connected with the output terminal of described comparer;
First electric capacity, one end of described first electric capacity is connected with the other end of described 4th resistance, the other end ground connection of described first electric capacity;
Second phase inverter, the input end of described second phase inverter is connected with the tie point of described first electric capacity with described 4th resistance; With
3rd phase inverter, the input end of described 3rd phase inverter is connected with the output terminal of described second phase inverter, the output terminal of described 3rd phase inverter is connected with the control end of described single-pole double-throw switch (SPDT), described single-pole double-throw switch (SPDT) controls to access a moved end of described single-pole double-throw switch (SPDT) or another moved end of described single-pole double-throw switch (SPDT) based on the output of described 3rd phase inverter, wherein
Described second phase inverter and described 3rd phase inverter are formed by R, S inverter series respectively, and R, S are respectively the odd number being more than or equal to 1.
12. cycle signal generators as claimed in claim 10, is characterized in that,
Described whole marble circuit comprises the 4th phase inverter, the input end of described 4th phase inverter by the input end as described whole marble circuit, the output terminal of described 4th phase inverter by the output terminal as described whole marble circuit, wherein,
Described 4th phase inverter is formed by W inverter series, and W be more than or equal to 1 odd number.
13. cycle signal generators as claimed in claim 10, is characterized in that,
Described adjustable delay electronic circuit, comprises
Second current source,
First delay switch, the grid of described first delay switch is connected with the output terminal of described whole marble circuit, and the source electrode of described first delay switch is connected with described power supply, and the drain electrode of described first delay switch is connected with described oscillator signal a little,
Second delay switch, the grid of described second delay switch is connected with the output terminal of described whole marble circuit, the source electrode of described second delay switch is connected to the ground via described second current source, and the drain electrode of described second delay switch is connected with described oscillator signal a little, and
Adjustable delay electric capacity, one end of described adjustable delay electric capacity is connected with described power supply, and the other end of described adjustable delay electric capacity is connected with described oscillator signal a little, wherein,
Described adjustable delay electric capacity is connected on described power supply and described a little between oscillator signal removedly.
14. cycle signal generators according to any one of claim 11-13, it is characterized in that, described cycle signal generator performs the second adjustable delay generating step:
Second adjustable delay generating step comprises the first time delay sub-step and the second time delay sub-step,
When the voltage drop of described oscillator signal is a little to during lower than the described lower limit reference voltage of vibration a little, described first time delay sub-step starts, now, a moved end of described single-pole double-throw switch (SPDT) is access in "-" end of described comparer, described comparer exports high level, at this moment
On the one hand, the extremely described two limit reference voltage source of described first phase inverter output low level, thus control to vibrate a little described in the output of described two limit reference voltage source upper limit reference voltage;
On the one hand, described first electric capacity, via described 4th resistance charging, makes the voltage of the tie point of described 4th resistance and described first electric capacity raise,
When before threshold voltage higher than described second phase inverter of the voltage of the tie point of described 4th resistance and described first electric capacity, described second phase inverter exports high level, described 3rd phase inverter output low level thus the described moved end controlling described single-pole double-throw switch (SPDT) are access in "-" end of described comparer
When after described first capacitor charging to threshold voltage higher than described second phase inverter of the voltage of the tie point of described 4th resistance and described first electric capacity, described second phase inverter output low level, described 3rd phase inverter exports high level thus "-" that another moved end controlling described single-pole double-throw switch (SPDT) is access in described comparer via described input off-set voltage electronic circuit holds, and before described input off-set voltage electronic circuit is switched on, described two limit reference voltage source has completed the upper limit reference voltage that to vibrate a little described in output;
On the other hand, described 4th phase inverter output low level, thus control described first delay switch conducting, described second delay switch disconnects, the voltage rise of oscillator signal a little described in making,
When the voltage rise of described oscillator signal is a little to the described upper limit reference voltage that vibrates a little, described first time delay sub-step terminates, and described second time delay sub-step starts, described comparer output low level; At this moment,
On the one hand, described comparer exports the extremely two limit reference source of high level, thus controls to vibrate a little described in the output of described two limit reference voltage source lower limit reference voltage;
On the one hand, described first electric capacity, via described 4th conductive discharge, makes the voltage of the tie point of described 4th resistance and described first electric capacity reduce,
When before threshold voltage lower than described second phase inverter of the voltage of the tie point of described 4th resistance and described first electric capacity, described second phase inverter output low level, described 3rd phase inverter exports high level thus "-" that another moved end controlling described single-pole double-throw switch (SPDT) is access in described comparer via described input off-set voltage electronic circuit holds
When after threshold voltage lower than described second phase inverter of the voltage of the tie point of described 4th resistance and described first electric capacity, described second phase inverter exports high level, described 3rd phase inverter output low level thus the moved end controlling described single-pole double-throw switch (SPDT) are access in "-" end of described comparer, and before described input off-set voltage electronic circuit is disconnected, described two limit reference voltage source has completed the lower limit reference voltage that to vibrate a little described in output;
On the other hand, described 4th phase inverter exports high level, thus control described first delay switch disconnection, described second delay switch conducting, described adjustable delay electric capacity is via described second delay switch and described second current source electric discharge, the voltage of described oscillator signal a little starts to decline, when the voltage drop of described oscillator signal is a little to during lower than the described lower limit reference voltage of vibration a little, described second time delay sub-step terminates, and described first time delay sub-step starts again;
Then, alternately perform described first time delay sub-step and the second time delay sub-step, thus oscillator signal a little described in producing.
15. cycle signal generators as claimed in claim 14, is characterized in that,
Described first delay switch is P channel-type metal-oxide-semiconductor; And
Described second delay switch is N channel-type metal-oxide-semiconductor.
16. cycle signal generators as claimed in claim 9, is characterized in that,
Described two limit reference voltage source, comprise the first resistance, second resistance, first field effect transistor, 3rd resistance, two limit reference voltage source switch, amplifier and direct voltage source, described first resistance and described second resistance form series circuit, one end of close described first resistance of described series circuit is connected with the power supply of powering to described cycle signal generator, the other end of close described second resistance of described series circuit is connected with the drain electrode of described first field effect transistor, the source electrode of described first field effect transistor is connected with one end of described 3rd resistance, the other end ground connection of described 3rd resistance, the grid of described first field effect transistor is connected with the output terminal of described amplifier, "+" input end of described amplifier is connected with the positive pole of described direct voltage source, the minus earth of described direct voltage source, "-" ground connection of described amplifier, the grid of described two limit reference voltage source switch is connected with the output terminal of described first phase inverter, the source electrode of described two limit reference voltage source switch is connected with described power supply, the drain electrode of described two limit reference voltage source switch is connected with the tie point of described first resistance with described second resistance, described second resistance is limit the output terminal of reference voltage source to be connected with an input end of described comparer electronic circuit with the tie point of the drain electrode of described first field effect transistor by as described pair.
17. cycle signal generators as claimed in claim 16, is characterized in that,
Described first field effect transistor is N channel-type metal-oxide-semiconductor; And
Described two limit reference voltage source switch is P channel-type metal-oxide-semiconductor.
18. cycle signal generators as claimed in claim 9, is characterized in that,
Described two limit reference voltage source, comprises
5th phase inverter, the input end of described 5th phase inverter is connected with the output terminal of described first phase inverter;
Single-chip microcomputer, first external interrupt input end of described single-chip microcomputer is connected with the output terminal of described first phase inverter, being connected with the output terminal of described 5th phase inverter of second external interrupt input end of described single-chip microcomputer, the value of vibrate a little described in storing with binary digital form in the storage unit of described single-chip microcomputer lower limit reference voltage and the described upper limit reference voltage that vibrates a little; With
Digital to analog converter, the input end of described digital to analog converter is connected with the output terminal of described single-chip microcomputer, and the output terminal of described digital to analog converter is limit the output terminal of reference voltage source as described pair, wherein,
When the interruption of the described first external interrupt input end of described single-chip microcomputer response, described single-chip microcomputer exports the binary data of the value of the described lower limit reference voltage that vibrates a little to described digital to analog converter, the value of lower limit reference voltage of vibrating a little described in the binary data of the value of the described lower limit reference voltage of vibrating a little is converted to by described digital to analog converter exports to described comparator unit
When the interruption of the described second external interrupt input end of described single-chip microcomputer response, described single-chip microcomputer exports the binary data of the value of the described upper limit reference voltage that vibrates a little to described digital to analog converter, and the value of the upper limit reference voltage that vibrates a little described in the binary data of the value of the described upper limit reference voltage that vibrates a little is converted to by described digital to analog converter exports to described comparator unit.
CN201310285321.6A 2013-07-08 2013-07-08 Periodic signal generating device Pending CN104282328A (en)

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CN114449698A (en) * 2021-02-05 2022-05-06 成都芯源系统有限公司 LED driving system, feedback control circuit thereof and feedback signal generation method

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US6215361B1 (en) * 1996-09-09 2001-04-10 Sgs-Thomson Microelectronics S.A. Phase-locked loop with a charge pump current limiting device
CN101562442A (en) * 2009-03-30 2009-10-21 Bcd半导体制造有限公司 Frequency jittering circuit and low-frequency triangle wave generator

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US6215361B1 (en) * 1996-09-09 2001-04-10 Sgs-Thomson Microelectronics S.A. Phase-locked loop with a charge pump current limiting device
CN101562442A (en) * 2009-03-30 2009-10-21 Bcd半导体制造有限公司 Frequency jittering circuit and low-frequency triangle wave generator

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114449698A (en) * 2021-02-05 2022-05-06 成都芯源系统有限公司 LED driving system, feedback control circuit thereof and feedback signal generation method
CN114449698B (en) * 2021-02-05 2024-01-12 成都芯源系统有限公司 LED driving system, feedback control circuit thereof and feedback signal generation method

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