CN205883702U - Avoid via hole back drilling's PCB wiring structure - Google Patents
Avoid via hole back drilling's PCB wiring structure Download PDFInfo
- Publication number
- CN205883702U CN205883702U CN201620685094.5U CN201620685094U CN205883702U CN 205883702 U CN205883702 U CN 205883702U CN 201620685094 U CN201620685094 U CN 201620685094U CN 205883702 U CN205883702 U CN 205883702U
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- signal line
- via hole
- layer hole
- hole
- layer
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Abstract
The utility model discloses an avoid via hole back drilling's PCB wiring structure, including first clock signal and second signal line, first clock signal is connected with the via hole signal line through the first layer hole of trading, and the via hole signal line trades layer hole and second signal line connection through the second, and the first extreme point that layer hole and second traded layer hole that trades is connected respectively at the both ends of via hole signal line. The utility model discloses the problem of via hole stub overlength has effectively been solved. Easy operation, only need establish ties near original via hole a via hole can, can not increase manufacturing cost.
Description
Technical field
This utility model relates to the routing field of High-Speed PCB, specifically, relates to a kind of PCB avoiding via back drill
Wire structures.
Background technology
In printed circuit board (pcb board), signal is to be transmitted by the holding wire on PCB, by single sided board layout
The restriction in space, present PCB many employings multilayer wiring mode, what multilayer wiring mode related to holding wire changes layer, changes layer
Realized by via.
Conventional pcb board via is divided into two kinds, and a kind of do not have via stub, that includes two signals layers；Another kind of
Having via stub, it has at least three signals layer, when adjacent two signals layers carry out signal transmission, with another signals layer
Between will form via stub.Via stub is transmitted without any effect to signal, and can affect the transmission of signal, particularly
When the situation that pcb board is thicker, via stub may be the longest.When signal transmission rate is increased to a certain degree, longer mistake
Hole stub can cause Insertion Loss curve to form resonance point in lower frequency, has a strong impact on the quality of signal transmission.Resistance at via
Anti-typically can be on the low side, long via stub can make the impedance of via on the low side more serious, causes channel impedance discontinuous.At a high speed
In circuit, the adverse effect that signal is produced by the longest via of via stub, the mistake shorter than using two via stubs
Hole also wants big.
In the prior art, by adjusting cabling, selecting suitable wiring layer to avoid longer via stub to occur, but
Due to reasons such as the restriction of arrangement space and impedance control, the length of via stub can not be controlled according to the wish of people
Degree.If the length of via stub has exceeded acceptable maximum, it is necessary to use back drill technology to be removed by via stub, or
Person uses blind hole.Use original back drill technology, can increase manufacturing procedure, and have the failed risk of back drill.Use blind hole technology
Also the cost of making sheet can be greatly increased.Both structures are all unfavorable for the transmission of signal, costly and risk is big.
Drawbacks described above, is worth solving.
Summary of the invention
In order to overcome the deficiency of existing technology, this utility model provides a kind of PCB layout structure avoiding via back drill.
Technical solutions of the utility model are as described below:
A kind of PCB layout structure avoiding via back drill, it is characterised in that include the first holding wire and secondary signal line,
Described first holding wire changes layer hole by first and is connected with Via signal line, and described Via signal line changes by second
Layer hole is connected with described secondary signal line, and the two ends of described Via signal line connect described first respectively and change layer hole and described second
Change the end points in layer hole.
Further, described first holding wire connects described first another end points changing layer hole.
Further, described secondary signal line connects described second and changes the position that the middle part in layer hole is top.
Further, described secondary signal line and described second changes the length of the via stub between another end points in layer hole
Degree L meets:The unit of described signal rate is Gbps.
According to this utility model of such scheme, it has the beneficial effects that, this utility model is not changing the manufacture of via
Under technique premise, effectively reduce the length of via stub, thus it is longer to efficiently solve via stub, cause Insertion Loss curve to exist
There is the phenomenon of resonance point in lower frequency, improves through hole impedance；Further, this utility model is simple to operate, will not increase production
Cost.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model；
Fig. 2 is the structural representation of this utility model Application Example.
In the drawings, the 11, first holding wire；12, secondary signal line；13, Via signal line；20, a layer hole is changed；21, first change
Layer hole；22, second a layer hole is changed；23, via stub；30, hole.
Detailed description of the invention
Below in conjunction with the accompanying drawings and this utility model is conducted further description by embodiment:
As it is shown in figure 1, a kind of PCB layout structure avoiding via back drill, including the first holding wire 11 and secondary signal line
12。
First holding wire 11 changes layer hole 21 by first and is connected with Via signal line 13, and Via signal line 13 changes by second
Layer hole 22 is connected with secondary signal line 12, and the two ends of Via signal line 13 connect first respectively and change layer hole 21 and second and change layer hole 22
End points.
Preferably, the first holding wire 11 connects first another end points changing layer hole 21, and secondary signal line 12 connects second
Change the position that the middle part in layer hole 22 is top.
In FIG, the first holding wire 11 is positioned at the first signals layer, and secondary signal line 12 is positioned at secondary signal layer, signal from
During first signals layer is transferred to secondary signal layer, signal is transmitted along the direction of A-B-C-D-E-F, and via is residual
Stake 23 is only EG section.
The applicable elements of the present embodiment is: the length that via stub is 23 sections is within the acceptable range, it may be assumed that secondary signal line
Length L of the via stub 23 between 12 and second another end points changing layer hole 21 need to meet:
The unit of signal rate is Gbps.
The present embodiment relates only to the signal transmission between the first signals layer and secondary signal layer, if relating to more layers
The secondary transmitting procedure between signal is also in like manner, and between three layers or above level in signals transmission, mutually enters
The both sides signals layer of row signal transmission is referred to as mutually the first signals layer and secondary signal layer.
As in figure 2 it is shown, a kind of specific embodiment of the present utility model, in side circuit, HW High Way can be residual to via
The length of stake is very sensitive, and HW High Way is usually with the form of differential lines (two adjacent spacing keeps constant holding wire)
Transmission.This utility model is applied in differential lines, so that the length of via stub substantially shortens.And be transmitted across at signal
Cheng Zhong, hole, ground 30 is not provided with the signals layer of multilamellar.
It should be appreciated that for those of ordinary skills, can be improved according to the above description or be converted,
And all these modifications and variations all should belong to the protection domain of this utility model claims.
Above in conjunction with accompanying drawing, this utility model patent is carried out exemplary description, it is clear that the reality of this utility model patent
Now it is not subject to the restrictions described above, as long as the method design that have employed this utility model patent is various with what technical scheme was carried out
Improve, or the most improved design by this utility model patent and technical scheme directly apply to other occasion, all in this reality
With in novel protection domain.
Claims (4)
1. the PCB layout structure avoiding via back drill, it is characterised in that include the first holding wire and secondary signal line, institute
Stating the first holding wire to change layer hole be connected with Via signal line by first, described Via signal line passes through second and changes layer hole with described
Secondary signal line connects, and the two ends of described Via signal line connect described first respectively and change layer hole and described second and change the end in layer hole
Point.
The PCB layout structure avoiding via back drill the most according to claim 1, it is characterised in that described first holding wire
Connect described first another end points changing layer hole.
The PCB layout structure avoiding via back drill the most according to claim 2, it is characterised in that described secondary signal line
Connect described second and change the position that the middle part in layer hole is top.
The PCB layout structure avoiding via back drill the most according to claim 1, it is characterised in that described secondary signal line
And length L of the via stub between described second another end points changing layer hole meets:Institute
The unit stating signal rate is Gbps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620685094.5U CN205883702U (en) | 2016-07-04 | 2016-07-04 | Avoid via hole back drilling's PCB wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620685094.5U CN205883702U (en) | 2016-07-04 | 2016-07-04 | Avoid via hole back drilling's PCB wiring structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205883702U true CN205883702U (en) | 2017-01-11 |
Family
ID=57693569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620685094.5U Active CN205883702U (en) | 2016-07-04 | 2016-07-04 | Avoid via hole back drilling's PCB wiring structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN205883702U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107846780A (en) * | 2017-11-01 | 2018-03-27 | 郑州云海信息技术有限公司 | A kind of method of the cabling in pcb board |
| CN108595839A (en) * | 2018-04-25 | 2018-09-28 | 郑州云海信息技术有限公司 | A kind of generation method and system of the crimp back drill via file based on Cadence Skill |
| CN110831318A (en) * | 2018-08-13 | 2020-02-21 | 中兴通讯股份有限公司 | PCB and electronic equipment |
| CN113966085A (en) * | 2021-10-29 | 2022-01-21 | 联想(北京)有限公司 | Circuit board and manufacturing method thereof |
| WO2022095874A1 (en) * | 2020-11-03 | 2022-05-12 | 南京中兴新软件有限责任公司 | Circuit board |
| CN115775791A (en) * | 2022-11-25 | 2023-03-10 | 北京斯年智驾科技有限公司 | Chip interconnection structure of high-speed circuit |
-
2016
- 2016-07-04 CN CN201620685094.5U patent/CN205883702U/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107846780A (en) * | 2017-11-01 | 2018-03-27 | 郑州云海信息技术有限公司 | A kind of method of the cabling in pcb board |
| CN107846780B (en) * | 2017-11-01 | 2020-06-16 | 苏州浪潮智能科技有限公司 | Method for wiring in PCB |
| CN108595839A (en) * | 2018-04-25 | 2018-09-28 | 郑州云海信息技术有限公司 | A kind of generation method and system of the crimp back drill via file based on Cadence Skill |
| CN108595839B (en) * | 2018-04-25 | 2021-11-02 | 郑州云海信息技术有限公司 | Method and system for generating compression joint back drilling via file based on Cadence skip |
| CN110831318A (en) * | 2018-08-13 | 2020-02-21 | 中兴通讯股份有限公司 | PCB and electronic equipment |
| WO2022095874A1 (en) * | 2020-11-03 | 2022-05-12 | 南京中兴新软件有限责任公司 | Circuit board |
| CN113966085A (en) * | 2021-10-29 | 2022-01-21 | 联想(北京)有限公司 | Circuit board and manufacturing method thereof |
| CN115775791A (en) * | 2022-11-25 | 2023-03-10 | 北京斯年智驾科技有限公司 | Chip interconnection structure of high-speed circuit |
| CN115775791B (en) * | 2022-11-25 | 2023-08-11 | 北京斯年智驾科技有限公司 | Chip interconnection structure of high-speed circuit |
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Legal Events
| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518000, 12H-12I, 12th Floor, Kangjia Research Building, 28 Science and Technology South 12 Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Yibo Science and Technology Co., Ltd. Address before: 518000, 12H-12I, 12th Floor, Kangjia Research Building, 28 Science and Technology South 12 Road, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Yi Bo Science and Technology Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 11F, Metro financial technology building, 9819 Shennan Avenue, Shenda community, Yuehai street, Nanshan District, Shenzhen, Guangdong 518000 Patentee after: EDADOC Co.,Ltd. Address before: 518000, 12H-12I, 12th Floor, Kangjia Research Building, 28 Science and Technology South 12 Road, Nanshan District, Shenzhen City, Guangdong Province Patentee before: EDADOC Co.,Ltd. |
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| CP02 | Change in the address of a patent holder |