CN205828394U - A kind of groove-shaped CoolMOS - Google Patents
A kind of groove-shaped CoolMOS Download PDFInfo
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- CN205828394U CN205828394U CN201620513881.1U CN201620513881U CN205828394U CN 205828394 U CN205828394 U CN 205828394U CN 201620513881 U CN201620513881 U CN 201620513881U CN 205828394 U CN205828394 U CN 205828394U
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Abstract
This utility model belongs to technical field of semiconductor device, a kind of groove-shaped CoolMOS, includes metal layer on back, N+ substrate, N epitaxial layer, P well region, n+ source region, insulating barrier and front metal layer the most successively；Being provided with some superjunction grooves of through N+ substrate on N+ substrate, superjunction groove one end extends to N epitaxial layer, is filled with P-type silicon in superjunction groove；P well region is provided with some gate trench of through P well region and n+ source region, and gate trench one end extends to N epitaxial layer, is filled with polysilicon in gate trench, is arranged by grid oxygen interval between polysilicon and gate trench；N+ source region is provided with some contact holes of through n+ source region and insulating barrier, and contact hole one end extends to P well region, is filled with conducting metal in contact hole, and conducting metal contacts with front metal layer.Front uses gate trench structure, back side grooving, fills P-type silicon, reaches repeatedly to inject the effect of diffusion p-type ion.
Description
Technical field
This utility model belongs to technical field of semiconductor device, particularly relates to a kind of groove CoolMOS.
Background technology
Being illustrated in figure 1 tradition CoolMOS structure, CoolMOS is again superjunction MOS, new owing to using
Structure of voltage-sustaining layer, its Electric Field Distribution is rectangular configuration, is keeping while power MOSFET advantage,
There is again extremely low conduction loss, there is conducting resistance low, high pressure resistant, feature that caloric value is low.
The super-junction structure of CoolMOS is a pectinate texture, needs to add secondary high-temperature by repeatedly ion implanting
Diffuse to form, make processing step significantly increase, add production cost.
Utility model content
The purpose of this utility model is lacking of the CoolMOS complex manufacturing technology that overcomes prior art to exist
Fall into, it is provided that a kind of groove-shaped CoolMOS, use back side grooving, the technique filling P-type silicon, reach repeatedly
Inject the effect of diffusion p-type ion；Front uses trench gate structure, reduces processing step, reduces chip face
Long-pending, save equipment and production cost, improve the electric property of device.
This utility model solves its technical problem and be the technical scheme is that a kind of groove-shaped
CoolMOS, includes metal layer on back, N+ substrate, N-epitaxial layer, P-well district, n+ the most successively
Source region, insulating barrier and front metal layer；
Some superjunction grooves of through described N+ substrate, described superjunction groove one it is provided with on described N+ substrate
End extends to described N-epitaxial layer, is filled with P-type silicon in described superjunction groove；
Described P-well district is provided with through described P-well district and some gate trench of n+ source region, described grid
Groove one end extends to N-epitaxial layer, is filled with polysilicon, described polysilicon and grid in described gate trench
Arranged by grid oxygen interval between groove；
Described n+ source region is provided with some contact holes of through described n+ source region and described insulating barrier, described contact
One end, hole extends to P-well district, is filled with conducting metal in described contact hole, and described conducting metal and institute
State front metal layer contact.
As preferably, described front metal layer and conducting metal are metallic aluminium.
Further, described contact hole and described gate trench interval are arranged.
As preferably, between described gate trench and superjunction groove, vertical dimension is more than 0.
Specifically, Ti layer that described metal layer on back includes from top to bottom setting gradually, Ni layer and
Ag layer.
The manufacture method of above-mentioned CoolMOS, comprises the steps:
(1) N+ Grown N-epitaxial layer, at the diffusion of N-epi-layer surface or injection boron ion, is formed
P-well district；
(2) in silicon chip surface deposited oxide layer, by gluing, the technique that exposes, develop, etch, formed
Gate trench；
(3) in gate trench, grow grid oxygen, then in gate trench, fill polysilicon, remove excess surface
Polysilicon, inject phosphorus or arsenic ion, form n+ source region；
(4) at n+ area surface depositing insulating layer, by gluing, the technique that exposes, develop, etch, shape
Become contact hole；
(5) in contact hole and surface of insulating layer sputtering conducting metal and front metal layer, electrode is formed；
(6) thinning back side, digs superjunction groove at N+ substrate back, and fills P-type silicon in groove；
(7) sputter or evaporate metal layer on back.
As preferably, described N-epitaxy layer thickness is 50 μm～55 μm.
As preferably, described P-well district thickness is 3～7 μm, and described oxidated layer thickness is 0.2 μm～1.5 μm.
As preferably, Ti layer that described metal layer on back includes from top to bottom setting gradually, Ni layer and
Ag layer, Ti layer thickness isNi layer thickness isAg layer thickness is
As preferably, between described superjunction groove and gate trench, vertical dimension is 5 μm～10 μm.
Beneficial effect: this utility model uses front to use gate trench structure, back side grooving, fills p-type
The technique of silicon, reaches repeatedly to inject the effect of diffusion p-type ion, and front uses gate trench structure, improves
Device pressure, reduces resistivity, reduces epitaxial thickness, reduces the switching loss of device.Reduce injection time
Number, reduces making step, reduces chip area, saved equipment and production cost.
Accompanying drawing explanation
With detailed description of the invention, this utility model is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 is the structural representation of tradition CoolMOS；
Fig. 2～Figure 12 is this utility model groove-shaped CoolMOS manufacturing process structure chart.
Wherein: 1.N+ substrate, 2.N-epitaxial layer, 3.P-well region, 31. oxide layers, 4. gate trench, 5. grid
Oxygen, 6. polysilicon, 7.n+ source region, 8. insulating barrier, 9. contact hole, 10. front metal layer, 11. superjunction
Groove, 12.P type silicon, 13. metal layer on back.
Detailed description of the invention
Embodiment 1
As shown in figure 12, a kind of groove-shaped CoolMOS, include metal layer on back the most successively
13, N+ substrate 1, N-epitaxial layer 2, P-well district 3, n+ source region 7, insulating barrier 8 and front metal layer 10；
Some superjunction grooves 11 of through described N+ substrate 1, described superjunction it is provided with on described N+ substrate 1
Groove 11 one end extends to described N-epitaxial layer 2, is filled with P-type silicon 12 in described superjunction groove 11；
Described P-well district 3 is provided with some gate trench 4 (grid of through described P-well district 3 and n+ source region 7
P-well district 3 is spaced from each other by pole groove 4, and n+ source region 7 is between gate trench 4), described gate trench
4 one end extend to N-epitaxial layer 2, are filled with polysilicon 6, described polysilicon 6 in described gate trench 4
And arranged by grid oxygen 5 interval between gate trench 4；Described gate trench 4 and superjunction groove 11
Between vertical dimension more than 0.
Described n+ source region 7 is provided with some contact holes 9 of through described n+ source region 7 and described insulating barrier 8 and (connects
N+ source region 7 is spaced from each other by contact hole 9), described contact hole 9 one end extends to P-well district 3, described contact
It is filled with conducting metal in hole 9, and described conducting metal contacts with described front metal layer 10, described front
Metal level 10 and conducting metal are metallic aluminium.Between described contact hole 9 and described gate trench 4
Every setting.Described metal layer on back 13 includes Ti layer, Ni layer and the Ag from top to bottom set gradually
Layer.
The manufacture method of above-mentioned CoolMOS, comprises the steps:
(1) as in figure 2 it is shown, Wafer Cleaning, N+ substrate 1 grows N-epitaxial layer 2, N-epitaxial layer 2
Thickness range is 50 μm-55 μm；
(2) as it is shown on figure 3, use diffusion or injection technology doped with boron ion, shape in N-epitaxial layer 2
Becoming P-well district 3, junction depth scope is 3 μm-7 μm, then in silicon chip surface deposited oxide layer 31, thickness model
Enclosing is 0.2 μm-1.5 μm；
(3) by gluing, expose, develop, the technique such as etching, oxide layer 31 and silicon chip are performed etching,
Forming gate trench 4, the depth bounds of gate trench 4 is 4 μm-8 μm；
(4) as it is shown in figure 5, growth grid oxygen 5, grid oxygen 5 thickness range is
(5) as shown in Figure 6, in gate trench 4, fill polysilicon 6, then remove silicon chip surface unnecessary
Polysilicon 6 and oxide layer 31；
(6) as it is shown in fig. 7, inject phosphorus or arsenic ion at silicon chip surface, energy range is 100Kev-200Kev,
Dosage range is 1E14/cm2-9E15/cm2, in P-well district 3, forming n+ source region 7, pn-junction is deeply at 0.2 μ
In m-0.5 μ m, at silicon chip surface depositing insulating layer 8, thickness range is 0.2 μm-1.5 μm；
(7) as shown in Figure 8, by gluing, expose, develop, the technique such as etching, etch away insulating barrier 8
And Si, forming contact hole 9, the degree of depth of contact hole 9 is in 0.3 μm-1 μ m；
(8) as it is shown in figure 9, use sputtering technology, splash-proofing sputtering metal aluminium lamination, form electrode, aluminum layer thickness model
Enclosing is 3 μm-5 μm；
(9) using technique for thinning back side, thinning silicon wafer thickness scope is to 90 μm-150 μm；
(10) as shown in Figure 10, superjunction groove 11, superjunction groove 11 break-through N+ are dug at silicon chip back side
Substrate 1 to N-epitaxial layer 2, superjunction groove 11 depth bounds is 40 μm-45 μm, superjunction groove 11 with
Gate trench 4 does not connects, and in a distance, distance range is 5 μm-10 μm；
(11) as shown in figure 11, in superjunction groove 11, P-type silicon 12 is filled；
(12) as shown in figure 12, sputtering or evaporation technology are used, at silicon chip back side sputtering or evaporation back-side gold
Belonging to layer, described metal layer on back 13 includes Ti layer, Ni layer and Ag layer, the Ti from top to bottom set gradually
Layer thickness isNi layer thickness isAg layer thickness is
Should be appreciated that specific embodiment described above is only used for explaining this utility model, and need not
In limiting this utility model.The obvious change extended out by spirit of the present utility model or change
Move among still in protection domain of the present utility model.
Claims (5)
1. a groove-shaped CoolMOS, it is characterised in that: include back metal the most successively
Floor (13), N+ substrate (1), N-epitaxial layer (2), P-well district (3), n+ source region (7), insulating barrier (8)
With front metal layer (10)；
Some superjunction grooves (11) of through described N+ substrate (1) it are provided with on described N+ substrate (1),
Described superjunction groove (11) one end extends to described N-epitaxial layer (2), fills out in described superjunction groove (11)
It is filled with P-type silicon (12)；
Described P-well district (3) is provided with through described P-well district (3) and some grid of n+ source region (7)
Pole groove (4), described gate trench (4) one end extends to N-epitaxial layer (2), described gate trench (4)
Inside it is filled with polysilicon (6), by between grid oxygen (5) between described polysilicon (6) and gate trench (4)
Every setting；
Described n+ source region (7) is provided with the some of through described n+ source region (7) and described insulating barrier (8)
Contact hole (9), described contact hole (9) one end extends to P-well district (3), in described contact hole (9)
It is filled with conducting metal, and described conducting metal contacts with described front metal layer (10).
Groove-shaped CoolMOS the most according to claim 1, it is characterised in that: described front
Metal level (10) and conducting metal are metallic aluminium.
Groove-shaped CoolMOS the most according to claim 1, it is characterised in that: described connects
Contact hole (9) and described gate trench (4) interval are arranged.
Groove-shaped CoolMOS the most according to claim 1, it is characterised in that: described grid
Between pole groove (4) and superjunction groove (11), vertical dimension is more than 0.
Groove-shaped CoolMOS the most according to claim 1, it is characterised in that: the described back of the body
Face metal level (13) includes Ti layer, Ni layer and the Ag layer from top to bottom set gradually.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201620513881.1U CN205828394U (en) | 2016-05-31 | 2016-05-31 | A kind of groove-shaped CoolMOS |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620513881.1U CN205828394U (en) | 2016-05-31 | 2016-05-31 | A kind of groove-shaped CoolMOS |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870194A (en) * | 2016-05-31 | 2016-08-17 | 苏州同冠微电子有限公司 | Groove type CoolMOS and manufacturing method thereof |
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2016
- 2016-05-31 CN CN201620513881.1U patent/CN205828394U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870194A (en) * | 2016-05-31 | 2016-08-17 | 苏州同冠微电子有限公司 | Groove type CoolMOS and manufacturing method thereof |
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