CN106935498B - The low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor - Google Patents
The low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor Download PDFInfo
- Publication number
- CN106935498B CN106935498B CN201511020961.XA CN201511020961A CN106935498B CN 106935498 B CN106935498 B CN 106935498B CN 201511020961 A CN201511020961 A CN 201511020961A CN 106935498 B CN106935498 B CN 106935498B
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive type
- back side
- pattern
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000003647 oxidation Effects 0.000 title claims abstract description 25
- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 67
- 239000007943 implant Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000005224 laser annealing Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 34
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 144
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 230000000149 penetrating effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor, first in the front production facade element and front metal layer of a first conductive type substrate.Multiple groove structure is made in the back side of the first conductive type substrate, there is a first conductive type impurity to be implanted into layer pattern on the outside of each groove, Yu Duochong groove structure bottom has a first conductive type impurity implant layer.With depositional mode in the multiple groove structure insert multilayer the first conductive type polysilicon layer, and these the first conductive type polysilicon layers respectively with these the first conductive type impurity implant layer alignment patterns.A second conductive type impurity layer is implanted into the first conductive type substrate surface.It is annealed with each impurity layer of the laser annealing technique to resulting structures, to make multiple cutoff layers.
Description
Technical field
The present invention relates to a kind of production methods of insulated gate bipolar transistor, are related to a kind of insulated gate bipolar transistor especially
The low-temperature oxidation layer manufacturing method thereof of back side field stop.
Background technique
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is a kind of combination gold
Oxide-semiconductor field-effect transistor (metal-oxide-semiconductor field effect transistor, MOSFET)
With the composite construction of bipolar junction transistors (bipolar junction transistor, BJT).IGBT is because combine
MOSET is easy to have the characteristic of low conducting voltage pressure drop using grid-controlled characteristic and BJT, therefore is widely used in high electricity
Press high-power application field.
General IGBT (such as a penetrating type IGBT) includes mainly a P+ type semiconductor base, forms a N-type thereon
Then buffer layer forms a N-type epitaxy layer on N-type buffer layer, the drain electrode as parasitism MOSFET in IGBT.Then, in
Gate structure (gate) and emitter structure (emitter) are formed in N-type epitaxy layer, and are formed in the bottom of P+ type semiconductor base
Collector (collector).In above-mentioned penetrating type IGBT, breakdown voltage (breakdown voltage) is mainly by P+ type
Semiconductor base stage and N-type buffer layer determine, have maximum value electric field in this two interlayer and generate.
Another IGBT is that non-penetrating type (Non Punch Through, NPT) IGBT does not have N-type buffer layer then, therefore
Breakdown voltage is determined by the snowslide phenomenon of N-type epitaxy layer (N-type drift region).In order to improve breakdown voltage, field cutoff layer
(Field Stop) IGBT is the N-type buffer layer being substituted in penetrating type IGBT with field cut-off ion implant, whereby with gradual change
(graded) or linear progression (linearly graded) N-type section replaces the precipitous junction of original penetrating type IGBT
(abrupt junction) to reduce electric field maximum, and then promotes breakdown voltage.
It, just must be usually before production front electrode (mostly include aluminum material) in existing field cutoff layer IGBT
Element back side fabricating yard cutoff layer.This is because the fusing point of aluminium electrode is at 630 degree Celsius or so, and field cutoff layer must be in ion cloth
The heat for carrying out high temperature after plant again drives in step (high temperature is about at 900 degree Celsius or more), this pyroprocess can be destroyed in front
The front electrode of formation.However above-mentioned existing back side fabricating yard cutoff layer is related to first being protected with protective layer and does not make front electrode
Insulated gate bipolar transistor front, then make the field cutoff layer at the back side, will increase the complexity of technique in this way.
Summary of the invention
In order to overcome prior art problem, a purpose of the invention is to provide the insulated gate bipolar transistor that can simplify process
The low-temperature oxidation production method of pipe.
To reach above-mentioned purpose, the present invention provides a kind of low temperature oxide layer system of the back side field stop of insulated gate bipolar transistor
Make method, include: (a) providing a first conductive type substrate, and double in a front production insulated gate of the first conductive type substrate
The facade element and front metal layer of gated transistors；(b) multiple groove structure is made in the back side of the first conductive type substrate, and more
Weight groove structure has multiple grooves, and the width of these grooves is tapered along depth direction, has one the on the outside of each groove
One conductive-type impurity is implanted into layer pattern, and Yu Duochong groove structure bottom has a bottom the first conductive type impurity implant layer；(c)
With depositional mode in filling multilayer the first conductive type amorphous silicon layer in the multiple groove, and these the first conductive type amorphous silicon layers divide
Not with these the first conductive type impurity implant layer alignment patterns；(d) it is led in the first conductive type substrate surface implantation one second
One the second conductive type amorphous silicon layer of electric type impurity implant layer or deposition；(e) with laser annealing technique to each amorphous of resulting structures
Silicon layer annealing, to form lamellar field cutoff layer (that is, back side field stop)；(f) in one collection of the first conductive type substrate surface production
Pole metal layer.
Process can be reduced, is dropped since field cutoff layer makes after front metal completion by above-mentioned technique
Low cost.
Furthermore by method of the invention, the field cutoff layer that multilayer has different impurities doping concentration can be made, effectively
Improve breakdown voltage.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Detailed description of the invention
Fig. 1-Figure 16, for illustrate the insulated gate bipolar transistor of an embodiment according to the present invention back side field stop low temperature
Aoxidize the side view of each step of layer manufacturing method thereof；
The low temperature oxide layer system of Figure 17 back side field stop of the insulated gate bipolar transistor of an embodiment to illustrate the invention
Make method flow diagram.
Wherein, appended drawing reference
10 N-type substrates
60 facade elements
62 front metal layers
20 low temperature depositing oxide layers
20A-20D low temperature depositing oxide pattern
22A side wall
26 photoresist patterns
30A-30D impurity implant layer
32A-32D impurity is implanted into layer pattern
The phosphorus-doped amorphous silicon layer of 50A-50C
70A-70D cutoff layers
60 boron doping silicon layers
80 collector metal layers
S10-S20 step
Specific embodiment
Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:
Referring to Fig. 1-Figure 16, for the back side field stop for illustrating the insulated gate bipolar transistor of an embodiment according to the present invention
The side view of each step of low-temperature oxidation layer manufacturing method thereof.Furthermore referring to Figure 17, to illustrate the exhausted of an embodiment according to the present invention
The low-temperature oxidation layer manufacturing method thereof flow chart of the back side field stop of edge grid bipolar transistor.As shown in figure 17, method packet of the invention
Containing the following steps: (S10) provides a first conductive type substrate, and double in a front production insulated gate of the first conductive type substrate
The facade element and front metal layer of gated transistors；(S12) multiple groove structure is made in the back side of the first conductive type substrate, and
Multiple groove structure has multiple grooves, and the width of these grooves is tapered along depth direction, has one on the outside of each groove
The first conductive type impurity is implanted into layer pattern, and Yu Duochong groove structure bottom has a bottom the first conductive type impurity implant layer；
(S14) with depositional mode in inserting multilayer the first conductive type amorphous silicon layer, and these the first conductive types in the multiple groove structure
Amorphous silicon layer respectively with these the first conductive type impurity implant layer alignment patterns；(S16) in the first conductive type substrate surface
It is implanted into one the second conductive type amorphous silicon layer of a second conductive type impurity implant layer or deposition；(S18) with laser annealing technique to institute
Each amorphous silicon layer annealing of structure is obtained, to form lamellar field cutoff layer；(S20) one is made in the first conductive type substrate surface
Back-metal layer.The details of above-mentioned steps is described in detail in i.e. cooperation Fig. 1-16 below.
As shown in Figure 1, completing MOSFET just according to traditional handicraft first on a N-type substrate (the first conductive type substrate) 10
Face element part 60 and front metal layer 62.Then as shown in Fig. 2, carrying out grinding back surface in the N-type substrate 10, and strained
Dehumidifying is gone to corrode (stress release wet etch) and clean (clean) step, with thinning N-type substrate 10, the wherein N
The thickness remaining after thinning of type substrate 10 is related to pressure resistance designed by this IGBT element.In thinning N-type substrate 10
Later, immediately with low temperature oxidation technology (LTO), such as with pecvd process in one low temperature depositing oxygen of the back side of N-type substrate 10 production
Change layer 20, and the temperature of this low temperature process can be under 450 degree Celsius, to avoid front metal layer 62 is destroyed.
As shown in figure 3, then with photoresist cloth shape technique in defining photoresist pattern 26 in low temperature depositing oxide layer 20, this photoresist
Pattern 26 can be used as etching mask so that the low temperature depositing oxide layer 20 not covered by photoresist pattern 40 can in the subsequent process by
Removal.
As shown in figure 4, with anisotropic etch process (such as dry etching process to oxide) and using this photoresist figure
Case 26 is used as etching mask, and removal is not removed by 20 part of low temperature depositing oxide layer that photoresist pattern 26 covers, with remaining the
One low temperature depositing oxide pattern 20A.Then using this first low temperature depositing oxide pattern 20A as exposure mask carry out phosphorus (P) from
Sub- implant, it is miscellaneous with the part implanted with n-type first not covered by the first low temperature depositing oxide pattern 20A at 10 back side of N-type substrate
Matter implant layer (the first impurity of the first conductive type implant layer) 30A.Then remove photoresist pattern 26 (Fig. 5), and as shown in fig. 6, after
It is continuous that this first low temperature depositing oxide pattern 20A is handled to make the first side wall (spacer) 22A extended laterally,
And this first side wall (spacer) 22A covers a marginal portion of this N-type the first impurity implant layer 30A.More specifically, herein
Place makes the first side wall (spacer) 22A, first can be covered on all body structure surfaces with low temperature oxidation technology deposited oxide layer
On, notch as shown in FIG. 6 then is etched by etching (such as isotropic etching) technique again, that is, produce as shown in Figure 6
The first side wall (spacer) 22A.
As shown in fig. 7, then using this first low temperature depositing oxide pattern 20A as etching mask, and for this N-type base
The back side of plate 10 is etched, to remove 10 back part of N-type substrate not covered by the first low temperature depositing oxide pattern 20A
Point, and the first groove 40A is formed after etching, the depth of this first groove 40 is enough to make not by the first low temperature depositing oxide pattern
The part N-type the first impurity implant layer 30A that 20A is covered removes, so that only remaining N-type first is miscellaneous by the first impurity implant layer 30A
Matter is implanted into layer pattern (the first conductive type impurity is implanted into layer pattern) 32A.
As shown in figure 8, partially forming the second low temperature arround the first groove 40A after forming the first groove 40A
Deposited oxide layer pattern 20B, and carry out phosphorus (P) ion implant again subsequently for the back side of N-type substrate 10, in the first groove
Implanted with n-type the second impurity implant layer 30B (Fig. 9) under the bottom 40A.More specifically, this second low temperature depositing oxide pattern
The production method of 20B can make similar to mode as shown in Figure 6, that is, be covered on all knots with low temperature oxidation technology deposited oxide layer
On structure surface, structure as shown in Figure 8 then is etched by etching (such as isotropic etching) technique again, that is, is produced such as figure
With the second low temperature depositing oxide pattern 20B of side wall shown in 8.After ion implant, immediately with the first low temperature depositing
Oxide pattern 20A and the second low temperature depositing oxide pattern 20B as etching mask, and to not by the first low temperature depositing aoxidize
The part that layer pattern 20A and the second low temperature depositing oxide pattern 20B is covered is etched, to form the second groove 40B.Such as figure
Shown in 10, the depth of this second groove 40B is enough to make the N-type second not covered by the second low temperature depositing oxide pattern 20B
The part impurity implant layer 30B removes, so that N-type the second impurity implant layer 30B is only left the second impurity of N-type and is implanted into layer pattern 32B.
The step of then repeating Fig. 8-Figure 10 is implanted into layer pattern to make the impurity of other layers, that is, N-type third impurity is planted
Enter layer pattern 32C and production the 4th impurity implant layer 30D of N-type, as shown in figure 11.
Then, remaining low temperature depositing oxide pattern, that is, the first low temperature are removed in a manner of dry ecthing or wet etching
Deposited oxide layer pattern 20A, the second low temperature depositing oxide pattern 20B, third low temperature depositing oxide pattern 20C and the 4th are low
Warm deposited oxide layer pattern 20D.As shown in figure 12, resulting structures are overleaf to have multiple groove structure 40 (recessed comprising first
Slot 40A, the second groove 40B and third groove 40C) N-type substrate 10, and on the outside of the first groove 40A have the first impurity of N-type
It is implanted into layer pattern 32A, on the outside of the second groove 40B there is the second impurity of N-type to be implanted into layer pattern 32B, on the outside of third groove 40C
There is the 4th impurity implant layer 30D of N-type with N-type third impurity implantation layer pattern 32C, in the third bottom groove 40C.
As shown in figure 13, the phosphorus-doped amorphous silicon layer of multilayer, that is, the first phosphorus-doped amorphous silicon are then made with pecvd process
Layer 50A, the second phosphorus-doped amorphous silicon layer 50B and the phosphorus-doped amorphous silicon layer 50C of third.In addition, the impurity of the first phosphorus-doped amorphous silicon layer 50A
Concentration is substantially identical as the first impurity of N-type implantation impurity concentration of layer pattern 32A；The impurity of second phosphorus-doped amorphous silicon layer 50B is dense
Degree is substantially identical as the second impurity of N-type implantation impurity concentration of layer pattern 32B；The impurity concentration of the phosphorus-doped amorphous silicon layer 50C of third
It is substantially identical as the N-type third impurity implantation impurity concentration of layer pattern 32C.
As shown in figure 14, non-in the first phosphorus-doped amorphous silicon layer 50A of formation, the second phosphorus-doped amorphous silicon layer 50B and third p-doped
After crystal silicon layer 50C, i.e., boron doping silicon layer (the second conductive type amorphous silicon layer) 60 is made with pecvd process, or with ion cloth
Plant mode is implanted into this boron doping silicon layer (the second conductive type impurity implant layer) 60.
As shown in figure 15, then with laser annealing silicon layer 50A phosphorus-doped amorphous for first, the second p-doped non-polycrystalline silicon layer
50B and third p-doped non-silicon layer 50C and boron doping silicon layer 60 are annealed.Because the structure shown in Figure 12 is in the first groove 40A
Outside has the second impurity implantation layer pattern 32B with the first impurity implantation layer pattern 32A, on the outside of the second groove 40B, the
There is third impurity to be implanted into layer pattern 32C on the outside of three groove 40C, these impurity implantation layer pattern can be used as crystal seed (seed), and
Make the first phosphorus-doped amorphous silicon layer 50A, the second phosphorus-doped amorphous silicon layer 50B and the phosphorus-doped amorphous silicon layer 50C of third after anneal at
For the monocrystalline silicon layer mixed with impurity.In other words, after anneal, first cut-off from shallow to deep can be formed in resulting structures
Layer 70A (being implanted into layer pattern 32A comprising the first phosphorus-doped amorphous silicon layer 50A originally and the first impurity), second cutoff layer 70B (packet
Be implanted into layer pattern 32B containing the second phosphorus-doped amorphous silicon layer 50B and the second impurity originally), third field cutoff layer 70C is (comprising originally the
Three phosphorus-doped amorphous silicon layer 50C and third impurity are implanted into layer pattern 32C) and the 4th cutoff layer 70D (by the 4th impurity implant layer
30D is formed after laser annealing).Furthermore between 10 back surfaces of first cutoff layer 70A and N-type substrate there is a boron to mix
Miscellaneous silicon layer 60 is to provide the p type semiconductor layer of insulated gate bipolar transistor bottom.Again referring to this figure, it is distributed from shallow to deep from bottom
First cutoff layer 70A, second cutoff layer 70B, third field cutoff layer 70C and the 4th cutoff layer 70D preferably along
The back side is gradually decreased to depth direction concentration；In other words, secondly the concentration highest of first cutoff layer 70A is second cut-off
Layer 70B, is thirdly third field cutoff layer 70C, and the concentration of the 4th cutoff layer 70D is minimum.In addition, this four layers of field cutoff layers
The range of the impurity concentration of 70A-70D is 1X 1013Cm-3 to 1X 1016cm-3；That is, first cutoff layer 70A's is dense
Highest is spent, but concentration is still below 1X 1016cm-3；The concentration of 4th cutoff layer 70D is minimum, but concentration is still higher than 1X
1013cm-3, to reach effect needed for element.
As shown in figure 16, a back-metal layer finally is made in 10 bottom of N-type substrate, using as this insulated gate bipolar transistor
The collector metal layer 80 of pipe, the material of this collector metal layer 80 can (but being not limited to) aluminium (Al), titanium nitride (TiN) or
Tungsten (W).
Process can be reduced, is dropped since field cutoff layer makes after front metal completion by above-mentioned technique
Low cost.
Furthermore by method of the invention, the field cutoff layer that multilayer has different impurities doping concentration can be made, effectively
Improve breakdown voltage.
The above embodiments are only some embodiments explanation of the present invention, still have it to the present invention known to this technology person of knowing
Remaining embodiment, N-type substrate 10 as escribed above can be replaced by p-type substrate, and related n-type doping is by p-type doped and substituted, P
Type doping is replaced by n-type doping, still may achieve the effect of avoiding the formation of Zener diode.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe
It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention
Shape all should fall within the scope of protection of the appended claims of the present invention.
Claims (7)
1. a kind of low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor, which is characterized in that comprising following
Step:
(a) a first conductive type substrate is provided, and in a front production insulated gate bipolar transistor of the first conductive type substrate
Facade element and front metal layer；
(b) multiple groove structure is made in the back side of the first conductive type substrate, which has multiple grooves, and this
The width of a little grooves on the outside of each groove there is a first conductive type impurity to be implanted into layer pattern to be tapered along depth direction, in
The multiple groove structure bottom has a bottom the first conductive type impurity implant layer；
(c) with depositional mode in filling multilayer the first conductive type amorphous silicon layer in the multiple groove structure, and these first conductions
Type amorphous silicon layer respectively with these the first conductive type impurity implant layer alignment patterns；
(d) a second conductive type impurity implant layer is implanted into the first conductive type substrate surface or one the second conductive type of deposition is non-
Crystal silicon layer；
(e) it is annealed with each amorphous silicon layer of the laser annealing technique to resulting structures, to form lamellar field cutoff layer；
(f) a collector metal layer is made in the first conductive type substrate surface；
Wherein, step (b) further includes
(b1) one first groove is defined and in the one the first conductive type impurity implant layer of the first bottom portion of groove implant；
(b2) the first low temperature depositing oxidation pattern with side wall, and this sidewall portion are made in the back side of the first conductive type substrate
Divide Chong Die with the first conductive type impurity implant layer；
(b3) it using the first low temperature depositing oxidation pattern as etching mask, removes and is not covered by the first low temperature depositing oxidation pattern
The first conductive type impurity implant layer part, with formed a first conductive type impurity be implanted into layer pattern；
(b4) have the second low temperature depositing oxidation pattern of side wall in resulting structures production, and the second low temperature depositing oxidation pattern compared with
The first low temperature depositing oxidation pattern is deep；
(b5) another the first conductive type impurity implant layer of implant under the second low temperature depositing oxidation pattern, and it is second low with this
Warm deposited oxide pattern is that etching mask removes another the first conductive type that do not covered by the second low temperature depositing oxidation pattern
Impurity implant layer, to form another the first conductive type impurity implantation layer pattern；
(b6) abovementioned steps (b4) and (b5) is repeated until required multilayer the first conductive type impurity implantation layer pattern is completed.
2. the low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor according to claim 1, special
Sign is that the first conductive type is N-type or p-type.
3. the low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor according to claim 1, special
Sign is that the step (c) is made with pecvd process.
4. the low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor according to claim 1, special
Sign is, four layers of field cutoff layer are formed after step (d).
5. the low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor according to claim 4, feature exist
In the impurity concentration of four layers of field cutoff layer is gradually decreased along the back side to depth direction.
6. the low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor according to claim 5, special
Sign is that the range of impurity concentration is 1X1013cm-3To 1 X 1016cm-3。
7. the low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor according to claim 1, special
Sign is that the material of the collector metal layer is aluminium, titanium nitride or tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511020961.XA CN106935498B (en) | 2015-12-30 | 2015-12-30 | The low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511020961.XA CN106935498B (en) | 2015-12-30 | 2015-12-30 | The low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106935498A CN106935498A (en) | 2017-07-07 |
| CN106935498B true CN106935498B (en) | 2019-09-13 |
Family
ID=59442400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511020961.XA Active CN106935498B (en) | 2015-12-30 | 2015-12-30 | The low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106935498B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054748A (en) * | 1997-03-18 | 2000-04-25 | Kabushiki Kaisha Toshiba | High voltage semiconductor power device |
| CN103871852A (en) * | 2012-12-14 | 2014-06-18 | 中国科学院微电子研究所 | Manufacture method of PT type power device with FS layers |
| CN104040692A (en) * | 2012-03-19 | 2014-09-10 | 富士电机株式会社 | Production method for semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5867484B2 (en) * | 2013-11-14 | 2016-02-24 | トヨタ自動車株式会社 | Manufacturing method of semiconductor device |
-
2015
- 2015-12-30 CN CN201511020961.XA patent/CN106935498B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054748A (en) * | 1997-03-18 | 2000-04-25 | Kabushiki Kaisha Toshiba | High voltage semiconductor power device |
| CN104040692A (en) * | 2012-03-19 | 2014-09-10 | 富士电机株式会社 | Production method for semiconductor device |
| CN103871852A (en) * | 2012-12-14 | 2014-06-18 | 中国科学院微电子研究所 | Manufacture method of PT type power device with FS layers |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106935498A (en) | 2017-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5560931B2 (en) | Manufacturing method of super junction semiconductor device | |
| CN104051540B (en) | Super-junction device and its manufacturing method | |
| CN104733531A (en) | Dual oxide trench gate power mosfet using oxide filled trench | |
| TW200933750A (en) | MOSFET active area and edge termination area charge balance | |
| CN111200008B (en) | Superjunction device and method of manufacturing the same | |
| CN105225935A (en) | There is trench gate structure and the manufacture method thereof of shield grid | |
| TWI539577B (en) | Integrated gate runner and field implant termination for trench devices | |
| EP1873837B1 (en) | Semiconductor power device having an edge-termination structure and manufacturing method thereof | |
| CN105870194A (en) | Groove type CoolMOS and manufacturing method thereof | |
| CN113035840A (en) | SGT MOSFET device and contact hole manufacturing method thereof | |
| CN111490097A (en) | Method for manufacturing power semiconductor device | |
| JP2018082057A (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN105513971A (en) | Manufacturing method of trench gate power device with shield gate | |
| CN105531827A (en) | Semiconductor device | |
| TWI503983B (en) | Power mosfet and methods for forming the same | |
| US20120273882A1 (en) | Shallow-trench cmos-compatible super junction device structure for low and medium voltage power management applications | |
| CN108807506A (en) | The deep trouth super-junction MOSFET device and its processing technology of with groove grid structure | |
| CN105428241A (en) | Manufacturing method of trench gate power device with shield grid | |
| CN105655385B (en) | The manufacturing method of groove-shaped super-junction device | |
| DE102016104968B3 (en) | METHOD FOR PRODUCING SEMICONDUCTOR DEVICES WITH TRANSISTOR CELLS, SEMICONDUCTOR DEVICE AND MICROELECTROMECHANICAL DEVICE | |
| CN104517855A (en) | Super-junction semiconductor device manufacturing method | |
| CN106935498B (en) | The low-temperature oxidation layer manufacturing method thereof of the back side field stop of insulated gate bipolar transistor | |
| CN107887447A (en) | A kind of MOS type device and its manufacture method | |
| CN110416079A (en) | The production method of trench gate igbt chip | |
| CN110223959B (en) | Metal oxide semiconductor field effect transistor with deep and shallow grooves and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220518 Address after: 1 / F and 4 / F, block B, No. 18, Sanle East Road, Beijiao Community Industrial Park, Beijiao Town, Shunde District, Foshan City, Guangdong Province Patentee after: Guangdong universal energy saving component Co.,Ltd. Address before: 1 F, shell Arts crafts emporium, 12 Zhong Jie street, Chai Wan, Hongkong, China Patentee before: PFC DEVICE HOLDING Ltd. |