CN110416079A - The production method of trench gate igbt chip - Google Patents
The production method of trench gate igbt chip Download PDFInfo
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- CN110416079A CN110416079A CN201810397165.5A CN201810397165A CN110416079A CN 110416079 A CN110416079 A CN 110416079A CN 201810397165 A CN201810397165 A CN 201810397165A CN 110416079 A CN110416079 A CN 110416079A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000011800 void material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 33
- 230000008569 process Effects 0.000 abstract description 21
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910004541 SiN Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000005283 ground state Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of production methods of trench gate igbt chip, including step 1: active groove and empty gate groove is formed on wafer substrate, empty gate groove is set between active groove；Step 2: the second oxide layer is formed in active groove and empty gate groove inner surface, and fills polysilicon in active groove and empty gate groove, forms real trench gate and empty trench gate；Step 3: insulating medium layer is formed on wafer substrate upper surface and real trench gate and empty trench gate；Step 4: performing etching the first predeterminated position on insulating medium layer, at least exposes the part wafer substrate between the corresponding empty trench gate in lower section and real trench gate and empty trench gate, forms the first contact window.The application between active groove by being inserted into one or more empty gate grooves, increase the size of metal contact hole using the spacing between the width and empty gate groove of empty gate groove itself, to reduce the formation process of metal contact window and the technology difficulty of metal filling perforation.
Description
Technical field
The present invention relates to technical field of semiconductor device more particularly to a kind of production methods of trench gate igbt chip.
Background technique
Insulated gate bipolar transistor (IGBT) is by double pole triode (BJT) and insulating gate type field effect tube
(MOSFET) the compound full-control type voltage driven type power semiconductor formed, since it is low with on-state voltage drop, electric current is close
The features such as degree is big, and input impedance is high and fast response time, be widely used in rail traffic, smart grid, industrial frequency conversion with
And the fields such as new-energy automobile.
Existing trench gate igbt chip technology is due to by being laterally converted into longitudinal direction, effectively eliminating in plane gate groove channel
JFET effect, limit gully density no longer by chip list area, thus improve cellular density and significantly promoted chip electricity
Current density, therefore plane gate technique has been gradually replaced in mesolow application field.In order to further enhance trench gate igbt chip
Power density, igbt chip manufacturer release one after another fine grooves design, pass through advanced photolithography techniques and manufacturing process, reduce
Groove width reduces separation, to increase MOS gully density, promotes chip current density.However as trench gate igbt chip
Fining degree is higher and higher, and the size of metal contact hole is also smaller and smaller, so that the formation process of metal contact window
And metal process for filling hole difficulty is increasing, the requirement to technique platform also will be higher and higher, further mentions and increases groove
The process complexity of grid igbt chip.
Therefore, needing one kind had both reduced the formation process and metal process for filling hole difficulty of metal contact window, but did not increased
Add the production method of the trench gate igbt chip of process complexity.
Summary of the invention
The technical problem to be solved by the present invention is to be gradually increased with the fining degree of existing trench gate igbt chip,
The formation process and metal process for filling hole difficulty of metal contact window in the production method of trench gate igbt chip are also gradually
Zeng great, to improve the process complexity of trench gate igbt chip.
In order to solve the above-mentioned technical problems, the present invention provides a kind of production methods of trench gate igbt chip, including such as
Lower step:
Step 1: forming active groove and empty gate groove on wafer substrate, and the void gate groove is set to described active
Between groove；
Step 2: the second oxide layer is formed in the active groove and the empty gate groove inner surface, and described active
Polysilicon is filled in groove and the empty gate groove, forms real trench gate and empty trench gate；
Step 3: dielectric is formed on the wafer substrate upper surface and the real trench gate and empty trench gate
Layer；
Step 4: performing etching the first predeterminated position on the insulating medium layer, and it is corresponding at least to expose lower section
Part wafer substrate between the void trench gate and the real trench gate and empty trench gate, forms the first contact window.
Preferably, further comprising the steps of before step 1:
The first oxide layer is formed in wafer substrate upper surface；
N-type impurity is injected into the wafer substrate, and so that it is spread the first junction depth and forms N trap；
P type impurity is injected into the N trap, and so that it is spread the second junction depth and forms p-well.
Preferably, the step 1 specifically includes:
To the second predeterminated position and the P corresponding with the second predeterminated position lower section in first oxide layer
Wafer substrate below trap, N trap and the N trap performs etching, and forms active groove and is set between the active groove
Empty gate groove, the empty gate groove between active groove described in any two is no less than one.
Preferably, the step 2 specifically includes:
Remaining first oxide layer is removed, and in the p-well upper surface, the active groove and the empty gate groove
Inner surface forms the second oxide layer；
It is formed in second oxide layer of the p-well upper surface and in the active groove and the empty gate groove
Polysilicon layer, the polysilicon in the active groove and the empty gate groove are respectively filled with the active groove and the empty grid ditch
Slot etches away second oxide layer of the p-well upper surface, and to described active to form real trench gate and empty trench gate
Polysilicon in groove and the empty gate groove performs etching, so that the polysilicon in the active groove and the empty gate groove
Highest point is poor lower than the wafer substrate upper surface preset height.
Preferably, further include following steps between the step 2 and step 3:
Etch away second oxide layer of the p-well upper surface；
The third predeterminated position of the p-well upper surface between the real trench gate and empty trench gate injects N-type impurity,
The area N+ of third junction depth is formed, the area N+ is contacted with the real trench gate；
Injecting p-type impurity in the p-well at least between the real trench gate and empty trench gate, forms the area P+, the N
+ area and the area P+ contact, and the area P+ is contacted with the empty trench gate.
Preferably, the step 5 specifically includes:
The first predeterminated position on the insulating medium layer is performed etching, the corresponding empty ditch in lower section is at least exposed
The area P+ between slot grid, the part area N+ and the real trench gate and empty trench gate, forms the first contact window.
Preferably, further include following steps after the step 5:
The deposited metal layer on first contact window and the remaining insulating medium layer forms source electrode.
Preferably, first junction depth is greater than second junction depth；Second junction depth is greater than the third junction depth.
Preferably, the p type impurity concentration in the p-well is less than the p type impurity concentration in the area P+, the N in the N trap
Type impurity concentration is less than the N-type impurity concentration in the area N+.
It preferably, further include forming back structures in the lower surface of the wafer substrate, the back structures are break-through
Type, non-punch or soft punch.
Compared with prior art, one or more embodiments in above scheme can have following advantage or beneficial to effect
Fruit:
Using the production method of trench gate igbt chip provided in an embodiment of the present invention, by being needed between active groove
The lower section of metal contact hole is done, one or more empty gate grooves are inserted into, utilizes the width and empty gate groove of empty gate groove itself
Between spacing increase the size of metal contact hole, to reduce the formation process and metal filling perforation of metal contact window
Technology difficulty, and reduce the requirement to technique platform.Simultaneously using trench gate igbt chip provided by the embodiments of the present application
Production method not will increase the integrated artistic of the production method of trench gate igbt chip without increasing additional processing step
Complexity.Designer can also carry out the ruler of coordinated control metal contact hole by the setting to empty gate groove difference number simultaneously
Very little, in order to adapt to different process equipments, this is set as designer and provides very big freedom degree.
Other features and advantages of the present invention will be illustrated in the following description, and partly becomes from specification
It is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by wanting in specification, right
Specifically noted structure is sought in book and attached drawing to be achieved and obtained.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, with reality of the invention
It applies example and is used together to explain the present invention, be not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the flow chart of the production method of trench gate igbt chip in the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram of the production method process of trench gate igbt chip in the embodiment of the present invention one；
Fig. 3 is the groove of not formed metal layer made of the production method of trench gate igbt chip in the embodiment of the present invention two
The structural schematic diagram of grid igbt chip；
Fig. 4 is the top view of trench gate igbt chip in the embodiment of the present invention two；
Fig. 5 is the groove of not formed metal layer made of the production method of trench gate igbt chip in the embodiment of the present invention three
The structural schematic diagram of grid igbt chip；
Fig. 6 is the top view of trench gate igbt chip in the embodiment of the present invention three；
Fig. 7 is the knot of trench gate igbt chip made of the production method of trench gate igbt chip in the embodiment of the present invention four
Structure schematic diagram；
Fig. 8 is the top view of trench gate igbt chip in the embodiment of the present invention four.
Specific embodiment
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, how to apply to the present invention whereby
Technological means solves technical problem, and the realization process for reaching technical effect can fully understand and implement.It needs to illustrate
As long as not constituting conflict, each feature in each embodiment and each embodiment in the present invention can be combined with each other,
It is within the scope of the present invention to be formed by technical solution.
In order to further enhance the power density of trench gate igbt chip, existing trench gate igbt chip passes through fine ditch
Slot design solves the problems, such as this, i.e., by advanced photolithography techniques and manufacturing process, reduces groove width, separation is reduced, to increase MOS
Gully density promotes chip current density.It is higher and higher however as the fining degree of trench gate igbt chip, metal contact
The size in hole is also smaller and smaller, so that the formation process of metal contact window and metal process for filling hole difficulty are increasingly
Greatly, also will be higher and higher to the requirement of technique platform, further increase the process complexity of trench gate igbt chip.
Embodiment one
To solve the above-mentioned technical problems in the prior art, the embodiment of the invention provides a kind of trench gate IGBT cores
The production method of piece.
Fig. 1 shows the flow chart of the production method of trench gate igbt chip in the embodiment of the present invention one；Fig. 2 shows this
The structural schematic diagram of the production method process of trench gate igbt chip in inventive embodiments one.
With reference to Fig. 1 and Fig. 2, there is the present embodiment trench gate igbt chip production method to include the following steps.
Step S101 forms the first oxide layer 1 on wafer substrate 2.
Specifically, wafer substrate 2 can choose fused silicon chip, and the first oxide layer 1 can be silica, lead on fused silicon chip
The mode for crossing deposition forms one layer of uniform silica or is directly formed by way of thermal oxide in fused silicon chip upper surface
One layer of uniform silica, the thickness of silica existBetween.
It should be noted that in other embodiments of the invention, other reasonable manners also can be used in wafer substrate 2
The first oxide layer 1 of upper formation, the present invention is not limited to the above methods.
N-type impurity is injected into wafer substrate 2 by step S102, and so that it is spread the first junction depth and formed N trap 3.
Specifically, N-type impurity is injected into 2 upper surface of wafer substrate, and so that it is spread the first junction depth and forms N trap 3.It is excellent
Selection of land, N-type impurity are phosphorus, and the dosage range for injecting phosphorus is 1 × 1013cm-2To 5 × 1014cm-2, the first junction depth is 2 μm -6 μm.
It should be noted that the diffusion process of all impurity includes not only longitudinal diffusion in the application, it further include transverse direction
Diffusion.Simultaneously it should also be noted that, since N trap 3 is progress impurity diffusion formation on the basis of wafer substrate 2,
The part that N trap 3 is formed on wafer substrate 2 also belongs to a part of wafer substrate 2；It is similarly subsequent to be formed on wafer substrate 2
P-well 4, the area N+ 9 and the area P+ 10 all belong to a part of wafer substrate 2.
P type impurity is injected into N trap 3 by step S103, and so that it is spread the second junction depth and formed p-well 4.
Specifically, p type impurity is injected into 3 upper surface of N trap, and it is made to spread the second junction depth of wafer substrate 2, formed
P-well 4.Wherein, the second junction depth of p type impurity diffusion is less than the first junction depth of N-type impurity diffusion.Preferably, p type impurity is boron,
The measures range for injecting boron is 1 × 1014cm-2To 1 × 1015cm-2, the second junction depth is 1 μm -3 μm.
It should be noted that since p-well 4 is to be diffused to be formed on the basis of N trap 3, original N trap 3 and p-well 4
The part of coincidence is p-well 4；Simultaneously when being diffused to the p type impurity for forming p-well 4, the N-type impurity in N trap 3 also can phase
The diffusion again answered, therefore finally formed 3 junction depth of N trap is greater than the first junction depth, and since the second junction depth of p-well 4 is less than N trap 3
The first junction depth, therefore anyway diffusion 3 federation of N trap below p-well 4.
Step S104, forms active groove and empty gate groove on wafer substrate 2, empty gate groove be set to active groove it
Between.
Specifically, groove 5 is formed on wafer substrate 2 by way of etching.Wherein, real trench gate 7 will be formed
Groove is set as active groove, and the groove that will form empty trench gate 8 is set as empty gate groove.Empty gate groove is set to active ditch
Between slot, and setting is no less than one empty gate groove between any two active groove.The present embodiment active groove it
Between the empty gate grooves of setting two.Further, the forming process of groove 5 are as follows: the portion of trench gate will be needed to form on wafer substrate 2
Divide position corresponding with the first oxide layer 1 to be arranged to the second predeterminated position, the second predeterminated position in the first oxide layer 1 is carried out
Etching exposes corresponding p-well 4 below the second predeterminated position, so that forming trench openings in the first oxide layer 1.Later to
The corresponding p-well 4 of trench openings and N trap 3 perform etching, and expose the wafer substrate 2 of corresponding 3 lower section of N trap of trench openings, then right
Wafer substrate 2 carries out endless full etching at this, forms groove 5.Preferably, the groove depth of groove 5 is between 3-7 μm, 5 groove width of groove
Between 0.5-1.5 μm.
It should be noted that since igbt chip includes multiple cellulars on wafer substrate 2, and the present embodiment is formed
Igbt chip each cellular on all have trench gate, therefore need in the step of forming groove 5 to more on wafer substrate 2
A position performs etching to form multiple grooves 5, therefore the second predeterminated position includes and needs to form groove 5 on wafer substrate 2
The corresponding position in all positions.Similarly subsequent first predeterminated position and third predeterminated position indicate multiple positions.
Step S105 forms the second oxide layer 6 in active groove and empty gate groove inner surface, and in active groove and empty grid
Polysilicon is filled in groove, forms real trench gate 7 and empty trench gate 8.
Specifically, etching removal remaining first oxide layer 1 in 4 upper surface of p-well, while in 4 upper surface of p-well and active ditch
Slot and empty gate groove inner surface form one layer of uniform second oxide layer 6, and the thickness of the second oxide layer 6 existsIt
Between.Further, the second oxide layer 6 of 4 upper surface of p-well and active groove and empty gate groove inner surface can pass through thermal oxide
Mode formed.Preferably, 6 material of the second oxide layer is silica.
Polysilicon layer is formed in the second oxide layer 6 of 4 upper surface of p-well and in active groove and empty gate groove, wherein
Polysilicon in active groove and empty gate groove fills up groove.It then etches away more in the second oxide layer 6 of 4 upper surface of p-well
Crystal silicon；The polysilicon in active groove and empty gate groove is performed etching simultaneously, so that the polysilicon highest point in groove is lower than P
4 upper surface of trap, and with that there are preset heights 4 upper surface of p-well is poor.Preferably, the range of preset height difference is 0-200nm, and ditch
Actual depth of the preset height difference of polysilicon highest point and 4 upper surface of p-well in slot no more than the area N+.
It should be noted that it can not be made to diffuse to form p-well after p type impurity is injected into N trap 3 in step s 103
4, p type impurity can be diffused simultaneously when the step forms the second oxide layer 6 and form it into p-well 4.
Step S106, etches away the second oxide layer 6 of p-well upper surface, i.e., by lithographic technique by the of 4 upper surface of p-well
Dioxide layer 6 etches away, and exposes 4 upper surface of p-well.
The third predeterminated position of step S107,4 upper surface of p-well between real trench gate 7 and empty trench gate 8 inject N-type
Impurity, forms the area N+ 9 of third junction depth, and the area N+ 9 is contacted with real trench gate 7.
Specifically, 4 upper surface of p-well between real trench gate 7 and empty trench gate 8 is set at the position of real trench gate 7
It is set to third predeterminated position, the third predeterminated position of 4 upper surface of p-well between real trench gate 7 and empty trench gate 8 injects N-type
Impurity forms the area N+ 9 of third junction depth by thermal diffusion or rapid thermal annealing etc..It should be noted that the area N+ 9 formed and reality
Trench gate 7 contacts, and does not contact with empty trench gate 8.Preferably, N-type impurity is phosphorus or arsenic, and injection measures range is 8 × 1014cm-2
To 8 × 1015cm-2, third junction depth can be 0.2~1.0 μm.Wherein, the N-type impurity concentration in the area N+ 9 is greater than the N-type impurity of N trap 3
Concentration, third junction depth is less than the second junction depth.
It should be noted that ibid, since the area N+ 9 is formed on the basis of p-well 4, former p-well 4 is formed with new
The area N+ 9 be overlapped part be the area N+ 9.
Step S108, injecting p-type impurity in the p-well 4 at least between real trench gate 7 and empty trench gate 8, forms the area P+
10, N+ areas 9 and the area P+ 10 contact, and the area P+ 10 is contacted with empty trench gate 8.
Specifically, p type impurity is injected into the p-well 4 between real trench gate 7 and empty trench gate 8, and expands p type impurity
It is scattered to one end and the area N+ 9 to connect, forms the area P+ 10.The area P+ 10 is contacted with the area N+ 9 and empty trench gate 8 respectively, and the area P+ 10 is simultaneously
It is not contacted with real trench gate.Preferably, p type impurity is still boron, and the dosage range for injecting boron is 1 × 1015cm-2To 5 × 1015cm-2.Wherein, the p type impurity concentration in p-well 4 is less than the p type impurity concentration in the area P+ 10.
Simultaneously can also injecting p-type impurity in the p-well 4 between empty trench gate 8 and empty trench gate 8, and spread its both ends
It is contacted with the empty trench gate 8 of two sides.
It should be noted that N trap 3, p-well 4, the area N+ 9 and the area P+ 10 of formation are most when impurity is no longer diffused
N trap 3, p-well 4, the area N+ 9 and the area P+ 10 of whole igbt chip.
Step S109 forms insulating medium layer 11 on 2 upper surface of wafer substrate and real trench gate 7 and empty trench gate 8.
Specifically, a floor is formed absolutely in 9 upper surface of the area N+, 10 upper surface of the area P+ and real trench gate 7 and empty trench gate 8
Edge dielectric layer 11, the thickness of insulating medium layer 11 is between 300-1500nm.
Step S110 performs etching the first predeterminated position on insulating medium layer 11, and it is corresponding at least to expose lower section
Part wafer substrate 2 between empty grid, real trench gate 7 and empty trench gate 8, forms the first contact window 13.
Specifically, the first predeterminated position is set by the SI semi-insulation dielectric layer between active groove, to insulating medium layer
The first predeterminated position on 11 performs etching, the corresponding empty grid in exposed lower section, the part area N+ 9, real trench gate 7 and empty trench gate 8
Between the area P+ 10 and empty grid and empty grid between the area P+ 10, form the first contact window 13.First contact window 13 at this time
Width range is between 0.5~7 μm.
It should be noted that the first contact window 13 is then right when being provided only with an empty gate groove between active groove
It should not need to expose the area P+ 10 between empty grid and empty grid.
Step S111, the deposited metal layer 12 on the first contact window 13 and remaining insulating medium layer 11 form source
Pole.Preferably, 12 material of metal layer is aluminium.The aluminium thickness range of deposition is 3~7 μm.
It should be noted that the production method of the present embodiment trench gate igbt chip further includes the following table in wafer substrate 2
Face forms back structures, and chip back structures can be punch, non-punch or soft punch, back process and existing core
Blade technolgy is consistent, therefore omits.
Using the production method of trench gate igbt chip provided in an embodiment of the present invention, by being needed between active groove
The lower section of metal contact hole is done, one or more empty gate grooves are inserted into, utilizes the width and empty gate groove of empty gate groove itself
Between spacing increase the size of metal contact hole, to reduce the formation process and metal filling perforation of metal contact window
Technology difficulty, and reduce the requirement to technique platform.Simultaneously using trench gate igbt chip provided by the embodiments of the present application
Production method not will increase the integrated artistic of the production method of trench gate igbt chip without increasing additional processing step
Complexity.Designer can also carry out the ruler of coordinated control metal contact hole by the setting to empty gate groove difference number simultaneously
Very little, in order to adapt to different technique equipment, this is set as designer and provides very big freedom degree.
Embodiment two
The present embodiment is further to be limited on the basis of example 1.
The production method of the present embodiment trench gate igbt chip is gone back in the step S110 of embodiment one between step S111
Include the following steps.
Step S201 is formed by way of deposition at the first contact window 13 and on remaining insulating medium layer 11
One layer of film dielectric layer 14, at least one of film dielectric layer SiO2, SiN, SiON.
Step S202 performs etching the 4th predeterminated position on film dielectric layer, forms the second contact window 15.
Specifically, the area P+ between empty grid and empty grid is set as the virtual area P+, by the thin-medium at the first contact window 13
Floor position not corresponding with the virtual area P+ is set as the 4th predeterminated position, carves to the 4th predeterminated position on film dielectric layer
Erosion forms the second contact window.At work, empty grid are in ground state to the trench gate igbt chip formed on this basis,
The virtual area P+ is in floating state.
Fig. 3 shows not formed metal layer made of the production method of trench gate igbt chip in the embodiment of the present invention two
The structural schematic diagram of trench gate igbt chip；Fig. 4 is the top view of trench gate igbt chip in the embodiment of the present invention two.
It is identical as the beneficial effect of Application Example one using the present embodiment, it is not repeated herein to it.
Embodiment three
The present embodiment is further to be limited on the basis of example 1.
The production method of the present embodiment trench gate igbt chip is gone back in the step S110 of embodiment one between step S111
Include the following steps.
Step S301 is formed by way of deposition at the first contact window 13 and on remaining insulating medium layer 11
One layer of film dielectric layer, at least one of film dielectric layer SiO2, SiN, SiON.
Step S302 performs etching the 4th predeterminated position on film dielectric layer, forms the second contact window.
Specifically, the area P+ between empty grid and empty grid is set as the virtual area P+, by the thin-medium at the first contact window 13
Layer is set as the 4th predeterminated position with not corresponding position on empty grid, performs etching to the 4th predeterminated position on film dielectric layer,
Form the second contact window.At work, the virtual area P+ is in ground state to the trench gate igbt chip formed on this basis,
Empty grid are in floating state.
Fig. 5 is the groove of not formed metal layer made of the production method of trench gate igbt chip in the embodiment of the present invention three
The structural schematic diagram of grid igbt chip；Fig. 6 is the top view of trench gate igbt chip in the embodiment of the present invention three.
It is identical as the beneficial effect of Application Example one using the present embodiment, it is not repeated herein to it.
Example IV
The present embodiment is further to be limited on the basis of example 1.
The production method of the present embodiment trench gate igbt chip is gone back in the step S110 of embodiment one between step S111
Include the following steps.
Step S401 is formed by way of deposition at the first contact window 13 and on remaining insulating medium layer 11
One layer of film dielectric layer, at least one of film dielectric layer SiO2, SiN, SiON.
Step S402 performs etching the 4th predeterminated position on film dielectric layer, forms the second contact window.
Specifically, the area P+ between empty grid and empty grid is set as the virtual area P+, by the thin-medium at the first contact window 13
Floor is set as the 4th predeterminated position with empty grid and the not corresponding position in the virtual area P+, to the 4th predeterminated position on film dielectric layer into
Row etching, forms the second contact window.The trench gate igbt chip formed on this basis at work, the virtual area P+ and empty grid
It is in floating state.
Fig. 7 is the knot of trench gate igbt chip made of the production method of trench gate igbt chip in the embodiment of the present invention four
Structure schematic diagram；Fig. 8 is the top view of trench gate igbt chip in the embodiment of the present invention four.
It is identical as the beneficial effect of Application Example one using the present embodiment, it is not repeated herein to it.
It should be noted that in addition to the above-mentioned lithographic method to film dielectric layer, it can also be to corresponding thin Jie of the first contact mouth
Matter layer carries out the etching of other forms, forms the second contact window of other forms, does not enumerate herein to it.
While it is disclosed that embodiment content as above but described only to facilitate understanding the present invention and adopting
Embodiment is not intended to limit the invention.Any those skilled in the art to which this invention pertains are not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and change can be made in the implementing form and in details,
But protection scope of the present invention still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of production method of trench gate igbt chip, which comprises the steps of:
Step 1: forming active groove and empty gate groove on wafer substrate, and the void gate groove is set to the active groove
Between；
Step 2: the second oxide layer is formed in the active groove and the empty gate groove inner surface, and in the active groove
Polysilicon is filled in the empty gate groove, forms real trench gate and empty trench gate；
Step 3: insulating medium layer is formed on the wafer substrate upper surface and the real trench gate and empty trench gate；
Step 4: performing etching the first predeterminated position on the insulating medium layer, and it is corresponding described at least to expose lower section
Part wafer substrate between empty trench gate and the real trench gate and empty trench gate, forms the first contact window.
2. manufacturing method according to claim 1, which is characterized in that further comprising the steps of before step 1:
The first oxide layer is formed in wafer substrate upper surface；
N-type impurity is injected into the wafer substrate, and so that it is spread the first junction depth and forms N trap；
P type impurity is injected into the N trap, and so that it is spread the second junction depth and forms p-well.
3. production method according to claim 2, which is characterized in that the step 1 specifically includes:
To the second predeterminated position and the p-well corresponding with the second predeterminated position lower section, N in first oxide layer
Wafer substrate below trap and the N trap performs etching, the empty grid for forming active groove and being set between the active groove
Groove, the empty gate groove between active groove described in any two are no less than one.
4. production method according to claim 3, which is characterized in that the step 2 specifically includes:
Remove remaining first oxide layer, and the table in the p-well upper surface, the active groove and the empty gate groove
Face forms the second oxide layer；
Polycrystalline is formed in second oxide layer of the p-well upper surface and in the active groove and the empty gate groove
Silicon layer, the polysilicon in the active groove and the empty gate groove are respectively filled with the active groove and the empty gate groove,
To form real trench gate and empty trench gate, second oxide layer of the p-well upper surface is etched away, and to the active groove
It is performed etching with the polysilicon in the empty gate groove, so that the polysilicon highest in the active groove and the empty gate groove
Point is poor lower than the wafer substrate upper surface preset height.
5. production method according to claim 4, which is characterized in that between the step 2 and step 3 further include as
Lower step:
Etch away second oxide layer of the p-well upper surface；
The third predeterminated position of the p-well upper surface between the real trench gate and empty trench gate injects N-type impurity, is formed
The area N+ of third junction depth, the area N+ are contacted with the real trench gate；
Injecting p-type impurity in the p-well at least between the real trench gate and empty trench gate, forms the area P+, the area N+
It is contacted with the area P+, and the area P+ is contacted with the empty trench gate.
6. production method according to claim 5, which is characterized in that the step 4 specifically includes:
The first predeterminated position on the insulating medium layer is performed etching, the corresponding empty groove in lower section is at least exposed
The area P+ between grid, the part area N+ and the real trench gate and empty trench gate, forms the first contact window.
7. production method according to claim 6, which is characterized in that further include following steps after the step 4:
The deposited metal layer on first contact window and the remaining insulating medium layer forms source electrode.
8. the production method according to claim 5 or 6, which is characterized in that first junction depth is greater than second knot
It is deep；Second junction depth is greater than the third junction depth.
9. the production method according to any one of claim 5 to 8, it is characterized in that, the p type impurity concentration in the p-well
Less than the p type impurity concentration in the area P+, the N-type impurity concentration in the N trap is less than the N-type impurity concentration in the area N+.
10. production method according to claim 1 to 9, it is characterized in that, it further include in the wafer substrate
Lower surface forms back structures, and the back structures are punch, non-punch or soft punch.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113066861A (en) * | 2019-12-16 | 2021-07-02 | 株洲中车时代半导体有限公司 | Trench gate power semiconductor device and manufacturing method thereof |
| CN117747672A (en) * | 2024-02-20 | 2024-03-22 | 深圳市威兆半导体股份有限公司 | SGT device and method of making same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582443A (en) * | 2008-05-13 | 2009-11-18 | 三菱电机株式会社 | Semiconductor device |
| JP2014179373A (en) * | 2013-03-13 | 2014-09-25 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method of the same |
| US20160149034A1 (en) * | 2014-11-26 | 2016-05-26 | Sinopower Semiconductor, Inc. | Power semiconductor device having low on-state resistance |
-
2018
- 2018-04-28 CN CN201810397165.5A patent/CN110416079A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582443A (en) * | 2008-05-13 | 2009-11-18 | 三菱电机株式会社 | Semiconductor device |
| JP2014179373A (en) * | 2013-03-13 | 2014-09-25 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method of the same |
| US20160149034A1 (en) * | 2014-11-26 | 2016-05-26 | Sinopower Semiconductor, Inc. | Power semiconductor device having low on-state resistance |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113066861A (en) * | 2019-12-16 | 2021-07-02 | 株洲中车时代半导体有限公司 | Trench gate power semiconductor device and manufacturing method thereof |
| CN113066861B (en) * | 2019-12-16 | 2023-04-07 | 株洲中车时代半导体有限公司 | Trench gate power semiconductor device and manufacturing method thereof |
| CN117747672A (en) * | 2024-02-20 | 2024-03-22 | 深圳市威兆半导体股份有限公司 | SGT device and method of making same |
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