CN205750814U - A kind of face identification system signal processing system based on bandwidth-limited circuit - Google Patents
A kind of face identification system signal processing system based on bandwidth-limited circuit Download PDFInfo
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- CN205750814U CN205750814U CN201620500934.6U CN201620500934U CN205750814U CN 205750814 U CN205750814 U CN 205750814U CN 201620500934 U CN201620500934 U CN 201620500934U CN 205750814 U CN205750814 U CN 205750814U
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Abstract
The utility model discloses a kind of face identification system signal processing system based on bandwidth-limited circuit, it is characterized in that, mainly by processing chip U, polar capacitor C8, N pole is connected with the FREP pin processing chip U, the diode D6 that P pole is connected with the RC pin processing chip U after resistance R16, the mixing tuning circuit being connected with process chip U, the signal frequency correcting circuit being connected with the COMP pin processing chip U after inductance L1, the signal pre-processing circuit being connected with signal frequency correcting circuit, and the bandwidth-limited circuit composition being serially connected between signal frequency correcting circuit and signal pre-processing circuit.This utility model carries out steady flat process to the high-low signal frequency in picture signal, and garbage signal frequency in picture signal is eliminated or decays simultaneously, make the transmission of the picture signal energy held stationary of input, thus this utility model can ensure that the accuracy of identification of face identification system.
Description
Technical field
This utility model relates to electronic applications, specifically, is a kind of face identification system based on bandwidth-limited circuit
Use signal processing system.
Background technology
Along with high-tech flourish, face identification system is wide by people because of its convenience as human body password
Model uses.In addition intelligent management has come into the social life of people now, and many Intelligent Buildings are rised sheer from level ground, suitable
Answer the epoch needs of information, as noble building and working environment, it is necessary to functionally meet the need of current and future development
Ask, become the base of culture and economic development.So face identification system is applied in the gate identification system of Balkh,
But because the interference signal in picture signal cannot be eliminated by the signal processing system of current face identification system, deposit simultaneously
Picture signal is being processed inaccurate, thus is causing the accuracy of identification of face identification system the highest, making face identification system know
Occur time other refusing to recognize situation, i.e. None-identified goes out client, or system has carried out wrong identification, and the place of causing carrys out personnel and enters into
Indoor, bring potential safety hazard.
Therefore it provides a kind of face identification system signal processing system that can improve capacity of resisting disturbance is when business
Anxious.
Utility model content
The purpose of this utility model is that the signal processing system overcoming face identification system of the prior art is anti-interference
Ability, to receive the inaccurate defect of signal processing, it is provided that a kind of based on bandwidth-limited circuit face identification system
Use signal processing system.
This utility model is achieved through the following technical solutions: a kind of face identification system based on bandwidth-limited circuit is used
Signal processing system, mainly by process chip U, N pole with process chip U FREP pin be connected, P pole after resistance R16 and
Processing the diode D6 that is connected of RC pin of chip U, positive pole is connected with the P pole of diode D6, negative pole and process chip U
The polar capacitor C8 that OUT pin is connected, the mixing tuning circuit being connected with process chip U, with process core after inductance L1
The signal frequency correcting circuit that the COMP pin of sheet U is connected, the Signal Pretreatment being connected with signal frequency correcting circuit electricity
Road, and the bandwidth-limited circuit composition being serially connected between signal frequency correcting circuit and signal pre-processing circuit；Described signal
Deaccentuator is connected with mixing tuning circuit.
Described bandwidth-limited circuit by amplifier P2, amplifier P3, positive pole is connected with the electrode input end of amplifier P2,
Negative pole as the input of bandwidth-limited circuit polar capacitor C9, the P pole that is connected with signal pre-processing circuit sequentially through electricity
Resistance R18 is connected with electrode input end with amplifier P2 after resistance R17, N pole after resistance R19 with the outfan of amplifier P2
The diode D7 being connected, positive pole is connected with the negative input of amplifier P2, the polar capacitor C10 of minus earth, negative pole
Be connected with the electrode input end of amplifier P3, polarity electricity that positive pole outfan with amplifier P2 after resistance R20 is connected
Hold C12, negative pole outfan with amplifier P3 after resistance R24 is connected, positive pole after resistance R21 with polar capacitor C12's
Polar capacitor C11, the N pole that positive pole is connected is connected with the outfan of amplifier P3, P pole after inductance L2 with polar capacitor
The diode D8 that the positive pole of C11 is connected, positive pole outfan with amplifier P3 after adjustable resistance R23 is connected, negative pole connects
The polar capacitor C13 on ground, and one end is connected with the negative input of amplifier P3, the other end is negative with polar capacitor C13's
The resistance R22 composition that pole is connected；The outfan of described amplifier P3 as bandwidth-limited circuit outfan and with signal frequency
Rate correcting circuit is connected.
Described signal pre-processing circuit is by amplifier P1, and positive pole is connected with the electrode input end of amplifier P1, negative pole is made
Be connected with the outfan of amplifier P1 for polar capacitor C1, the N pole of the input of signal pre-processing circuit, P pole is through resistance R1
The diode D1 that electrode input end with amplifier P1 is connected afterwards, positive pole is connected with the electrode input end of amplifier P1, bears
Polar capacitor C2, the P pole that pole is connected with the N pole of diode D1 after resistance R2 after resistance R5 with the outfan of amplifier P1
Be connected, diode D2 that N pole electrode input end with amplifier P1 after resistance R3 is connected, and negative pole and amplifier P1
The polar capacitor C3 that negative input is connected, positive pole is connected with the P pole of diode D2 after resistance R4 composition；Described put
The negative input ground connection of big device P1, its outfan is connected with the negative pole of polar capacitor C9.
Described signal frequency correcting circuit is connected with the outfan of amplifier P3 by audion VT, P pole, N pole is through inductance
It is connected with diode D4, the P pole that is connected of COMP pin processing chip U outfan with amplifier P1 after resistance R7 after L1
Connect, diode D3 that N pole is sequentially connected with the N pole of diode D4 after resistance R9 through resistance R8, positive pole after resistance R6 with
The polar capacitor C4 of ground connection, positive pole and two poles after the P pole of diode D4 is connected, negative pole is connected with the colelctor electrode of audion VT
The polar capacitor C5 that the N pole of pipe D4 is connected, negative pole is connected with the base stage of audion VT, and the N of one end and diode D4
The resistance R10 composition that pole is connected, the other end is connected with the emitter stage of audion VT；The emitter stage of described audion VT is with mixed
Frequently tuning circuit is connected.
Described mixing tuning circuit is connected with the THR pin processing chip U by one end, the other end and process chip U
The resistance R12 that CMIN pin is connected, negative pole with process chip U CMIN pin be connected, positive pole after resistance R11 with three poles
Polar capacitor C6, the P pole that the emitter stage of pipe VT is connected emitter stage with audion VT after resistance R13 is connected, N pole is through can
The diode D5 being connected with the OUT pin processing chip U after adjusting resistance R15, one end is connected with the CMIN pin processing chip U
Connect, resistance R14 that the other end is connected with the N pole of diode D5, and positive pole is connected with the REF pin of process chip U, negative
The polar capacitor C7 composition that pole is connected with the N pole of diode D5.
For practical effect of the present utility model, described process chip U preferentially have employed and comes into the integrated chip of LM331
Realize.
This utility model compared with prior art, has the following advantages and beneficial effect:
(1) this utility model has stronger capacity of resisting disturbance, can garbage signal frequency in picture signal be eliminated；Simultaneously
Harmonic wave in picture signal can be eliminated by this utility model, makes picture signal smoother, and can accurately transmit, thus really
The accuracy that picture signal is processed by the utility model that breaks even.
(2) this utility model can carry out frequency correction to picture signal, makes the transmission speed of each frequency of picture signal
Can keep consistent, thus effectively raise the accuracy that picture signal is processed by this utility model.
(3) mixing in picture signal can effectively be tuned by this utility model, makes each frequency of picture signal
Held stationary, clear, effectively ensure that picture signal can accurately be processed by this utility model, ensure that face
The accuracy of identification of identification system.
(4) this utility model can make the accuracy of identification of face identification system improve more than 70%, can effectively prevent face
Identification system carries out wrong identification, thus effectively raises the practicality of face identification system.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Fig. 2 is the electrical block diagram of bandwidth-limited circuit of the present utility model.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing thereof, this utility model is described in further detail, but reality of the present utility model
The mode of executing is not limited to this.
Embodiment
As it is shown in figure 1, this utility model is mainly by processing chip U, resistance R16, polar capacitor C8, diode D6, band is logical
Filter circuit, is mixed tuning circuit, signal frequency correcting circuit, and signal pre-processing circuit composition.
During enforcement, the N pole of diode D6 with process chip U FREP pin be connected, its P pole after resistance R16 with place
The RC pin of reason chip U is connected.The positive pole of polar capacitor C8 is connected with the P pole of diode D6, its negative pole with process chip U
OUT pin be connected.Mixing tuning circuit is connected with processing chip U.Signal frequency correcting circuit after inductance L1 with place
The COMP pin of reason chip U is connected.Its signal pre-processing circuit is connected with signal frequency correcting circuit.Bandwidth-limited circuit
It is serially connected between signal frequency correcting circuit and signal pre-processing circuit.Described signal frequency correcting circuit and mixing tuning circuit
It is connected.The OUT pin of described process chip U is connected with the controller of face identification system.
Wherein, described signal pre-processing circuit by amplifier P1, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5,
Polar capacitor C1, polar capacitor C2, polar capacitor C3, diode D1, and diode D2 form.
During connection, the positive pole of polar capacitor C1 is connected with the electrode input end of amplifier P1, its negative pole is pre-as signal
Process the input of circuit.The N pole of diode D1 is connected with the outfan of amplifier P1, its P pole after resistance R1 with amplification
The electrode input end of device P1 is connected.The positive pole of polar capacitor C2 is connected with the electrode input end of amplifier P1, its negative pole warp
After resistance R2, the N pole with diode D1 is connected.
Meanwhile, the P pole of diode D2 outfan with amplifier P1 after resistance R5 is connected, its N pole is after resistance R3
It is connected with the electrode input end of amplifier P1.The negative pole of polar capacitor C3 is connected with the negative input of amplifier P1, it
Positive pole P pole with diode D2 after resistance R4 is connected.The negative input ground connection of described amplifier P1, its outfan and pole
The negative pole of property electric capacity C9 is connected.
Further, described signal frequency correcting circuit by audion VT, resistance R6, resistance R7, resistance R8, resistance R9,
Resistance R10, polar capacitor C4, polar capacitor C5, diode D3, and diode D4 form.
During connection, the P pole of diode D4 is connected with the outfan of amplifier P3, its N pole after inductance L1 with process core
The COMP pin of sheet U is connected.The P pole of diode D3 outfan with amplifier P1 after resistance R7 is connected, its N pole sequentially
It is connected through resistance R8 N pole with diode D4 after resistance R9.The positive pole of polar capacitor C4 after resistance R6 with diode D4
P pole be connected, its negative pole be connected with the colelctor electrode of audion VT after ground connection.
Wherein, the positive pole of polar capacitor C5 is connected with the N pole of diode D4, its negative pole is connected with the base stage of audion VT
Connect.One end of resistance R10 is connected with the N pole of diode D4, its other end is connected with the emitter stage of audion VT.Described three
The emitter stage of pole pipe VT is connected with mixing tuning circuit.
Further, described mixing tuning circuit is by resistance R11, resistance R12, resistance R13, resistance R14, adjustable resistance
R15, polar capacitor C6, polar capacitor C7, diode D5, and inductance L1 form.
During connection, one end of resistance R12 is connected with the THR pin processing chip U, its other end with process chip U
CMIN pin is connected.The negative pole of polar capacitor C6 is connected with the CMIN pin processing chip U, its positive pole is after resistance R11
It is connected with the emitter stage of audion VT.The P pole of diode D5 emitter stage with audion VT after resistance R13 is connected, its N
Pole is connected with the OUT pin processing chip U after adjustable resistance R15.One end of resistance R14 and the CMIN pipe processing chip U
Foot is connected, its other end is connected with the N pole of diode D5.The positive pole of polar capacitor C7 and the REF pin phase processing chip U
Connect, its negative pole is connected with the N pole of diode D5.
As in figure 2 it is shown, described bandwidth-limited circuit is by amplifier P2, amplifier P3, resistance R17, resistance R18, resistance
R19, resistance R20, resistance R21, resistance R22, adjustable resistance R23, resistance R24, polar capacitor C9, polar capacitor C10, polarity electricity
Hold C11, polar capacitor C12, polar capacitor C13, diode D7, diode D8, and inductance L2 composition.
During connection, the positive pole of polar capacitor C9 is connected with the electrode input end of amplifier P2, its negative pole is filtered as band is logical
The input of wave circuit is also connected with signal pre-processing circuit.The P pole of diode D7 is sequentially after resistance R18 and resistance R17
Be connected with the electrode input end of amplifier P2, its N pole outfan with amplifier P2 after resistance R19 is connected.Polarity electricity
The positive pole of appearance C10 is connected with the negative input of amplifier P2, its minus earth.The negative pole of polar capacitor C12 and amplifier
The electrode input end of P3 is connected, its positive pole outfan with amplifier P2 after resistance R20 is connected.
Wherein, the negative pole of polar capacitor C11 outfan with amplifier P3 after resistance R24 is connected, its positive pole is through electricity
It is connected with the positive pole of polar capacitor C12 after resistance R21.The N pole of diode D8 is connected with the outfan of amplifier P3, its P pole
After inductance L2, the positive pole with polar capacitor C11 is connected.The positive pole of polar capacitor C13 after adjustable resistance R23 with amplifier
The outfan of P3 is connected, its minus earth.One end of resistance R22 is connected with the negative input of amplifier P3, its another
End is connected with the negative pole of polar capacitor C13.The outfan of described amplifier P3 as bandwidth-limited circuit outfan and with
Signal frequency correcting circuit is connected.
During operation, during operation, this utility model carries out steady putting down and processes the high-low signal frequency in picture signal, and simultaneously
Garbage signal frequency in picture signal is eliminated or decays；Harmonic wave in picture signal is disappeared by this utility model simultaneously
Remove, make picture signal smoother, make the transmission of the picture signal energy held stationary of input.This utility model and to transmission in letter
Number frequency is corrected, and makes the transmission speed of each frequency of picture signal can keep consistent, it is ensured that picture signal transmission steady
Fixed.Meanwhile, the mixing in picture signal is effectively tuned by this utility model, makes each frequency of picture signal keep flat
Surely, clearly, it is tuned after rear signal is analyzed processing by process chip U and obtains image information accurately, this utility model
The information obtained after processing chip U process can accurately be transferred to the controller of face identification system, ensures that face
The accuracy of identification of identification system.
This utility model can make the accuracy of identification of face identification system improve more than 70%, can effectively prevent recognition of face
System carries out wrong identification, thus effectively raises the practicality of face identification system.Actual make in order to of the present utility model
By effect, described process chip U preferentially have employed and realizes for the integrated chip of LM331.
According to above-described embodiment, can well realize this utility model.
Claims (6)
1. a face identification system signal processing system based on bandwidth-limited circuit, it is characterised in that main by processing
Chip U, N pole is connected with the FREP pin processing chip U, P pole is connected with the RC pin processing chip U after resistance R16
Diode D6, the polar capacitor that positive pole is connected with the P pole of diode D6, negative pole is connected with the OUT pin of process chip U
C8, the mixing tuning circuit being connected with process chip U, the letter being connected with the COMP pin processing chip U after inductance L1
Number deaccentuator, the signal pre-processing circuit being connected with signal frequency correcting circuit, and it is serially connected in signal frequency school
Bandwidth-limited circuit composition between positive circuit and signal pre-processing circuit；Described signal frequency correcting circuit and mixing tuning electricity
Road is connected.
A kind of face identification system signal processing system based on bandwidth-limited circuit the most according to claim 1, its
Being characterised by, described bandwidth-limited circuit is connected with the electrode input end of amplifier P2 by amplifier P2, amplifier P3, positive pole
Connect, negative pole is as the input of bandwidth-limited circuit polar capacitor C9, the P pole sequentially warp that is connected with signal pre-processing circuit
Resistance R18 is connected with electrode input end with amplifier P2 after resistance R17, N pole after resistance R19 with the output of amplifier P2
The diode D7 that end is connected, positive pole is connected with the negative input of amplifier P2, the polar capacitor C10 of minus earth, negative
The polarity that pole is connected with the electrode input end of amplifier P3, positive pole outfan with amplifier P2 after resistance R20 is connected
Electric capacity C12, negative pole outfan with amplifier P3 after resistance R24 is connected, positive pole after resistance R21 with polar capacitor C12
Polar capacitor C11, the N pole that is connected of positive pole be connected with the outfan of amplifier P3, P pole after inductance L2 with polar capacitor
The diode D8 that the positive pole of C11 is connected, positive pole outfan with amplifier P3 after adjustable resistance R23 is connected, negative pole connects
The polar capacitor C13 on ground, and one end is connected with the negative input of amplifier P3, the other end is negative with polar capacitor C13's
The resistance R22 composition that pole is connected；The outfan of described amplifier P3 as bandwidth-limited circuit outfan and with signal frequency
Rate correcting circuit is connected.
A kind of face identification system signal processing system based on bandwidth-limited circuit the most according to claim 2, its
Being characterised by, described signal pre-processing circuit is by amplifier P1, and positive pole is connected with the electrode input end of amplifier P1, negative pole is made
Be connected with the outfan of amplifier P1 for polar capacitor C1, the N pole of the input of signal pre-processing circuit, P pole is through resistance R1
The diode D1 that electrode input end with amplifier P1 is connected afterwards, positive pole is connected with the electrode input end of amplifier P1, bears
Polar capacitor C2, the P pole that pole is connected with the N pole of diode D1 after resistance R2 after resistance R5 with the outfan of amplifier P1
Be connected, diode D2 that N pole electrode input end with amplifier P1 after resistance R3 is connected, and negative pole and amplifier P1
The polar capacitor C3 that negative input is connected, positive pole is connected with the P pole of diode D2 after resistance R4 composition；Described put
The negative input ground connection of big device P1, its outfan is connected with the negative pole of polar capacitor C9.
A kind of face identification system signal processing system based on bandwidth-limited circuit the most according to claim 3, its
Being characterised by, described signal frequency correcting circuit is connected with the outfan of amplifier P3 by audion VT, P pole, N pole is through inductance
It is connected with diode D4, the P pole that is connected of COMP pin processing chip U outfan with amplifier P1 after resistance R7 after L1
Connect, diode D3 that N pole is sequentially connected with the N pole of diode D4 after resistance R9 through resistance R8, positive pole after resistance R6 with
The polar capacitor C4 of ground connection, positive pole and two poles after the P pole of diode D4 is connected, negative pole is connected with the colelctor electrode of audion VT
The polar capacitor C5 that the N pole of pipe D4 is connected, negative pole is connected with the base stage of audion VT, and the N of one end and diode D4
The resistance R10 composition that pole is connected, the other end is connected with the emitter stage of audion VT；The emitter stage of described audion VT is with mixed
Frequently tuning circuit is connected.
A kind of face identification system signal processing system based on bandwidth-limited circuit the most according to claim 4, its
Being characterised by, described mixing tuning circuit is connected with the THR pin processing chip U by one end, the other end and process chip U
The resistance R12 that CMIN pin is connected, negative pole with process chip U CMIN pin be connected, positive pole after resistance R11 with three poles
Polar capacitor C6, the P pole that the emitter stage of pipe VT is connected emitter stage with audion VT after resistance R13 is connected, N pole is through can
The diode D5 being connected with the OUT pin processing chip U after adjusting resistance R15, one end is connected with the CMIN pin processing chip U
Connect, resistance R14 that the other end is connected with the N pole of diode D5, and positive pole is connected with the REF pin of process chip U, negative
The polar capacitor C7 composition that pole is connected with the N pole of diode D5.
A kind of face identification system signal processing system based on bandwidth-limited circuit the most according to claim 5, its
Being characterised by, described process chip U is the integrated chip of LM331.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620500934.6U CN205750814U (en) | 2016-05-26 | 2016-05-26 | A kind of face identification system signal processing system based on bandwidth-limited circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620500934.6U CN205750814U (en) | 2016-05-26 | 2016-05-26 | A kind of face identification system signal processing system based on bandwidth-limited circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205750814U true CN205750814U (en) | 2016-11-30 |
Family
ID=57362176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620500934.6U Expired - Fee Related CN205750814U (en) | 2016-05-26 | 2016-05-26 | A kind of face identification system signal processing system based on bandwidth-limited circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205750814U (en) |
-
2016
- 2016-05-26 CN CN201620500934.6U patent/CN205750814U/en not_active Expired - Fee Related
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161130 Termination date: 20170526 |
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| CF01 | Termination of patent right due to non-payment of annual fee |