CN204347863U - A kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system - Google Patents
A kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system Download PDFInfo
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- CN204347863U CN204347863U CN201420740032.0U CN201420740032U CN204347863U CN 204347863 U CN204347863 U CN 204347863U CN 201420740032 U CN201420740032 U CN 201420740032U CN 204347863 U CN204347863 U CN 204347863U
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Abstract
The utility model discloses a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system, primarily of fingerprint capturer, be arranged on the control chip HV of fingerprint capturer inside, the finger scan circuit be connected with this control chip HV, the image acquisition units be connected with finger scan circuit, the imaging lens be connected with this image acquisition units and the beam excitation formula logic amplifying circuit be connected with control chip HV form; The asymmetric trigger circuit of described emitter-base bandgap grading manifold type are then by the asymmetric circuit of emitter-base bandgap grading manifold type; and the passive π type filtering circuit to be connected with its output terminal forms; it is characterized in that, between beam excitation formula logic amplifying circuit and the asymmetric circuit of emitter-base bandgap grading manifold type, be also serially connected with virtual protection emitter-base bandgap grading manifold type amplifying circuit.The utility model adds the brand-new asymmetric trigger circuit of emitter-base bandgap grading manifold type in traditional fingerprint recognition system, thoroughly can overcome the defect of the unstable properties existing for conventional fingerprint recognizer.
Description
Technical field
The utility model relates to a kind of fingerprint recognition system, specifically refers to a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system.
Background technology
At present, existing single fingerprint identification device generally all adopts a fingerprint capturer to realize, not only its collection, discriminating fingerprint and management function are more single, and its recognition efficiency is low, only can carry out the alignments of 1:1 or 1:N at one time to a user.Meanwhile, these single fingerprint identification device accuracy of identification are lower at present, unstable properties, once finger has dust or water stain, just often there will be the situation that can not identify continuously.Therefore, how effectively overcoming the function singleness that existing fingerprint recognition system exists, the defect that recognition efficiency is low and precision is not high, is the task of top priority of people.
Utility model content
The purpose of this utility model is to overcome current single fingerprint identification device function singleness, recognition efficiency is low and precision is not high defect, provides a kind of dependable performance, a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system that accuracy of identification is high.
The utility model is achieved through the following technical solutions: a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system, primarily of fingerprint capturer, be arranged on the control chip HV of fingerprint capturer inside, the finger scan circuit be connected with this control chip HV, the image acquisition units be connected with finger scan circuit, the imaging lens be connected with this image acquisition units, be arranged on the asymmetric trigger circuit of emitter-base bandgap grading manifold type between finger scan circuit and the tie point of image acquisition units, and the beam excitation formula logic amplifying circuit to be connected with control chip HV forms, the asymmetric trigger circuit of described emitter-base bandgap grading manifold type are then by the asymmetric circuit of emitter-base bandgap grading manifold type, and the passive π type filtering circuit be connected with its output terminal forms.
Meanwhile, between beam excitation formula logic amplifying circuit and the asymmetric circuit of emitter-base bandgap grading manifold type, virtual protection emitter-base bandgap grading manifold type amplifying circuit is also serially connected with, described beam excitation formula logic amplifying circuit is primarily of power amplifier P3, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, negative pole is connected with the in-phase end of power amplifier P3, the polar capacitor C8 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C8, the resistance R12 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R12, the polar capacitor C10 of minus earth, one end is connected with the negative input of Sheffer stroke gate IC1, the resistance R13 that the other end is connected with the in-phase end of power amplifier P3, be serially connected in the resistance R14 between the end of oppisite phase of power amplifier P3 and output terminal, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R16 that the other end is connected with the negative input of Sheffer stroke gate IC3, positive pole is connected with the output terminal of Sheffer stroke gate IC2, the electric capacity C9 that negative pole is connected with the negative input of Sheffer stroke gate IC3, and one end is connected with the positive pole of polar capacitor C10, the resistance R15 that the other end is connected with the negative input of Sheffer stroke gate IC2 forms, the electrode input end of described Sheffer stroke gate IC1 is connected with the end of oppisite phase of power amplifier P3, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2, and the electrode input end of Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P3, the output terminal of described Sheffer stroke gate IC3 is then connected with the CS1 pin of control chip HV.
Described virtual protection emitter-base bandgap grading manifold type amplifying circuit is primarily of triode Q5, triode Q6, power amplifier P4, power amplifier P5, be serially connected in the resistance R18 between the end of oppisite phase of power amplifier P4 and output terminal, be serially connected in the polar capacitor C13 between the in-phase end of power amplifier P5 and output terminal, be serially connected in the resistance R17 between the in-phase end of power amplifier P4 and the collector of triode Q5, be serially connected in the resistance R19 between the collector of triode Q5 and the base stage of triode Q6, the electric capacity C12 be in parallel with resistance R19, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C11 that positive pole is connected with the emitter of triode Q5 after resistance R20, be serially connected in the resistance R21 between the base stage of triode Q6 and the positive pole of polar capacitor C11, positive pole is connected with the emitter of triode Q6, negative pole is in turn through electric capacity C14 that voltage stabilizing diode D5 is connected with the output terminal of power amplifier P4 after resistance R22, P pole is connected with the output terminal of power amplifier P5, the diode D6 that N pole is connected with the tie point of resistance R22 with voltage stabilizing diode D5 after resistance R23 through resistance R24, and P pole is connected with the negative pole of electric capacity C14, the voltage stabilizing diode D7 that N pole is connected with the tie point of resistance R24 with diode D6 forms, the base stage of described triode Q5 is connected with the positive pole of polar capacitor C11, and its emitter is connected with the emitter of triode Q6, and its collector is connected with the end of oppisite phase of power amplifier P4, the collector of triode Q6 is connected with the end of oppisite phase of power amplifier P5, and the in-phase end of power amplifier P5 is connected with the output terminal of power amplifier P4, the described positive pole of polar capacitor C11 is connected with the negative input of Sheffer stroke gate IC3, and resistance R24 is then connected with the asymmetric circuit of emitter-base bandgap grading manifold type with the tie point of resistance R23.
Described emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, be serially connected in the first-level filtering wave circuit between the emitter of triode Q2 and the base stage of triode Q3, be serially connected in the resistance R7 between the collector of triode Q3 and the collector of diode Q2, be serially connected in the resistance R3 between the collector of triode Q1 and the collector of triode Q2, be serially connected in the secondary filter circuit between the emitter of triode Q1 and passive π type filtering circuit, be serially connected in three grades of filtering circuits between the base stage of triode Q1 and passive π type filtering circuit, and the resistance R2 be serially connected between the base stage of triode Q1 and passive π type filtering circuit and the resistance R6 be serially connected between the base stage of triode Q3 and passive π type filtering circuit forms, the base stage of described triode Q2 is connected with the collector of triode Q1, and its collector is connected with passive π type filtering circuit, the emitter of described triode Q2 and the equal ground connection of emitter of triode Q3, described resistance R24 is then connected with three grades of filtering circuits with the tie point of resistance R23.
Described passive π type filtered electrical routing capacitance C1, electric capacity C2, and the resistance R8 be serially connected between the positive pole of electric capacity C1 and the positive pole of electric capacity C2 forms; The collector of described triode Q2 is then connected with the positive pole of electric capacity C2.
Described finger scan circuit is connected with the GATE pin of main control chip HV by base stage, collector is connected with the CS pin of main control chip HV after the primary coil L1 of transformer T1 emitter is then successively through the triode Q4 that resistance R9 is connected with the CS pin of main control chip HV after resistance R10, and two backup each other and the secondary link I be connected with LED respectively and secondary link II composition.
Described secondary link I to be connected with the Same Name of Ends of the secondary coil L2 of transformer T1 the diode D1 that P pole is then connected with the non-same polarity of secondary coil L2 after resistance R12 by N pole, and form with the electric capacity C6 that resistance R12 is in parallel, and the two ends of this electric capacity C6 are then connected with the both positive and negative polarity of LED respectively; Meanwhile, the positive pole of electric capacity C6 is connected with the positive pole of electric capacity C1, and its negative pole is connected with the negative pole of electric capacity C1.
Described secondary link II to be connected with the Same Name of Ends of the secondary coil L3 of transformer T1 the diode D2 that P pole is then connected with the non-same polarity of secondary coil L3 after resistance R13 by N pole, and form with the electric capacity C7 that resistance R13 is in parallel, and the two ends of this electric capacity C7 are connected with the both positive and negative polarity of LED respectively; Meanwhile, the positive pole of electric capacity C7 is connected with the positive pole of electric capacity C1, and its negative pole is then connected with the negative pole of electric capacity C1.
For guaranteeing result of use, described electric capacity C1, electric capacity C2 are patch capacitor, and described first-level filtering wave circuit, secondary filter circuit and three grades of filtering circuits are RC filtering circuit.
The utility model compared with prior art, has the following advantages and beneficial effect:
(1) not only one-piece construction is very simple for the utility model, and it makes and very easy to use, and it interiorly at one time can also carry out fingerprint recognition to multiple user, and therefore its function is very powerful, can improve knowledge treatment effeciency significantly.
(2) the utility model adopts high precision identification processing system to be used as processing core, can increase exponentially fingerprint recognition efficiency, reliability and security, and is easier to the beneficial effect expanding fingerprint identification device function.
(3) the utility model adds the brand-new asymmetric trigger circuit of emitter-base bandgap grading manifold type in traditional fingerprint recognition system, therefore thoroughly can overcome the unstable properties existing for conventional fingerprint recognizer, on fingerprint, have dust or the water stain defect that can not identify.
Accompanying drawing explanation
Fig. 1 is integrated circuit structural representation of the present utility model.
Fig. 2 is virtual protection emitter-base bandgap grading manifold type amplification circuit structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but embodiment of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, the utility model is primarily of the fingerprint capturer being with Camera communication interface and USB communication interface, be arranged on the control chip HV of fingerprint capturer inside, the finger scan circuit be connected with this control chip HV, the image acquisition units be connected with finger scan circuit, and the imaging lens be connected with this image acquisition units forms.For guaranteeing the stable performance of the application; the application is also provided with the asymmetric trigger circuit of emitter-base bandgap grading manifold type between finger scan circuit and the tie point of image acquisition units; the beam excitation formula logic amplifying circuit be connected with the CS1 pin of control chip HV, and be serially connected in the virtual protection emitter-base bandgap grading manifold type amplifying circuit between beam excitation formula logic amplifying circuit and the asymmetric trigger circuit of emitter-base bandgap grading manifold type.
Described beam excitation formula logic amplifying circuit is primarily of power amplifier P3, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, negative pole is connected with the in-phase end of power amplifier P3, the polar capacitor C8 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C8, the resistance R12 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R12, the polar capacitor C10 of minus earth, one end is connected with the negative input of Sheffer stroke gate IC1, the resistance R13 that the other end is connected with the in-phase end of power amplifier P3, be serially connected in the resistance R14 between the end of oppisite phase of power amplifier P3 and output terminal, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R16 that the other end is connected with the negative input of Sheffer stroke gate IC3, positive pole is connected with the output terminal of Sheffer stroke gate IC2, the electric capacity C9 that negative pole is connected with the negative input of Sheffer stroke gate IC3, and one end is connected with the positive pole of polar capacitor C10, the resistance R15 that the other end is connected with the negative input of Sheffer stroke gate IC2 forms.
The electrode input end of described Sheffer stroke gate IC1 is connected with the end of oppisite phase of power amplifier P3, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2, and the electrode input end of Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P3; The output terminal of described Sheffer stroke gate IC3 is then connected with the CS1 pin of control chip HV.
The asymmetric trigger circuit of described emitter-base bandgap grading manifold type are then by the asymmetric circuit of emitter-base bandgap grading manifold type, and the passive π type filtering circuit be connected with its output terminal forms.Wherein, emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8 and electric capacity C3, electric capacity C4 and electric capacity C5 form.
Passive π type filtering circuit is by electric capacity C1, electric capacity C2, and is serially connected in the low-pass filter circuit that the resistance R8 between the positive pole of electric capacity C1 and the positive pole of electric capacity C2 forms.According to the actual requirements, this passive π type filtering circuit also can be high-pass filtering circuit.During connection, the negative pole of electric capacity C1 is connected with the negative pole of electric capacity C2, forms a loop to guarantee resistance R8, between electric capacity C1 and electric capacity C2.The positive pole of electric capacity C1 and negative pole then form output terminal of the present utility model.For guaranteeing result of use, electric capacity C1 and electric capacity C2 is patch capacitor.
As shown in Figure 1, resistance R5 and electric capacity C3 is in parallel, and forms first-level filtering wave circuit; Resistance R4 and electric capacity C4 is in parallel, and forms secondary filter circuit; Resistance R1 and electric capacity C5 is in parallel, and forms three grades of filtering circuits.During connection, first-level filtering wave circuit is serially connected between the emitter of triode Q2 and the base stage of triode Q3, resistance R7 is serially connected between the collector of triode Q3 and the collector of diode Q2, resistance R3 is serially connected between the collector of triode Q1 and the collector of triode Q2, secondary filter circuit is then serially connected between the emitter of triode Q1 and the negative pole of electric capacity C2, and three grades of filtering circuits are then serially connected between the base stage of triode Q1 and the negative pole of electric capacity C2.
Described resistance R2 is serially connected between the base stage of triode Q1 and the negative pole of electric capacity C2, and resistance R6 is then serially connected between the base stage of triode Q3 and the negative pole of electric capacity C2.For guaranteeing result of use, the base stage of this triode Q2 is connected with the collector of triode Q1, and its collector is connected with the positive pole of electric capacity C2, the emitter of triode Q2 and the equal ground connection of emitter of triode Q3.
Described finger scan circuit is then connected with the GATE pin of main control chip HV by base stage, collector is connected with the CS pin of main control chip HV after the primary coil L1 of transformer T1 emitter is then successively through the triode Q4 that resistance R9 is connected with the CS pin of main control chip HV after resistance R10, and two backup each other and the secondary link I be connected with LED respectively and secondary link II composition.For guaranteeing result of use, this main control chip HV preferentially adopts 9910B type integrated chip to realize.
Wherein, secondary link I to be connected with the Same Name of Ends of the secondary coil L2 of transformer T1 the diode D1 that P pole is then connected with the non-same polarity of secondary coil L2 after resistance R12 by N pole, and form with the electric capacity C6 that resistance R12 is in parallel, and the two ends of this electric capacity C6 are then connected with the both positive and negative polarity of LED respectively.
Secondary link II to be connected with the Same Name of Ends of the secondary coil L3 of transformer T1 the diode D2 that P pole is then connected with the non-same polarity of secondary coil L3 after resistance R13 by N pole, and form with the electric capacity C7 that resistance R13 is in parallel, and the two ends of this electric capacity C7 are connected with the both positive and negative polarity of LED respectively.
Meanwhile, electric capacity C1, electric capacity C6 and electric capacity C7 will be in parallel, and namely electric capacity C6 is connected with the positive pole of electric capacity C1 with the positive pole of electric capacity C7, and electric capacity C6 is connected with the negative pole of electric capacity C1 with the negative pole of electric capacity C7.
The structure of described virtual protection emitter-base bandgap grading manifold type amplifying circuit as shown in Figure 2, it is primarily of triode Q5, triode Q6, power amplifier P4, power amplifier P5, be serially connected in the resistance R18 between the end of oppisite phase of power amplifier P4 and output terminal, be serially connected in the polar capacitor C13 between the in-phase end of power amplifier P5 and output terminal, be serially connected in the resistance R17 between the in-phase end of power amplifier P4 and the collector of triode Q5, be serially connected in the resistance R19 between the collector of triode Q5 and the base stage of triode Q6, the electric capacity C12 be in parallel with resistance R19, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C11 that positive pole is connected with the emitter of triode Q5 after resistance R20, be serially connected in the resistance R21 between the base stage of triode Q6 and the positive pole of polar capacitor C11, positive pole is connected with the emitter of triode Q6, negative pole is in turn through electric capacity C14 that voltage stabilizing diode D5 is connected with the output terminal of power amplifier P4 after resistance R22, P pole is connected with the output terminal of power amplifier P5, the diode D6 that N pole is connected with the tie point of resistance R22 with voltage stabilizing diode D5 after resistance R23 through resistance R24, and P pole is connected with the negative pole of electric capacity C14, the voltage stabilizing diode D7 that N pole is connected with the tie point of resistance R24 with diode D6 forms.
Meanwhile, the base stage of described triode Q5 is connected with the positive pole of polar capacitor C11, and its emitter is connected with the emitter of triode Q6, and its collector is connected with the end of oppisite phase of power amplifier P4; The collector of triode Q6 is connected with the end of oppisite phase of power amplifier P5, and the in-phase end of power amplifier P5 is connected with the output terminal of power amplifier P4.
During connection, the positive pole of described polar capacitor C11 will be connected with the negative input of Sheffer stroke gate IC3, and resistance R24 is then connected with the tie point of electric capacity C5 with resistance R1 with the tie point of resistance R23.That is, resistance R24 and the tie point of resistance R23 are connected with the base stage of triode Q1 after resistance R1.
As mentioned above, just the utility model can be realized preferably.
Claims (6)
1. a virtual protection emitter-base bandgap grading manifold type fingerprint recognition system, primarily of fingerprint capturer, be arranged on the control chip HV of fingerprint capturer inside, the finger scan circuit be connected with this control chip HV, the image acquisition units be connected with finger scan circuit, the imaging lens be connected with this image acquisition units, be arranged on the asymmetric trigger circuit of emitter-base bandgap grading manifold type between finger scan circuit and the tie point of image acquisition units, and the beam excitation formula logic amplifying circuit be connected with control chip HV forms, the asymmetric trigger circuit of described emitter-base bandgap grading manifold type are then by the asymmetric circuit of emitter-base bandgap grading manifold type, and the passive π type filtering circuit to be connected with its output terminal forms, it is characterized in that, between beam excitation formula logic amplifying circuit and the asymmetric circuit of emitter-base bandgap grading manifold type, be also serially connected with virtual protection emitter-base bandgap grading manifold type amplifying circuit, described beam excitation formula logic amplifying circuit is primarily of power amplifier P3, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, negative pole is connected with the in-phase end of power amplifier P3, the polar capacitor C8 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C8, the resistance R12 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R12, the polar capacitor C10 of minus earth, one end is connected with the negative input of Sheffer stroke gate IC1, the resistance R13 that the other end is connected with the in-phase end of power amplifier P3, be serially connected in the resistance R14 between the end of oppisite phase of power amplifier P3 and output terminal, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R16 that the other end is connected with the negative input of Sheffer stroke gate IC3, positive pole is connected with the output terminal of Sheffer stroke gate IC2, the electric capacity C9 that negative pole is connected with the negative input of Sheffer stroke gate IC3, and one end is connected with the positive pole of polar capacitor C10, the resistance R15 that the other end is connected with the negative input of Sheffer stroke gate IC2 forms, the electrode input end of described Sheffer stroke gate IC1 is connected with the end of oppisite phase of power amplifier P3, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2, and the electrode input end of Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P3, the output terminal of described Sheffer stroke gate IC3 is then connected with the CS1 pin of control chip HV, described virtual protection emitter-base bandgap grading manifold type amplifying circuit is primarily of triode Q5, triode Q6, power amplifier P4, power amplifier P5, be serially connected in the resistance R18 between the end of oppisite phase of power amplifier P4 and output terminal, be serially connected in the polar capacitor C13 between the in-phase end of power amplifier P5 and output terminal, be serially connected in the resistance R17 between the in-phase end of power amplifier P4 and the collector of triode Q5, be serially connected in the resistance R19 between the collector of triode Q5 and the base stage of triode Q6, the electric capacity C12 be in parallel with resistance R19, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C11 that positive pole is connected with the emitter of triode Q5 after resistance R20, be serially connected in the resistance R21 between the base stage of triode Q6 and the positive pole of polar capacitor C11, positive pole is connected with the emitter of triode Q6, negative pole is in turn through electric capacity C14 that voltage stabilizing diode D5 is connected with the output terminal of power amplifier P4 after resistance R22, P pole is connected with the output terminal of power amplifier P5, the diode D6 that N pole is connected with the tie point of resistance R22 with voltage stabilizing diode D5 after resistance R23 through resistance R24, and P pole is connected with the negative pole of electric capacity C14, the voltage stabilizing diode D7 that N pole is connected with the tie point of resistance R24 with diode D6 forms, the base stage of described triode Q5 is connected with the positive pole of polar capacitor C11, and its emitter is connected with the emitter of triode Q6, and its collector is connected with the end of oppisite phase of power amplifier P4, the collector of triode Q6 is connected with the end of oppisite phase of power amplifier P5, and the in-phase end of power amplifier P5 is connected with the output terminal of power amplifier P4, the described positive pole of polar capacitor C11 is connected with the negative input of Sheffer stroke gate IC3, and resistance R24 is then connected with the asymmetric circuit of emitter-base bandgap grading manifold type with the tie point of resistance R23.
2. a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system according to claim 1, it is characterized in that, described emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, be serially connected in the first-level filtering wave circuit between the emitter of triode Q2 and the base stage of triode Q3, be serially connected in the resistance R7 between the collector of triode Q3 and the collector of diode Q2, be serially connected in the resistance R3 between the collector of triode Q1 and the collector of triode Q2, be serially connected in the secondary filter circuit between the emitter of triode Q1 and passive π type filtering circuit, be serially connected in three grades of filtering circuits between the base stage of triode Q1 and passive π type filtering circuit, and the resistance R2 be serially connected between the base stage of triode Q1 and passive π type filtering circuit and the resistance R6 be serially connected between the base stage of triode Q3 and passive π type filtering circuit forms, the base stage of described triode Q2 is connected with the collector of triode Q1, and its collector is connected with passive π type filtering circuit, the emitter of described triode Q2 and the equal ground connection of emitter of triode Q3, described resistance R24 is then connected with three grades of filtering circuits with the tie point of resistance R23.
3. a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system according to claim 2, is characterized in that, described passive π type filtered electrical routing capacitance C1, electric capacity C2, and the resistance R8 be serially connected between the positive pole of electric capacity C1 and the positive pole of electric capacity C2 forms; The collector of described triode Q2 is then connected with the positive pole of electric capacity C2.
4. a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system according to claim 3, it is characterized in that, described finger scan circuit is connected with the GATE pin of main control chip HV by base stage, collector is connected with the CS pin of main control chip HV after the primary coil L1 of transformer T1 emitter is then successively through the triode Q4 that resistance R9 is connected with the CS pin of main control chip HV after resistance R10, and two backup each other and the secondary link I be connected with LED respectively and secondary link II composition;
Described secondary link I to be connected with the Same Name of Ends of the secondary coil L2 of transformer T1 the diode D1 that P pole is then connected with the non-same polarity of secondary coil L2 after resistance R12 by N pole, and form with the electric capacity C6 that resistance R12 is in parallel, and the two ends of this electric capacity C6 are then connected with the both positive and negative polarity of LED respectively; Meanwhile, the positive pole of electric capacity C6 is connected with the positive pole of electric capacity C1, and its negative pole is connected with the negative pole of electric capacity C1;
Described secondary link II to be connected with the Same Name of Ends of the secondary coil L3 of transformer T1 the diode D2 that P pole is then connected with the non-same polarity of secondary coil L3 after resistance R13 by N pole, and form with the electric capacity C7 that resistance R13 is in parallel, and the two ends of this electric capacity C7 are connected with the both positive and negative polarity of LED respectively; Meanwhile, the positive pole of electric capacity C7 is connected with the positive pole of electric capacity C1, and its negative pole is then connected with the negative pole of electric capacity C1.
5. a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system according to claim 4, it is characterized in that, described electric capacity C1, electric capacity C2 are patch capacitor.
6. a kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system according to claim 5, it is characterized in that, described first-level filtering wave circuit, secondary filter circuit and three grades of filtering circuits are RC filtering circuit.
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|---|---|---|---|
| CN201420740032.0U CN204347863U (en) | 2014-11-28 | 2014-11-28 | A kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system |
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| CN201420740032.0U CN204347863U (en) | 2014-11-28 | 2014-11-28 | A kind of virtual protection emitter-base bandgap grading manifold type fingerprint recognition system |
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