CN104461462A - Novel logic protection emitter coupling type row address register system - Google Patents
Novel logic protection emitter coupling type row address register system Download PDFInfo
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- CN104461462A CN104461462A CN201410712289.XA CN201410712289A CN104461462A CN 104461462 A CN104461462 A CN 104461462A CN 201410712289 A CN201410712289 A CN 201410712289A CN 104461462 A CN104461462 A CN 104461462A
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Abstract
The invention discloses a novel logic protection emitter coupling type row address register system. The novel logic protection emitter coupling type row address register system is mainly composed of a direct-current conversion chip U, a row address register array connected with a pin P10 of the direct-current conversion chip U and a trigger circuit connected with a pin C1 and a pin C2 of the direct-current conversion chip U, and the trigger circuit is composed of an emitter coupling type asymmetric circuit and a passive Pi type filter circuit which is connected with the output end of the emitter coupling type asymmetric circuit. The novel logic protection emitter coupling type row address register system is characterized in that a light beam excitation type logic amplification circuit and a logic protection emitter coupling type amplification circuit are connected between the pin C2 and a pin C3 of the direct-current conversion chip U. According to the novel logic protection emitter coupling type row address register system, the overall structure is extremely simple, after the emitter coupling type asymmetric circuit is adopted to serve as the trigger circuit, power consumption of a row address register can be reduced to the maximum extent, and breakdown, caused by current pulses, of the register can be effectively prevented.
Description
Technical field
The present invention relates to a kind of register circuit, specifically refer to a kind of new logic protection emitter-base bandgap grading manifold type row address register system.
Background technology
Register is indispensable storage unit in CPU, and the size of its capacity and travelling speed directly determine the performance of CPU.At present, comparatively advanced is row address register and column address register, and no matter is which kind of register, and it all needs to be used as driving by circuit.But the row address register that current people use makes its energy consumption higher because its circuit structure is comparatively complicated, and arithmetic speed is comparatively slow, is not well positioned to meet the demand of the low energy consumption of people, high operation efficiency.
Summary of the invention
The object of the invention is to the defect that energy consumption is higher, arithmetic speed is lower overcome existing for current row address register, provide a kind of new logic to protect emitter-base bandgap grading manifold type row address register system.
Object of the present invention is achieved through the following technical solutions: a kind of new logic protection emitter-base bandgap grading manifold type row address register system, primarily of direct current conversion chip U, the row address register array be connected with the P10 pin of direct current conversion chip U, and form with the trigger circuit that the C1 pin of direct current conversion chip U is connected with C2 pin; Described trigger circuit are by the asymmetric circuit of emitter-base bandgap grading manifold type, and the passive π type filtering circuit be connected with its output terminal forms.Meanwhile, between the C2 pin and C3 pin of direct current conversion chip U, beam excitation formula logic amplifying circuit and virtual protection emitter-base bandgap grading manifold type amplifying circuit is also serially connected with.
Described beam excitation formula logic amplifying circuit is primarily of power amplifier P1, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, negative pole is connected with the in-phase end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D1, one end is connected with the positive pole of polar capacitor C6, the resistance R13 of other end ground connection after diode D2, positive pole is connected with the tie point of diode D2 with resistance R13, the polar capacitor C8 of minus earth, one end is connected with the negative input of Sheffer stroke gate IC1, the resistance R9 that the other end is connected with the in-phase end of power amplifier P1, be serially connected in the resistance R10 between the end of oppisite phase of power amplifier P1 and output terminal, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R11 that the other end is connected with the negative input of Sheffer stroke gate IC3, positive pole is connected with the output terminal of Sheffer stroke gate IC2, the electric capacity C7 that negative pole is connected with the negative input of Sheffer stroke gate IC3, and one end is connected with the positive pole of polar capacitor C8, the resistance R12 that the other end is connected with the negative input of Sheffer stroke gate IC2 forms, the electrode input end of described Sheffer stroke gate IC1 is connected with the end of oppisite phase of power amplifier P1, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2, and the electrode input end of Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P1, the in-phase end of power amplifier P1 is then connected with the C2 pin of direct current conversion chip U, and the output terminal of Sheffer stroke gate IC3 is then connected with virtual protection emitter-base bandgap grading manifold type amplifying circuit.
Described virtual protection emitter-base bandgap grading manifold type amplifying circuit is by triode Q4, triode Q5, power amplifier P2, power amplifier P3, be serially connected in the resistance R16 between the end of oppisite phase of power amplifier P2 and output terminal, be serially connected in the polar capacitor C11 between the in-phase end of power amplifier P3 and output terminal, be serially connected in the resistance R15 between the in-phase end of power amplifier P2 and the collector of triode Q4, be serially connected in the resistance R17 between the collector of triode Q4 and the base stage of triode Q5, the electric capacity C10 be in parallel with resistance R17, negative pole is connected with the in-phase end of power amplifier P2, the polar capacitor C9 that positive pole is connected with the emitter of triode Q4 after resistance R18, be serially connected in the resistance R19 between the base stage of triode Q5 and the positive pole of polar capacitor C9, positive pole is connected with the emitter of triode Q5, negative pole is in turn through electric capacity C12 that voltage stabilizing diode D3 is connected with the output terminal of power amplifier P2 after resistance R20, P pole is connected with the output terminal of power amplifier P3, the diode D4 that N pole is connected with the tie point of resistance R20 with voltage stabilizing diode D3 after resistance R21 through resistance R22, and P pole is connected with the negative pole of electric capacity C12, the voltage stabilizing diode D5 that N pole is connected with the tie point of resistance R22 with diode D4 forms, the base stage of described triode Q4 is connected with the positive pole of polar capacitor C9, and its emitter is connected with the emitter of triode Q5, and its collector is connected with the end of oppisite phase of power amplifier P2, the collector of triode Q5 is connected with the end of oppisite phase of power amplifier P3, and the in-phase end of power amplifier P3 is connected with the output terminal of power amplifier P2, the described positive pole of polar capacitor C9 is connected with the output terminal of Sheffer stroke gate IC3, and resistance R22 is then connected with the C3 pin of direct current conversion chip U with the tie point of resistance R21.
Described emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, be serially connected in the first-level filtering wave circuit between the emitter of triode Q2 and the base stage of triode Q3, be serially connected in the resistance R7 between the collector of triode Q3 and the collector of diode Q2, be serially connected in the resistance R3 between the collector of triode Q1 and the collector of triode Q2, be serially connected in the secondary filter circuit between the emitter of triode Q1 and passive π type filtering circuit, be serially connected in three grades of wave filters between the base stage of triode Q1 and passive π type filtering circuit, and the resistance R2 be serially connected between the base stage of triode Q1 and passive π type filtering circuit and the resistance R6 be serially connected between the base stage of triode Q3 and passive π type filtering circuit forms, the base stage of described triode Q2 is connected with the collector of triode Q1, and its collector is connected with passive π type filtering circuit, the emitter of described triode Q2 and the equal ground connection of emitter of triode Q3.
Described passive π type filtered electrical routing capacitance C1, electric capacity C2, and the resistance R8 be serially connected between the positive pole of electric capacity C1 and the positive pole of electric capacity C2 forms; The collector of described triode Q2 is then connected with the positive pole of electric capacity C2; Positive pole and the negative pole of electric capacity C1 then form output terminal.
For guaranteeing result of use, described electric capacity C1, electric capacity C2 are patch capacitor, and described row address register array is then made up of 6 row address register, and these 6 row address register are all connected through the P10 pin of switch S with direct current conversion chip U.
Described direct current conversion chip U is ZXLD1320 voltage-dropping type chip.
Compared with prior art, tool has the following advantages and beneficial effect in the present invention:
(1) one-piece construction of the present invention is very simple, after the asymmetric circuit of employing emitter-base bandgap grading manifold type is as trigger circuit, farthest can reduces the energy consumption of row address register, can effectively prevent current impulse puncturing register.
(2) the present invention adopts direct current conversion chip to be used as step-down chip, after in conjunction with the asymmetric circuit of emitter-base bandgap grading manifold type, can make that the access speed of row address register is more traditional provides more than 20%.
Accompanying drawing explanation
Fig. 1 is one-piece construction schematic diagram of the present invention.
Fig. 2 is virtual protection emitter-base bandgap grading manifold type amplification circuit structure schematic diagram of the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
As shown in Figure 1; the present invention is primarily of direct current conversion chip U; the row address register array be connected with the P10 pin of direct current conversion chip U; the trigger circuit be connected with C2 pin with the C1 pin of direct current conversion chip U, and the beam excitation formula logic amplifying circuit be serially connected between the C2 pin of direct current conversion chip U and C3 pin and virtual protection emitter-base bandgap grading manifold type amplifying circuit form.
In this application, this direct current conversion chip U preferentially adopts ZXLD1320 voltage-dropping type chip to realize.This ZXLD1320 voltage-dropping type chip is the special steady current change-over circuit of ZETEX company designs, and its input supply voltage VCC is 4 ~ 18V DC voltage, and its output current is 1.5A.
During connection, as shown in Figure 1, this beam excitation formula logic amplifying circuit is primarily of power amplifier P1, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, negative pole is connected with the in-phase end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D1, one end is connected with the positive pole of polar capacitor C6, the resistance R13 of other end ground connection after diode D2, positive pole is connected with the tie point of diode D2 with resistance R13, the polar capacitor C8 of minus earth, one end is connected with the negative input of Sheffer stroke gate IC1, the resistance R9 that the other end is connected with the in-phase end of power amplifier P1, be serially connected in the resistance R10 between the end of oppisite phase of power amplifier P1 and output terminal, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R11 that the other end is connected with the negative input of Sheffer stroke gate IC3, positive pole is connected with the output terminal of Sheffer stroke gate IC2, the electric capacity C7 that negative pole is connected with the negative input of Sheffer stroke gate IC3, and one end is connected with the positive pole of polar capacitor C8, the resistance R12 that the other end is connected with the negative input of Sheffer stroke gate IC2 forms.
The electrode input end of described Sheffer stroke gate IC1 is connected with the end of oppisite phase of power amplifier P1, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2, and the electrode input end of Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P1; The in-phase end of power amplifier P1 is then connected with the C2 pin of direct current conversion chip U, and the output terminal of Sheffer stroke gate IC3 is then connected with virtual protection emitter-base bandgap grading manifold type amplifying circuit.
For guaranteeing result of use, these trigger circuit are preferentially by the asymmetric circuit of emitter-base bandgap grading manifold type, and the passive π type filtering circuit be connected with its output terminal realizes.Wherein, emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8 and electric capacity C3, electric capacity C4 and electric capacity C5 form.
Passive π type filtering circuit is by electric capacity C1, electric capacity C2, and is serially connected in the low-pass filter circuit that the resistance R8 between the positive pole of electric capacity C1 and the positive pole of electric capacity C2 forms.According to the actual requirements, this passive π type filtering circuit also can be high-pass filtering circuit.During connection, the negative pole of electric capacity C1 is connected with the negative pole of electric capacity C2, forms a loop to guarantee resistance R8, between electric capacity C1 and electric capacity C2.The positive pole of electric capacity C1 and negative pole then form output terminal of the present invention.For guaranteeing result of use, electric capacity C1 and electric capacity C2 is patch capacitor.
Described resistance R5 and electric capacity C3 is in parallel, and forms first-level filtering wave circuit; Resistance R4 and electric capacity C4 is in parallel, and forms secondary filter circuit; Resistance R1 and electric capacity C5 is in parallel, and forms three grades of filtering circuits.During connection, first-level filtering wave circuit is serially connected between the emitter of triode Q2 and the base stage of triode Q3, resistance R7 is serially connected between the collector of triode Q3 and the collector of diode Q2, resistance R3 is serially connected between the collector of triode Q1 and the collector of triode Q2, secondary filter circuit is then serially connected between the emitter of triode Q1 and the negative pole of electric capacity C2, and three grades of wave filters are then serially connected between the base stage of triode Q1 and the negative pole of electric capacity C2.
Described resistance R2 is serially connected between the base stage of triode Q1 and the negative pole of electric capacity C2, and resistance R6 is then serially connected between the base stage of triode Q3 and the negative pole of electric capacity C2.For guaranteeing result of use, the base stage of this triode Q2 is connected with the collector of triode Q1, and its collector is connected with the positive pole of electric capacity C2, the emitter of triode Q2 and the equal ground connection of emitter of triode Q3
The array group of row address register array for being made up of 6 row address register, these described 6 row address register are all connected through the P10 pin of switch S with direct current conversion chip U.
The structure of described virtual protection emitter-base bandgap grading manifold type amplifying circuit as shown in Figure 2, it is by triode Q4, triode Q5, power amplifier P2, power amplifier P3, be serially connected in the resistance R16 between the end of oppisite phase of power amplifier P2 and output terminal, be serially connected in the polar capacitor C11 between the in-phase end of power amplifier P3 and output terminal, be serially connected in the resistance R15 between the in-phase end of power amplifier P2 and the collector of triode Q4, be serially connected in the resistance R17 between the collector of triode Q4 and the base stage of triode Q5, the electric capacity C10 be in parallel with resistance R17, negative pole is connected with the in-phase end of power amplifier P2, the polar capacitor C9 that positive pole is connected with the emitter of triode Q4 after resistance R18, be serially connected in the resistance R19 between the base stage of triode Q5 and the positive pole of polar capacitor C9, positive pole is connected with the emitter of triode Q5, negative pole is in turn through electric capacity C12 that voltage stabilizing diode D3 is connected with the output terminal of power amplifier P2 after resistance R20, P pole is connected with the output terminal of power amplifier P3, the diode D4 that N pole is connected with the tie point of resistance R20 with voltage stabilizing diode D3 after resistance R21 through resistance R22, and P pole is connected with the negative pole of electric capacity C12, the voltage stabilizing diode D5 that N pole is connected with the tie point of resistance R22 with diode D4 forms.
Meanwhile, the base stage of described triode Q4 is connected with the positive pole of polar capacitor C9, and its emitter is connected with the emitter of triode Q5, and its collector is connected with the end of oppisite phase of power amplifier P2; The collector of triode Q5 is connected with the end of oppisite phase of power amplifier P3, and the in-phase end of power amplifier P3 is connected with the output terminal of power amplifier P2.
During connection, the described positive pole of polar capacitor C9 is connected with the output terminal of Sheffer stroke gate IC3, and resistance R22 is then connected with the C3 pin of direct current conversion chip U with the tie point of resistance R21.
As mentioned above, just the present invention can be realized preferably.
Claims (6)
1. a new logic protection emitter-base bandgap grading manifold type row address register system, primarily of direct current conversion chip U, the row address register array be connected with the P10 pin of direct current conversion chip U, and form with the trigger circuit that the C1 pin of direct current conversion chip U is connected with C2 pin, described trigger circuit are by the asymmetric circuit of emitter-base bandgap grading manifold type, and the passive π type filtering circuit to be connected with its output terminal forms, it is characterized in that, between the C2 pin and C3 pin of direct current conversion chip U, be also serially connected with beam excitation formula logic amplifying circuit and virtual protection emitter-base bandgap grading manifold type amplifying circuit, described beam excitation formula logic amplifying circuit is primarily of power amplifier P1, Sheffer stroke gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, negative pole is connected with the in-phase end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D1, one end is connected with the positive pole of polar capacitor C6, the resistance R13 of other end ground connection after diode D2, positive pole is connected with the tie point of diode D2 with resistance R13, the polar capacitor C8 of minus earth, one end is connected with the negative input of Sheffer stroke gate IC1, the resistance R9 that the other end is connected with the in-phase end of power amplifier P1, be serially connected in the resistance R10 between the end of oppisite phase of power amplifier P1 and output terminal, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R11 that the other end is connected with the negative input of Sheffer stroke gate IC3, positive pole is connected with the output terminal of Sheffer stroke gate IC2, the electric capacity C7 that negative pole is connected with the negative input of Sheffer stroke gate IC3, and one end is connected with the positive pole of polar capacitor C8, the resistance R12 that the other end is connected with the negative input of Sheffer stroke gate IC2 forms, the electrode input end of described Sheffer stroke gate IC1 is connected with the end of oppisite phase of power amplifier P1, and its output terminal is connected with the electrode input end of Sheffer stroke gate IC2, and the electrode input end of Sheffer stroke gate IC3 is connected with the output terminal of power amplifier P1, the in-phase end of power amplifier P1 is then connected with the C2 pin of direct current conversion chip U, and the output terminal of Sheffer stroke gate IC3 is then connected with virtual protection emitter-base bandgap grading manifold type amplifying circuit,
Described virtual protection emitter-base bandgap grading manifold type amplifying circuit is by triode Q4, triode Q5, power amplifier P2, power amplifier P3, be serially connected in the resistance R16 between the end of oppisite phase of power amplifier P2 and output terminal, be serially connected in the polar capacitor C11 between the in-phase end of power amplifier P3 and output terminal, be serially connected in the resistance R15 between the in-phase end of power amplifier P2 and the collector of triode Q4, be serially connected in the resistance R17 between the collector of triode Q4 and the base stage of triode Q5, the electric capacity C10 be in parallel with resistance R17, negative pole is connected with the in-phase end of power amplifier P2, the polar capacitor C9 that positive pole is connected with the emitter of triode Q4 after resistance R18, be serially connected in the resistance R19 between the base stage of triode Q5 and the positive pole of polar capacitor C9, positive pole is connected with the emitter of triode Q5, negative pole is in turn through electric capacity C12 that voltage stabilizing diode D3 is connected with the output terminal of power amplifier P2 after resistance R20, P pole is connected with the output terminal of power amplifier P3, the diode D4 that N pole is connected with the tie point of resistance R20 with voltage stabilizing diode D3 after resistance R21 through resistance R22, and P pole is connected with the negative pole of electric capacity C12, the voltage stabilizing diode D5 that N pole is connected with the tie point of resistance R22 with diode D4 forms, the base stage of described triode Q4 is connected with the positive pole of polar capacitor C9, and its emitter is connected with the emitter of triode Q5, and its collector is connected with the end of oppisite phase of power amplifier P2, the collector of triode Q5 is connected with the end of oppisite phase of power amplifier P3, and the in-phase end of power amplifier P3 is connected with the output terminal of power amplifier P2, the described positive pole of polar capacitor C9 is connected with the output terminal of Sheffer stroke gate IC3, and resistance R22 is then connected with the C3 pin of direct current conversion chip U with the tie point of resistance R21.
2. a kind of new logic protection emitter-base bandgap grading manifold type row address register system according to claim 1, it is characterized in that, described emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, be serially connected in the first-level filtering wave circuit between the emitter of triode Q2 and the base stage of triode Q3, be serially connected in the resistance R7 between the collector of triode Q3 and the collector of diode Q2, be serially connected in the resistance R3 between the collector of triode Q1 and the collector of triode Q2, be serially connected in the secondary filter circuit between the emitter of triode Q1 and passive π type filtering circuit, be serially connected in three grades of wave filters between the base stage of triode Q1 and passive π type filtering circuit, and the resistance R2 be serially connected between the base stage of triode Q1 and passive π type filtering circuit and the resistance R6 be serially connected between the base stage of triode Q3 and passive π type filtering circuit forms, the base stage of described triode Q2 is connected with the collector of triode Q1, and its collector is connected with passive π type filtering circuit, the emitter of described triode Q2 and the equal ground connection of emitter of triode Q3.
3. a kind of new logic protection emitter-base bandgap grading manifold type row address register system according to claim 2, it is characterized in that, described passive π type filtered electrical routing capacitance C1, electric capacity C2, and the resistance R8 be serially connected between the positive pole of electric capacity C1 and the positive pole of electric capacity C2 forms; The collector of described triode Q2 is then connected with the positive pole of electric capacity C2; Positive pole and the negative pole of electric capacity C1 then form output terminal.
4. a kind of new logic protection emitter-base bandgap grading manifold type row address register system according to claim 3, it is characterized in that, described electric capacity C1, electric capacity C2 are patch capacitor.
5. a kind of new logic protection emitter-base bandgap grading manifold type row address register system according to claim 4; it is characterized in that; described row address register array is made up of 6 row address register, and these 6 row address register are all connected through the P10 pin of switch S with direct current conversion chip U.
6. a kind of new logic protection emitter-base bandgap grading manifold type row address register system according to any one of Claims 1 to 5, it is characterized in that, described direct current conversion chip U is ZXLD1320 voltage-dropping type chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410712289.XA CN104461462A (en) | 2014-11-28 | 2014-11-28 | Novel logic protection emitter coupling type row address register system |
| CN201510324068.XA CN104965688A (en) | 2014-11-28 | 2015-06-12 | Novel logic protection emitter coupling type double-filtering row address register system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410712289.XA CN104461462A (en) | 2014-11-28 | 2014-11-28 | Novel logic protection emitter coupling type row address register system |
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| CN104461462A true CN104461462A (en) | 2015-03-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410712289.XA Pending CN104461462A (en) | 2014-11-28 | 2014-11-28 | Novel logic protection emitter coupling type row address register system |
| CN201510324068.XA Withdrawn CN104965688A (en) | 2014-11-28 | 2015-06-12 | Novel logic protection emitter coupling type double-filtering row address register system |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510324068.XA Withdrawn CN104965688A (en) | 2014-11-28 | 2015-06-12 | Novel logic protection emitter coupling type double-filtering row address register system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104852711A (en) * | 2014-11-19 | 2015-08-19 | 成都冠深科技有限公司 | Phase-locked energy-saving pulse detection sensor based on pulse amplification trigger circuit |
-
2014
- 2014-11-28 CN CN201410712289.XA patent/CN104461462A/en active Pending
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2015
- 2015-06-12 CN CN201510324068.XA patent/CN104965688A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104852711A (en) * | 2014-11-19 | 2015-08-19 | 成都冠深科技有限公司 | Phase-locked energy-saving pulse detection sensor based on pulse amplification trigger circuit |
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| CN104965688A (en) | 2015-10-07 |
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Application publication date: 20150325 |