CN107645818A - A kind of light-controlled lamp signal processing system with the processing of signal offset drift - Google Patents
A kind of light-controlled lamp signal processing system with the processing of signal offset drift Download PDFInfo
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- CN107645818A CN107645818A CN201711092621.7A CN201711092621A CN107645818A CN 107645818 A CN107645818 A CN 107645818A CN 201711092621 A CN201711092621 A CN 201711092621A CN 107645818 A CN107645818 A CN 107645818A
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Abstract
The invention discloses a kind of light-controlled lamp signal processing system with the processing of signal offset drift, it is characterized in that, mainly by process chip U, triode VT1, signal offset correction circuit, the low-pass filter circuit being connected respectively with process chip U VINP pins and GNEG pins, the signal transmitting modulate circuit being connected respectively with triode VT1 emitter stage and process chip U, and the composition such as anti-electromagnetic wave interference circuit.The present invention can by input signal because of external interference electric wave and caused by Harmonics elimination or suppression；And the present invention can also be adjusted to the bandwidth of output signal, make output signal consistent with the collection signal inputted, accuracy of the present invention to signal transacting is ensured that, effectively ensure that the accuracy that open and close of the light-operated LED control system to LED control.
Description
Technical field
It is a kind of there is signal offset drift to handle specifically the present invention relates to a kind of signal processing system
Light-controlled lamp signal processing system.
Background technology
At present, because LED has the characteristics that energy consumption is low, service life is long and safety and environmental protection, it has become people
One of the main product of life lighting.People are realized to LED using acoustic control or light-operated control system more in life
Open and close.Light-operated LED control system can control the unlatching of LED and pass because of it according to the brightness of LED use environment
Close, and can effectively meet requirement of the people to LED in terms of energy-conservation, and enjoy the favor of people.It is however, existing light-operated
The signal processing system of LED control system is easily inaccurate to luminance signal processing by the Electromagnetic Interference in the external world, causes light-operated
Control system can not accurately control the open and close of LED according to the intensity of illumination of environment, so as to meet people well
Requirement in terms of energy-conservation.
Therefore it provides a kind of can be the task of top priority to the signal processing system of the accurate processing of luminance signal.
The content of the invention
It is an object of the invention to overcome the signal processing system of light-operated LED control system of the prior art easily by the external world
Electromagnetic Interference and to luminance signal processing it is inaccurate the defects of, there is provided it is a kind of with signal offset drift processing it is light-operated
Lamp signal processing system.
The present invention is achieved through the following technical solutions：A kind of light-controlled lamp with the processing of signal offset drift is with signal
Reason system, mainly by process chip U, triode VT1, concatenation process chip U FDBK pins and triode VT1 colelctor electrode it
Between signal offset correction circuit, N poles are connected with process chip U FDBK pins, P poles after resistance R6 with process chip U
Diode D2, the P pole that is connected of COM pins be connected after resistance R7 with process chip U VNEG pins, N poles and three poles
The diode D3 that pipe VT1 base stage is connected, the low pass filtered being connected respectively with process chip U VINP pins and GNEG pins
Wave circuit, the signal transmitting modulate circuit being connected respectively with triode VT1 emitter stage and process chip U, and and signal
The anti-electromagnetic wave interference circuit composition that transmitting modulate circuit is connected；The colelctor electrode of the triode VT1 is with process chip U's
FDBK pins are connected；The anti-electromagnetic wave disturbs circuit by FET MOS101, FET MOS102, amplifier
P101, polar capacitor C101, the P pole and polar capacitor that positive pole is connected with FET MOS101 drain electrode, negative pole is grounded
The diode D101 that C101 negative pole is connected, N poles are connected after adjustable resistance R101 with amplifier P101 negative pole, one end
It is connected with FET MOS101 grid, the inductance L101 that the other end is connected with FET MOS102 drain electrode, just
It is grounded after pole is connected after resistance R102 with diode D101 N poles, negative pole is connected with amplifier P101 output end
Polar capacitor C102, N pole is connected with FET MOS102 source electrode, N poles after resistance R103 with FET MOS102
The diode D102 that is connected of grid, one end is connected with diode D102 P poles, the other end and amplifier P101 output
The inductance L102 that is connected is held, and one end is connected with FET MOS102 grid, the other end and amplifier P101
The inductance L103 compositions that output end is connected；The drain electrode of the FET MOS101 is connected with signal transmitting modulate circuit,
FET MOS101 source electrode is connected with external power source；The grid of the FET MOS102 also with amplifier P101
Positive pole be connected；Output end of the output end of the amplifier P101 as anti-electromagnetic wave interference circuit.
The signal offset correction circuit is by triode VT2, triode VT3, positive pole after adjustable resistance R16 with triode
VT3 base stage is connected, negative pole as signal offset correction circuit input and be connected with process chip U FDBK pins
Polar capacitor C11, positive pole is connected after resistance R13 with polar capacitor C11 negative pole, negative pole ground connection polar capacitor C10,
It is connected after the adjustable resistance R18 of N poles with triode VT3 colelctor electrode, negative pole phase of the P poles after resistance R15 with polar capacitor C10
The diode D7 of connection, the pole that negative pole is connected with triode VT2 base stage, positive pole is connected with polar capacitor C11 negative pole
Property electric capacity C12, N poles are connected with triode VT2 colelctor electrode, positive pole of the P poles with polar capacitor C12 after resistance R14 is connected
Diode D5, the P pole connect is connected after resistance R19 with triode VT3 emitter stage, N poles are as signal offset correction circuit
Output end and the diode D6 that is connected with triode VT1 colelctor electrode, and positive pole after resistance R17 with triode VT2
Colelctor electrode be connected, polar capacitor C13 that negative pole is connected after resistance R20 with diode D6 N poles composition；Three pole
Pipe VT2 emitter stage is connected with adjustable resistance R16 adjustable end.
The low-pass filter circuit is by amplifier P1, and positive pole is connected with amplifier P1 positive pole, negative pole is as low pass filtered
The polar capacitor C1 of the input of wave circuit, one end is connected with polar capacitor C1 negative pole, the resistance R1 of other end ground connection, just
Pole is connected after resistance R2 with amplifier P1 negative pole, negative pole ground connection polar capacitor C2, positive pole after resistance R3 with amplification
Device P 1 positive pole is connected, negative pole is connected with amplifier P1 output end polar capacitor C3, P pole with amplifier P1 just
The diode D1 that pole is connected, N poles are connected after resistance R4 with polar capacitor C3 negative pole, and negative pole is with amplifier P1's
The polar capacitor C4 compositions that output end is connected, positive pole is connected after resistance R5 with process chip U GNEG pins；It is described to put
Big device P1 output end is connected with process chip U VINP pins.
The signal transmitting modulate circuit is connected by FET MOS, amplifier P2, N pole with FET MOS drain electrode
Connect, the diode D4 that P poles are connected after resistance R8 with process chip U VPOS pins, negative pole after resistance R11 with amplifier
The polar capacitor C5 that P2 output end is connected, positive pole is connected after resistance R9 with FET MOS drain electrode, one end and field
The adjustable resistance R10 that effect pipe MOS source electrode is connected, the other end is connected with amplifier P2 output end, negative pole are imitated with field
Should pipe MOS source electrode be connected, the polar capacitor C6 that positive pole is connected with amplifier P2 positive pole, positive pole and triode VT1's
The polar capacitor C7 that emitter stage is connected, negative pole is connected after resistance R12 with amplifier P2 negative pole, positive pole and amplifier P2
Output end be connected, polar capacitor C8 of the negative pole as the output end of signal transmitting modulate circuit, and positive pole and amplifier
The polar capacitor C9 compositions that P2 output end is connected, negative pole is connected with polar capacitor C8 negative pole；The polar capacitor C7
Negative pole ground connection；The grid of the FET MOS is connected with process chip U VOUT pins；The polar capacitor C8's
Negative pole is connected with FET MOS101 drain electrode.
For the practical effect of the present invention, the process chip U is then preferentially realized using AD603 integrated chips.
The present invention compared with prior art, has advantages below and beneficial effect：
(1) present invention can by input signal because of external interference electric wave and caused by Harmonics elimination or suppression；And the present invention
The bandwidth of output signal can also be adjusted, make output signal consistent with the collection signal inputted, ensure that the present invention
To the accuracy of signal transacting, it is accurate effectively to ensure that open and close of the light-operated LED control system to LED control
Property.
(2) the anti-electromagnetic wave interference circuit that the present invention is set can carry out scaling down processing to signal, i.e. the circuit will can input
The height frequency of signal separated, and the Electromagnetic Interference signal in height frequency is eliminated respectively, believes output
It is number more accurate, more steady.
(3) present invention can make signal to signal offset drift is corrected caused by the reasons such as temperature in signal transacting
Dead point held stationary, so as to improve the present invention to the accuracy of signal transacting.
(4) process chip of the invention employs AD603 integrated chips to realize, chip performance stabilization and external circuit
It is combined and effectively raises accuracy of the present invention to signal transacting.
Brief description of the drawings
Fig. 1 is the overall structure diagram of the present invention.
Fig. 2 is the electrical block diagram of signal offset correction circuit.
Fig. 3 is that the anti-electromagnetic wave of the present invention disturbs the electrical block diagram of circuit.
Embodiment
The present invention is described in further detail with reference to embodiment and its accompanying drawing, but embodiments of the present invention are not
It is limited to this.
Embodiment
As shown in figure 1, the present invention is mainly by process chip U, triode VT1, concatenation process chip U FDBK pins and three
Signal offset correction circuit between pole pipe VT1 colelctor electrode, N poles are connected with process chip U FDBK pins, P poles are through electricity
VNEG pin of diode D2, the P pole being connected after resistance R6 with process chip U COM pins after resistance R7 with process chip U
It is connected, the diode D3 that N poles are connected with triode VT1 base stage, the VINP pins and GNEG with process chip U are managed respectively
The low-pass filter circuit that pin is connected, the signal transmitting conditioning being connected respectively with triode VT1 emitter stage and process chip U
Circuit, and the anti-electromagnetic wave interference circuit composition being connected with signal transmitting modulate circuit；The colelctor electrode of the triode VT1
It is connected with process chip U FDBK pins.
Wherein, the low-pass filter circuit is by amplifier P1, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, pole
Property electric capacity C1, polar capacitor C2, polar capacitor C3, polar capacitor C4, and diode D1 composition.
During connection, polar capacitor C1 positive pole is connected with amplifier P1 positive pole, its negative pole is as low-pass filter circuit
Input and be connected with luminance sensor.Resistance R1 one end is connected with polar capacitor C1 negative pole, its another termination
Ground.Polar capacitor C2 positive pole is connected after resistance R2 with amplifier P1 negative pole, its negative pole ground connection.Polar capacitor C3 is just
Pole is connected after resistance R3 with amplifier P 1 positive pole, its negative pole is connected with amplifier P1 output end.
Meanwhile diode D1 P poles are connected with amplifier P1 positive pole, its N pole after resistance R4 with polar capacitor C3
Negative pole be connected.Polar capacitor C4 negative pole is connected with amplifier P1 output end, its positive pole after resistance R5 with processing
Chip U GNEG pins are connected.The output end of the amplifier P1 is connected with process chip U VINP pins.
Further, the signal launches modulate circuit by FET MOS, amplifier P2, resistance R8, resistance R9, can
Adjust resistance R10, resistance R11, resistance R12, polar capacitor C5, polar capacitor C6, polar capacitor C7, polar capacitor C8, polarity electricity
Hold C9, diode D4 compositions.
During connection, diode D4 N poles are connected with FET MOS drain electrode, its P pole after resistance R8 with handling core
Piece U VPOS pins are connected.Polar capacitor C5 negative pole is connected after resistance R11 with amplifier P2 output end, its just
Drain electrode of the pole with FET MOS after resistance R9 is connected.Adjustable resistance R10 one end and FET MOS source electrode phase
Connection, its other end are connected with amplifier P2 output end.
Meanwhile polar capacitor C6 negative pole is connected with FET MOS source electrode, the positive pole of its positive pole and amplifier P2
It is connected.Polar capacitor C7 positive pole is connected with triode VT1 emitter stage, its negative pole after resistance R12 with amplifier P2
Negative pole be connected.Polar capacitor C8 positive pole is connected with amplifier P2 output end, its negative pole launches conditioning as signal
The output end of circuit is simultaneously connected with light-operated LED controller.Polar capacitor C9 positive pole is connected with amplifier P2 output end,
Its negative pole is connected with polar capacitor C8 negative pole.The negative pole ground connection of the polar capacitor C7；The grid of the FET MOS
It is connected with process chip U VOUT pins.The negative pole of the polar capacitor C8 is connected with FET MOS101 drain electrode.
As shown in Fig. 2 the signal offset correction circuit is by triode VT2, triode VT3, resistance R13, resistance R14,
Resistance R15, adjustable resistance R16, resistance R17, adjustable resistance R18, resistance R19, resistance R20, polar capacitor C10, polar capacitor
C11, polar capacitor C12, polar capacitor C13, diode D5, diode D6, and diode D7 compositions.
During connection, polar capacitor C11 positive pole is connected after adjustable resistance R16 with triode VT3 base stage, its negative pole
As signal offset correction circuit input and be connected with process chip U FDBK pins.Polar capacitor C10 positive pole warp
It is connected after resistance R13 with polar capacitor C11 negative pole, its negative pole ground connection.With three after diode D7 N poles adjustable resistance R18
Pole pipe VT3 colelctor electrode is connected, its negative pole of P poles with polar capacitor C10 after resistance R15 is connected.Polar capacitor C12's
Negative pole is connected with triode VT2 base stage, its positive pole is connected with polar capacitor C11 negative pole.
Meanwhile diode D5 N poles are connected with triode VT2 colelctor electrode, its P pole is electric with polarity after resistance R14
The positive pole for holding C12 is connected.Diode D6 P poles are connected after resistance R19 with triode VT3 emitter stage, its N poles conduct
The output end of signal offset correction circuit is simultaneously connected with triode VT1 colelctor electrode.Polar capacitor C13 positive pole is through resistance
It is connected after R17 with triode VT2 colelctor electrode, its negative pole is connected after resistance R20 with diode D6 N poles.Described three
Pole pipe VT2 emitter stage is connected with adjustable resistance R16 adjustable end.
As shown in figure 3, the anti-electromagnetic wave disturbs circuit by FET MOS101, FET MOS102, amplifier
P101, polar capacitor C101, polar capacitor C102, adjustable resistance R101, resistance R102, resistance R103, diode D101, two poles
Pipe D102, inductance L101, inductance L012, and inductance L103 compositions.
During connection, polar capacitor C101 positive pole is connected with FET MOS101 drain electrode, negative pole ground connection.Diode
D101 P poles are connected with polar capacitor C101 negative pole, negative pole of the N poles with amplifier P101 after adjustable resistance R101 is connected
Connect.Inductance L101 one end is connected with FET MOS101 grid, the other end and FET MOS102 drain electrode phase
Connection.Polar capacitor C102 positive pole is connected after resistance R102 with diode D101 N poles, negative pole and amplifier P101
Output end is grounded after being connected.Diode D102 N poles are connected with FET MOS102 source electrode, N poles are through resistance R103
The grid with FET MOS102 is connected afterwards.Inductance L102 one end is connected with diode D102 P poles, the other end with
Amplifier P101 output end is connected.Inductance L103 one end is connected with FET MOS102 grid, the other end with
Amplifier P101 output end is connected.
The drain electrode of the FET MOS101 is connected with signal transmitting modulate circuit, FET MOS101 source
Pole is connected with external power source, and its external power source is 12V DC voltage.The grid of the FET MOS102 also with amplification
Device P101 positive pole is connected；The output end of the amplifier P101 as anti-electromagnetic wave interference circuit output end and with it is light-operated
LED control system is connected, and for light-operated LED control, system provides accurate control signal source, to ensure that light-operated LED control system can be accurate
True is controlled to LED.
Wherein, during the operation of anti-electromagnetic wave interference circuit, FET MOS101 and FET MOS102 and inductance
L101 forms frequency dividing circuit, grid output of the high-frequency signal in its signal through FET MOS101, and passes through inductance L101
Exported after carrying out magnetic reactance processing through FET MOS102；And the low frequency signal in signal is then through polar capacitor C101 and diode
The signalling channel that D101 is formed delivers to the low frequency amplification that amplifier P101 and adjustable resistance R101 and polar capacitor C102 are formed
Device enters line frequency amplification, and the low frequency signal after frequency amplification carries out magnetic reactance processing through inductance L103, finally after its separating treatment
Signal is merged into a complete signal frequency in the letter frequency passage that inductance L102 and diode D102 is formed.Therefore, should
Circuit separates to the height frequency of the signal of input by carrying out scaling down processing to signal, realizes the height to signal
Electromagnetic Interference signal in low frequency is eliminated respectively, makes output signal more accurate, more steady.
During implementation, the present invention can by input signal because of external interference electric wave and caused by Harmonics elimination or suppression；And this
Invention can also be adjusted to the bandwidth of output signal, make output signal consistent with the collection signal inputted.And at analysis
Signal after reason is converted to disturbs circuit to carry out scaling down processing to signal after accurate data-signal by anti-electromagnetic wave, i.e., to letter
Number height frequency separated, while the Electromagnetic Interference signal in height frequency is eliminated respectively, its anti-electromagnetic wave
Interference circuit finally provides an accurate control information for the controller of light-operated LED control system, and controller is then according to reception
Data-signal control the open and close of LED.
Meanwhile present invention employs AD603 integrated chips to be used as process chip U, the chip performance is stable and external electrical
Road, which is combined, effectively raises accuracy of the present invention to signal transacting.For the practical effect of the present invention, the place
Reason chip U is then preferentially realized using AD603 integrated chips.
According to above-described embodiment, you can realize the present invention well.
Claims (5)
1. a kind of light-controlled lamp signal processing system with the processing of signal offset drift, it is characterised in that mainly by processing core
Piece U, triode VT1, the signal bias correction electricity between concatenation process chip U FDBK pins and triode VT1 colelctor electrode
Road, N poles are connected with process chip U FDBK pins, P poles are connected after resistance R6 with process chip U COM pins two
Pole pipe D2, P pole is connected after resistance R7 with process chip U VNEG pins, N poles are connected with triode VT1 base stage
Diode D3, the low-pass filter circuit being connected respectively with process chip U VINP pins and GNEG pins, respectively with triode
The signal transmitting modulate circuit that VT1 emitter stage is connected with process chip U, and be connected with signal transmitting modulate circuit
Anti-electromagnetic wave interference circuit composition；The colelctor electrode of the triode VT1 is connected with process chip U FDBK pins；It is described anti-
Electromagnetic Interference circuit is by FET MOS101, FET MOS102, amplifier P101, positive pole and FET MOS101
Drain electrode be connected, polar capacitor C101, the P pole of negative pole ground connection is connected with polar capacitor C101 negative pole, N poles are through adjustable electric
The diode D101 being connected after resistance R101 with amplifier P101 negative pole, one end is connected with FET MOS101 grid
Connect, the inductance L101 that the other end is connected with FET MOS102 drain electrode, positive pole after resistance R102 with diode D101
N poles be connected, polar capacitor C102, the N pole that negative pole is grounded after being connected with amplifier P101 output end and FET
MOS102 source electrode is connected, N poles are connected after resistance R103 with FET MOS102 grid diode D102, one
End is connected with diode D102 P poles, the inductance L102 that the other end is connected with amplifier P101 output end, and one end
It is connected with FET MOS102 grid, the inductance L103 compositions that the other end is connected with amplifier P101 output end；
The drain electrode of the FET MOS101 is connected with signal transmitting modulate circuit, the FET MOS101 source electrode and outside
Power supply is connected；Positive pole of the grid of the FET MOS102 also with amplifier P101 is connected；The amplifier P101
Output end as anti-electromagnetic wave interference circuit output end.
2. a kind of light-controlled lamp signal processing system with the processing of signal offset drift according to claim 1, it is special
Sign is, the signal offset correction circuit is by triode VT2, triode VT3, positive pole after adjustable resistance R16 with triode
VT3 base stage is connected, negative pole as signal offset correction circuit input and be connected with process chip U FDBK pins
Polar capacitor C11, positive pole is connected after resistance R13 with polar capacitor C11 negative pole, negative pole ground connection polar capacitor C10,
It is connected after the adjustable resistance R18 of N poles with triode VT3 colelctor electrode, negative pole phase of the P poles after resistance R15 with polar capacitor C10
The diode D7 of connection, the pole that negative pole is connected with triode VT2 base stage, positive pole is connected with polar capacitor C11 negative pole
Property electric capacity C12, N poles are connected with triode VT2 colelctor electrode, positive pole of the P poles with polar capacitor C12 after resistance R14 is connected
Diode D5, the P pole connect is connected after resistance R19 with triode VT3 emitter stage, N poles are as signal offset correction circuit
Output end and the diode D6 that is connected with triode VT1 colelctor electrode, and positive pole after resistance R17 with triode VT2
Colelctor electrode be connected, polar capacitor C13 that negative pole is connected after resistance R20 with diode D6 N poles composition；Three pole
Pipe VT2 emitter stage is connected with adjustable resistance R16 adjustable end.
3. a kind of light-controlled lamp signal processing system with the processing of signal offset drift according to claim 2, it is special
Sign is that the low-pass filter circuit is by amplifier P1, and positive pole is connected with amplifier P1 positive pole, negative pole is as LPF
The polar capacitor C1 of the input of circuit, one end is connected with polar capacitor C1 negative pole, the resistance R1 of other end ground connection, positive pole
Be connected after resistance R2 with amplifier P1 negative pole, negative pole ground connection polar capacitor C2, positive pole after resistance R3 with amplifier P
Polar capacitor C3, the P pole and amplifier P1 positive pole phase that 1 positive pole is connected, negative pole is connected with amplifier P1 output end
The diode D1 that connection, N poles are connected after resistance R4 with polar capacitor C3 negative pole, and the output of negative pole and amplifier P1
The polar capacitor C4 compositions that end is connected, positive pole is connected after resistance R5 with process chip U GNEG pins；The amplifier
P1 output end is connected with process chip U VINP pins.
4. a kind of light-controlled lamp signal processing system with the processing of signal offset drift according to claim 3, it is special
Sign is that the signal transmitting modulate circuit is connected by FET MOS, amplifier P2, N pole with FET MOS drain electrode
Connect, the diode D4 that P poles are connected after resistance R8 with process chip U VPOS pins, negative pole after resistance R11 with amplifier
The polar capacitor C5 that P2 output end is connected, positive pole is connected after resistance R9 with FET MOS drain electrode, one end and field
The adjustable resistance R10 that effect pipe MOS source electrode is connected, the other end is connected with amplifier P2 output end, negative pole are imitated with field
Should pipe MOS source electrode be connected, the polar capacitor C6 that positive pole is connected with amplifier P2 positive pole, positive pole and triode VT1's
The polar capacitor C7 that emitter stage is connected, negative pole is connected after resistance R12 with amplifier P2 negative pole, positive pole and amplifier P2
Output end be connected, polar capacitor C8 of the negative pole as the output end of signal transmitting modulate circuit, and positive pole and amplifier
The polar capacitor C9 compositions that P2 output end is connected, negative pole is connected with polar capacitor C8 negative pole；The polar capacitor C7
Negative pole ground connection；The grid of the FET MOS is connected with process chip U VOUT pins；The polar capacitor C8's
Negative pole is connected with FET MOS101 drain electrode.
5. a kind of light-controlled lamp signal processing system with the processing of signal offset drift according to claim 6, it is special
Sign is that the process chip U is AD603 integrated chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711092621.7A CN107645818A (en) | 2017-11-08 | 2017-11-08 | A kind of light-controlled lamp signal processing system with the processing of signal offset drift |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711092621.7A CN107645818A (en) | 2017-11-08 | 2017-11-08 | A kind of light-controlled lamp signal processing system with the processing of signal offset drift |
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| CN107645818A true CN107645818A (en) | 2018-01-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110133206A (en) * | 2019-06-19 | 2019-08-16 | 金陵科技学院 | A kind of multi-parameter combined type water monitoring device and detection method |
-
2017
- 2017-11-08 CN CN201711092621.7A patent/CN107645818A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110133206A (en) * | 2019-06-19 | 2019-08-16 | 金陵科技学院 | A kind of multi-parameter combined type water monitoring device and detection method |
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