CN205750620U - The effectively current mirror of suppression supply voltage impact - Google Patents

Abstract

This utility model provides the current mirror of effectively suppression supply voltage impact, and it can be effectively improved the output electric current rejection ability to mains fluctuations, it is ensured that current precision；It includes reference current generating circuit, the first mirror image circuit, the second mirror image circuit and current output circuit, the outfan of described reference current generating circuit connects described first mirror image circuit, the input of the second mirror image circuit, described first mirror image circuit, the outfan output extremely described current output circuit of the second mirror image circuit.

Description

The effectively current mirror of suppression supply voltage impact

Technical field

The present invention relates to Analog Circuit Design technical field, especially a kind of current mirror, the current mirror of a kind of effective suppression supply voltage impact.

Background technology

In Analog Circuit Design, circuit module it is frequently necessary to use more accurate bias current, circuit performance is stabilized and increased extremely important by this, popularizing in particular with portable consumer electronics product in recent years, requiring that power supply voltage variation device within the specific limits can normally work, the design of current mirroring circuit is had higher requirement by this.

Traditional current mirroring circuit is as it is shown in figure 1, all pipes in circuit are desirable that and are operated in saturation region, and wherein the grid of PMOS PM1 connects the drain electrode of NMOS tube NM1, and the source electrode of PMOS PM1 connects power supply, and the drain electrode of PMOS PM1 connects the drain electrode of NMOS tube NM1；The grid of PMOS PM2 connects the drain electrode of NMOS tube NM1, and the source electrode of PMOS PM2 connects power supply, and the drain electrode of PMOS PM2 connects the drain electrode of NMOS tube NM2；The grid of NMOS tube NM1 connects external voltage offset port Vbias, the source ground of NMOS tube NM1；The grid of NMOS tube NM2 connects the drain electrode of NMOS tube NM2, the source ground of NMOS tube NM2；The grid of NMOS tube NM3 connects the drain electrode of NMOS tube NM2, the source ground of NMOS tube NM3, and the drain electrode of NMOS tube NM3 meets current output terminal mouth Iout1；The grid of NMOS tube NM3 connects the drain electrode of NMOS tube NM2, the source ground of NMOS tube NM3, and the drain electrode of NMOS tube NM4 meets current output terminal mouth Iout2；

On the premise of not considering channel-length modulation, according to the circuit formula (1) of saturation region metal-oxide-semiconductor it is

$I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{ox}\left(\frac{W}{L}\right){(V_{GS}-V_{TH})}^2---\left(1\right)$

If it is considered that the second-order effect of metal-oxide-semiconductor, can obtain the most accurate current formula (2) is

$I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{ox}{\left(\frac{W}{L}\right)}_{NM2}{(V_{GS}-V_{TH})}^2(1+{\mathrm{\λV}}_{DS})---\left(2\right)$

The electric current flowing through NMOS tube NM2 and NMOS tube NM3 does one now analyze simply:

$I_{DNM2}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{ox}{\left(\frac{W}{L}\right)}_{NM2}{(V_{GSNM2}-V_{THN})}^2(1+{\mathrm{\λV}}_{DSNM2})---\left(3\right)$

μ in formula_nFor electron mobility, dielectric constantWherein ε_oFor permittivity of vacuum,For silicon dioxide relative dielectric constant, t_oxFor the thickness of gate oxide, W is channel width, and L is channel length,It is referred to as the breadth length ratio of device, V_THFor the threshold voltage of metal-oxide-semiconductor, V_GSFor grid source voltage, V_DSFor drain-source step voltage；V_GSNM2For the grid of NMOS tube NM2 to source voltage, V_DSNM2For the drain electrode of NMOS tube NM2 to source voltage, for NMOS tube NM2, both are numerically equal, in like manner obtain flowing through the electric current of NMOS tube NM3

$I_{DNM3}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{ox}{\left(\frac{W}{L}\right)}_{NM3}{(V_{GSNM3}-V_{THN})}^2(1+{\mathrm{\λV}}_{DSNM3})---\left(4\right)$

V in formula_GSNM3For the grid of NMOS tube NM3 to source voltage, V_DSNM3For the drain electrode of NMOS tube NM3 to source voltage；

Because NMOS tube NM2 is identical with the grid voltage of NMOS tube NM3, formula (3), (4) two formulas are compared, and obtain

$\frac{I_{DNM2}}{I_{DNM3}}=\frac{{(W/L)}_{NM2}}{{(W/L)}_{NM3}}\left(\frac{1+{\mathrm{\λV}}_{DSNM2}}{1+{\mathrm{\λV}}_{DSNM3}}\right)---\left(5\right)$

Be can be seen that by above formula (5), the image current value replicated has two influence factors: 1. breadth length ratio, 2. the drain-source voltage deviation of current mirror pipe, but in fact, the conclusion of formula (5) is to obtain in the difference of the threshold voltage ignoring NMOS tube NM2 and NMOS tube NM3, in accurate current mirroring circuit, this factor of influence can not simply be ignored；Wherein the breadth length ratio of pipe can accomplish fairly small difference by the layout optimization of domain, therefore affecting mirror currents precision, to be heavily dependent on the drain-source voltage of mirror image pipe poor, and in conventional current mirror circuit, due to the defect in structure, the pressure reduction of two mirror image pipe drain-source voltages is bigger, particularly when fluctuation occurs in supply voltage, can cause the drain-source voltage of current output portion mirror image pipe that bigger change occurs therewith, cause exporting electric current substantial deviation design load.

Summary of the invention

For the problem that the drain-source voltage difference of existing current mirror mirror image pipe is big on output electric current impact, the invention provides the current mirror of a kind of effective suppression supply voltage impact, it can be effectively improved the output electric current rejection ability to mains fluctuations, it is ensured that current precision.

Its technical scheme is such, it is characterized in that: it includes reference current generating circuit, the first mirror image circuit, the second mirror image circuit and current output circuit, the outfan of described reference current generating circuit connects described first mirror image circuit, the input of the second mirror image circuit, described first mirror image circuit, the outfan output extremely described current output circuit of the second mirror image circuit.

It is further characterized by described reference current generating circuit and includes PMOS PM1, NMOS tube NM1, the grid of described PMOS PM1 connects the drain electrode of described NMOS tube NM1, the source electrode of described PMOS PM1 connects power supply, and the drain electrode of described PMOS PM1 connects the drain electrode of described NMOS tube NM1；The grid of described NMOS tube NM1 connects the bias voltage Vbias to external port, the source ground of described NMOS tube NM1；

Described first mirror image circuit includes PMOS PM2, NMOS tube NM2, the grid of described PMOS PM2 connects the drain electrode of described NMOS tube NM1, the source electrode of described PMOS PM2 connects power supply, the drain electrode of described PMOS PM2 connects the drain electrode of described NMOS tube NM2, the grid of described NMOS tube NM2 connects the drain electrode of described NMOS tube NM2, the source ground of described NMOS tube NM2；

Described second mirror image circuit includes PMOS PM3, NMOS tube NM7, NMOS tube NM8, the grid of described PMOS PM3 connects the drain electrode of described NMOS tube NM1, the source electrode of described PMOS PM3 connects power supply, the drain electrode of described PMOS PM3 connects the drain electrode of described NMOS tube NM7, the grid of described NMOS tube NM7 connects the drain electrode of described NMOS tube NM2, the source electrode of described NMOS tube NM7 connects the drain electrode of described NMOS tube NM8, the grid of described NMOS tube NM8 connects the drain electrode of described NMOS tube NM7, the source ground of described NMOS tube NM8；

Described current output circuit includes that NMOS tube NM3～NM6, the grid of described NMOS tube NM3 connect the drain electrode of described NMOS tube NM2, and the source electrode of described NMOS tube NM3 connects the drain electrode of described NMOS tube NM4, and the drain electrode of described NMOS tube NM3 meets current output terminal mouth Iout1；The grid of described NMOS tube NM4 connects the drain electrode of described NMOS tube NM7, the source ground of described NMOS tube NM4；The grid of described NMOS tube NM5 connects the drain electrode of NMOS tube NM2, and the source electrode of described NMOS tube NM5 connects the drain electrode of described NMOS tube NM6, and the drain electrode of described NMOS tube NM5 meets current output terminal mouth Iout2；The grid of described NMOS tube NM6 connects the drain electrode of described NMOS tube NM7, the source ground of described NMOS tube NM6；

Its further,

Described reference current generating circuit includes PMOS PM1, NMOS tube NM1, the grid of described PMOS pipe PM1 meets the bias voltage Vbias to external port, the source electrode of described PMOS PM1 connects power supply, the drain electrode of described PMOS PM1 connects the drain electrode of described NMOS tube NM1, the grid of described NMOS tube NM1 connects the drain electrode of described NMOS tube NM1, the source ground of described NMOS tube NM1；

Described first mirror image circuit includes PMOS PM2, NMOS tube NM2, the grid of described PMOS PM2 connects the drain electrode of described NMOS tube NM2, the source electrode of described PMOS PM2 connects power supply, the drain electrode of described PMOS PM2 connects the drain electrode of described NMOS tube NM2, the grid of described NMOS tube NM2 connects the drain electrode of described NMOS tube NM1, the source ground of described NMOS tube NM2；

Described second mirror image circuit includes PMOS PM7, PM8, NMOS tube NM3, the grid of described PMOS PM7 connects the drain electrode of described NMOS tube NM3, the source electrode of described PMOS PM7 connects power supply, the drain electrode of described PMOS PM7 connects the source electrode of described PMOS PM8, the grid of described PMOS PM8 connects the drain electrode of described NMOS tube NM2, the drain electrode of described PMOS PM8 connects the drain electrode of described NMOS tube NM3, the grid of described NMOS tube NM3 connects the drain electrode of described NMOS tube NM1, the source ground of described NMOS tube NM3；

nullDescribed current output circuit includes PMOS PM3～PM6，The grid of described PMOS PM3 connects the drain electrode of described NMOS tube NM3，The source electrode of described PMOS PM3 connects power supply，The drain electrode of described PMOS PM3 connects the source electrode of described PMOS PM4，The grid of described PMOS PM4 connects the drain electrode of described NMOS tube NM2，The drain electrode of described PMOS PM4 meets described current output terminal mouth Iout1，The grid of described PMOS PM5 connects the drain electrode of described NMOS tube NM3，The source electrode of described PMOS PM5 connects power supply，The drain electrode of described PMOS PM5 connects the source electrode of described PMOS PM6，The grid of described PMOS PM6 connects the drain electrode of described NMOS tube NM2，The drain electrode of described PMOS PM6 meets described current output terminal mouth Iout2.

The invention has the beneficial effects as follows, it is by the mirror image effect of two groups of mirror image circuits, current output circuit mirror image pipe drain-source voltage can be made equal, thus offset the error that channel-length modulation brings, can effectively suppress the mains fluctuations impact on output electric current, improve the PSRR of current mirror.

Accompanying drawing explanation

Fig. 1 is conventional current mirror circuit schematic diagram；

Fig. 2 is the circuit flow chart of the present invention；

Fig. 3 is the circuit diagram of a kind of embodiment of the present invention；

Fig. 4 is the circuit diagram of another embodiment of the present invention；

Fig. 5 is the simulation waveform that conventional current mirror circuit exports electric current when mains fluctuations；

Fig. 6 is the simulation waveform that circuit of the present invention exports electric current when mains fluctuations.

Detailed description of the invention

The present invention includes reference current generating circuit, the first mirror image circuit, the second mirror image circuit and current output circuit, the outfan of reference current generating circuit connects the first mirror image circuit, the input of the second mirror image circuit, and the first mirror image circuit, the outfan of the second mirror image circuit export to current output circuit.

Embodiment one

As shown in Figure 2 and Figure 3, reference current generating circuit includes PMOS PM1, NMOS tube NM1, and the grid of PMOS PM1 connects the drain electrode of NMOS tube NM1, and the source electrode of PMOS PM1 connects power supply, and the drain electrode of PMOS PM1 connects the drain electrode of NMOS tube NM1；The grid of NMOS tube NM1 connects the bias voltage Vbias to external port, the source ground of NMOS tube NM1；First mirror image circuit includes PMOS PM2, NMOS tube NM2, the grid of PMOS PM2 connects the drain electrode of NMOS tube NM1, and the source electrode of PMOS PM2 connects power supply, and the drain electrode of PMOS PM2 connects the drain electrode of NMOS tube NM2, the grid of NMOS tube NM2 connects the drain electrode of NMOS tube NM2, the source ground of NMOS tube NM2；Second mirror image circuit includes PMOS PM3, NMOS tube NM7, NMOS tube NM8, the grid of PMOS PM3 connects the drain electrode of NMOS tube NM1, the source electrode of PMOS PM3 connects power supply, the drain electrode of PMOS PM3 connects the drain electrode of NMOS tube NM7, the grid of NMOS tube NM7 connects the drain electrode of NMOS tube NM2, the source electrode of NMOS tube NM7 connects the drain electrode of NMOS tube NM8, and the grid of NMOS tube NM8 connects the drain electrode of NMOS tube NM7, the source ground of NMOS tube NM8；Current output circuit includes NMOS tube NM3～NM6, and the grid of NMOS tube NM3 connects the drain electrode of NMOS tube NM2, and the source electrode of NMOS tube NM3 connects the drain electrode of NMOS tube NM4, and the drain electrode of NMOS tube NM3 meets current output terminal mouth Iout1；The grid of NMOS tube NM4 connects the drain electrode of NMOS tube NM7, the source ground of NMOS tube NM4；The grid of NMOS tube NM5 connects the drain electrode of NMOS tube NM2, and the source electrode of NMOS tube NM5 connects the drain electrode of NMOS tube NM6, and the drain electrode of NMOS tube NM5 meets current output terminal mouth Iout2；The grid of NMOS tube NM6 connects the drain electrode of NMOS tube NM7, the source ground of NMOS tube NM6；Wherein, when circuit design, the quantity of current output terminal mouth, namely some metal-oxide-semiconductors in parallel between NMOS tube NM3 and NM5, NM4 and NM6 can be increased and decreased according to demand, thus be supplied to different circuit module and stablize high-precision electric current.

In work process, to the bias voltage Vbias of external port to produce stable reference current, (and in side circuit, layout in view of domain, often NMOS tube NM2 is divided into the series connection of two NMOS tube), acted on by NMOS tube NM7, the impact of insulating power supply voltage verses current outgoing mirror image tube, the namely impact on NMOS tube NM8, make NMOS tube NM4, NM6, the drain-source step voltage VDS of NM8 these three pipe is equal, thus effectively offset channel-length modulation and the drain voltage unequal error of the inconsistent threshold voltage brought, and can be seen that according to formula (2), to the NMOS tube under same technique, as long as ensureing gate-source voltage V_GSWith drain-source voltage V_DSEqual, the electric current flowing through NMOS tube is the most relevant with the breadth length ratio of pipe；Then under the effect of bias voltage Vbias, produce reference current Iref and flow through NMOS tube NM1, also this electric current is flow through with NMOS tube NM1 in PMOS PM1 so connected, by PMOS PM2 and the image copying of PM3, produce the electric current proportional to reference current Iref, the electric current then flowing through NMOS tube NM2 and PMOS PM2 is equal, flow through NMOS tube NM7, the electric current of NM8 and PMOS PM3 is the most equal, so breadth length ratio by regulation respective tubes just can regulate the size of output electric current, simultaneously, by NMOS tube NM3, NM5, the isolation of NM7, the fluctuation of supply voltage is to NMOS tube NM4, the impact of NM6 is effectively weakened, thus stabilize output electric current.

Then assume when supply voltage is 5V, carry out emulating (because metal-oxide-semiconductor is equivalently-sized, the output result of current output terminal mouth Iout1 or Iout2 is the most identical) for the output result of current output terminal mouth Iout1 or Iout2 of current mirroring circuit in conventional current mirror circuit and embodiment one:

When the simulation result of conventional current mirror circuit is as it is shown in figure 5, supply voltage changes between 3V to 5V, its output electric current wafts to 59.7uA from 44.6uA；

In embodiment one, the simulation result of current mirroring circuit is as shown in Figure 6, and when supply voltage changes equally between 3V to 5V, its output electric current wafts to 66.2uA from 64.1uA；

To sum up, drawn by analogous diagram and the simulation result of the current output terminal mouth of current mirroring circuit in conventional current mirror circuit and embodiment one, in embodiment one, the floating scope of output electric current of current mirroring circuit is less, thus has the rejection ability more higher than conventional current mirror circuit.

Embodiment two

As shown in Figure 4, reference current generating circuit includes PMOS PM1, NMOS tube NM1, the grid of PMOS PM1 meets the bias voltage Vbias to external port, the source electrode of PMOS PM1 connects power supply, the drain electrode of PMOS PM1 connects the drain electrode of NMOS tube NM1, the grid of NMOS tube NM1 connects the drain electrode of NMOS tube NM1, the source ground of NMOS tube NM1；First mirror image circuit includes PMOS PM2, NMOS tube NM2, the grid of PMOS PM2 connects the drain electrode of NMOS tube NM2, and the source electrode of PMOS PM2 connects power supply, and the drain electrode of PMOS PM2 connects the drain electrode of NMOS tube NM2, the grid of NMOS tube NM2 connects the drain electrode of NMOS tube NM1, the source ground of NMOS tube NM2；Second mirror image circuit includes PMOS PM7, PM8, NMOS tube NM3, the grid of PMOS PM7 connects the drain electrode of NMOS tube NM3, the source electrode of PMOS PM7 connects power supply, the drain electrode of PMOS PM7 connects the source electrode of PMOS PM8, the grid of PMOS PM8 connects the drain electrode of NMOS tube NM2, the drain electrode of PMOS PM8 connects the drain electrode of NMOS tube NM3, and the grid of NMOS tube NM3 connects the drain electrode of NMOS tube NM1, the source ground of NMOS tube NM3；Current output circuit includes PMOS PM3～PM6, the grid of PMOS PM3 connects the drain electrode of NMOS tube NM3, the source electrode of PMOS PM3 connects power supply, the drain electrode of PMOS PM3 connects the source electrode of PMOS PM4, the grid of PMOS PM4 connects the drain electrode of NMOS tube NM2, the drain electrode of PMOS PM4 meets current output terminal mouth Iout1, the grid of PMOS PM5 connects the drain electrode of NMOS tube NM3, the source electrode of PMOS PM5 connects power supply, the drain electrode of PMOS PM5 connects the source electrode of PMOS PM6, the grid of PMOS PM6 connects the drain electrode of NMOS tube NM2, the drain electrode of PMOS PM6 meets current output terminal mouth Iout2；Wherein, when circuit design, the quantity of current output terminal mouth, namely some metal-oxide-semiconductors in parallel between PMOS PM3 and PM5, PM4 and PM6 can be increased and decreased according to demand, thus be supplied to different circuit module and stablize high-precision electric current；And the operation principle in embodiment two is with embodiment one, then it is not discussed in detail, but the fluctuation of supply voltage directly acts on the source electrode of PMOS PM3, PM5 and PM7 in embodiment two, then there is no any shielding isolation, being affected by power supply can more greatly, so the inhibitory action of supply voltage can be slightly worse than embodiment one.

Claims (9)

1. the current mirror of effectively suppression supply voltage impact, it is characterized in that: it includes reference current generating circuit, the first mirror image circuit, the second mirror image circuit and current output circuit, the outfan of described reference current generating circuit connects described first mirror image circuit, the input of the second mirror image circuit, described first mirror image circuit, the outfan output extremely described current output circuit of the second mirror image circuit.

The most effectively current mirror of suppression supply voltage impact, it is characterized in that: described reference current generating circuit includes PMOS PM1, NMOS tube NM1, the grid of described PMOS PM1 connects the drain electrode of described NMOS tube NM1, the source electrode of described PMOS PM1 connects power supply, and the drain electrode of described PMOS PM1 connects the drain electrode of described NMOS tube NM1；The grid of described NMOS tube NM1 connects the bias voltage Vbias to external port, the source ground of described NMOS tube NM1.

The most effectively current mirror of suppression supply voltage impact, it is characterized in that: described first mirror image circuit includes PMOS PM2, NMOS tube NM2, the grid of described PMOS PM2 connects the drain electrode of NMOS tube NM1, the source electrode of described PMOS PM2 connects power supply, the drain electrode of described PMOS PM2 connects the drain electrode of described NMOS tube NM2, the grid of described NMOS tube NM2 connects the drain electrode of described NMOS tube NM2, the source ground of described NMOS tube NM2.

The most effectively current mirror of suppression supply voltage impact, it is characterized in that: described second mirror image circuit includes PMOS PM3, NMOS tube NM7, NMOS tube NM8, the grid of described PMOS PM3 connects the drain electrode of NMOS tube NM1, the source electrode of described PMOS PM3 connects power supply, the drain electrode of described PMOS PM3 connects the drain electrode of described NMOS tube NM7, the grid of described NMOS tube NM7 connects the drain electrode of NMOS tube NM2, the source electrode of described NMOS tube NM7 connects the drain electrode of described NMOS tube NM8, the grid of described NMOS tube NM8 connects the drain electrode of described NMOS tube NM7, the source ground of described NMOS tube NM8.

The most effectively current mirror of suppression supply voltage impact, it is characterized in that: described current output circuit includes NMOS tube NM3 ~ NM6, the grid of described NMOS tube NM3 connects the drain electrode of NMOS tube NM2, the source electrode of described NMOS tube NM3 connects the drain electrode of described NMOS tube NM4, and the drain electrode of described NMOS tube NM3 meets current output terminal mouth Iout1；The grid of described NMOS tube NM4 connects the drain electrode of NMOS tube NM7, the source ground of described NMOS tube NM4；The grid of described NMOS tube NM5 connects the drain electrode of NMOS tube NM2, and the source electrode of described NMOS tube NM5 connects the drain electrode of described NMOS tube NM6, and the drain electrode of described NMOS tube NM5 meets current output terminal mouth Iout2；The grid of described NMOS tube NM6 connects the drain electrode of described NMOS tube NM7, the source ground of described NMOS tube NM6.

The most effectively current mirror of suppression supply voltage impact, it is characterized in that: described reference current generating circuit includes PMOS PM1, NMOS tube NM1, the grid of described PMOS PM1 meets the bias voltage Vbias to external port, the source electrode of described PMOS PM1 connects power supply, the drain electrode of described PMOS PM1 connects the drain electrode of described NMOS tube NM1, the grid of described NMOS tube NM1 connects the drain electrode of described NMOS tube NM1, the source ground of described NMOS tube NM1.

The most effectively current mirror of suppression supply voltage impact, it is characterized in that: described first mirror image circuit includes PMOS PM2, NMOS tube NM2, the grid of described PMOS PM2 connects the drain electrode of described NMOS tube NM2, the source electrode of described PMOS PM2 connects power supply, the drain electrode of described PMOS PM2 connects the drain electrode of described NMOS tube NM2, the grid of described NMOS tube NM2 connects the drain electrode of NMOS tube NM1, the source ground of described NMOS tube NM2.

The most effectively current mirror of suppression supply voltage impact, it is characterized in that: described second mirror image circuit includes PMOS PM7, PM8, NMOS tube NM3, the grid of described PMOS PM7 connects the drain electrode of described NMOS tube NM3, the source electrode of described PMOS PM7 connects power supply, the drain electrode of described PMOS PM7 connects the source electrode of described PMOS PM8, the grid of described PMOS PM8 connects the drain electrode of NMOS tube NM2, the drain electrode of described PMOS PM8 connects the drain electrode of described NMOS tube NM3, the grid of described NMOS tube NM3 connects the drain electrode of NMOS tube NM1, the source ground of described NMOS tube NM3.

nullThe most effectively current mirror of suppression supply voltage impact，It is characterized in that: described current output circuit includes PMOS PM3 ~ PM6，The grid of described PMOS PM3 connects the drain electrode of NMOS tube NM3，The source electrode of described PMOS PM3 connects power supply，The drain electrode of described PMOS PM3 connects the source electrode of described PMOS PM4，The grid of described PMOS PM4 connects the drain electrode of NMOS tube NM2，The drain electrode of described PMOS PM4 meets current output terminal mouth Iout1，The grid of described PMOS PM5 connects the drain electrode of described NMOS tube NM3，The source electrode of described PMOS PM5 connects power supply，The drain electrode of described PMOS PM5 connects the source electrode of described PMOS PM6，The grid of described PMOS PM6 connects the drain electrode of described NMOS tube NM2，The drain electrode of described PMOS PM6 meets current output terminal mouth Iout2.