CN205595374U - 发光式封装结构 - Google Patents
发光式封装结构 Download PDFInfo
- Publication number
- CN205595374U CN205595374U CN201620393819.3U CN201620393819U CN205595374U CN 205595374 U CN205595374 U CN 205595374U CN 201620393819 U CN201620393819 U CN 201620393819U CN 205595374 U CN205595374 U CN 205595374U
- Authority
- CN
- China
- Prior art keywords
- light
- illuminated
- encapsulating structure
- lead
- emitting component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title abstract 3
- 210000002683 foot Anatomy 0.000 claims description 61
- 230000004888 barrier function Effects 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 15
- 238000005538 encapsulation Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 239000000741 silica gel Substances 0.000 description 5
- 229910002027 silica gel Inorganic materials 0.000 description 5
- 239000011230 binding agent Substances 0.000 description 4
- 229920000297 Rayon Polymers 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 238000004020 luminiscence type Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
- H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
- H01L33/502—Wavelength conversion materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/56—Materials, e.g. epoxy or silicone resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Abstract
一种发光式封装结构,包括:具有分离的两导脚的导线架、结合至该两导脚上的发光元件、以及连接该发光元件与该两导脚的多个导电元件,藉由该两导脚同时承受该发光元件的重量与应力,以平均分布应力,避免该发光式封装结构结合于电路板时发生倾斜问题或墓碑效应(Tombstoning),并使该发光式封装结构具备优良的光形。
Description
技术领域
本实用新型有关一种封装结构,尤指一种发光式封装结构。
背景技术
随着电子产业的蓬勃发展,电子产品在型态上趋于轻薄短小,在功能上则逐渐迈入高性能、高功能、高速度化的研发方向,其中,发光二极管(Light Emitting Diode,简称LED)因具有寿命长、体积小、高耐震性及耗电量低等优点,故广泛地应用于照光需求的电子产品中,因此,于工业上、各种电子产品、生活家电的应用日趋普及。
一般发光二极管分为垂直(vertical)型、面朝上(face up)型、覆晶(flip chip)型,其中,该垂直型LED的两电极分别位于相对的出光侧(即主要射出光线之侧)与接置侧(即结合至承载件之侧),面朝上型LED的两电极均位于出光侧,覆晶型LED的两电极均位于接置侧。
图1A揭示一种传统面朝上型LED封装结构1的剖面示意图。如图1A所示,该LED封装结构1包括:一导线架10、一发光二极管芯片11、一反射件12以及一硅胶13。
所述的导线架10具有多个导脚10a,10b,且该发光二极管芯片11设于其中一导脚10b上。
所述的发光二极管芯片11具有相对的出光侧11a与接置侧11b,该出光侧11a具有电极110,以藉由焊线15打线连接至该导脚10a上,且该发光二极管芯片11以其接置侧11b藉由结合层14(如黏胶)结合至该导脚10b上。
所述的反射件12嵌设该导线架10,并于上侧围绕该发光二极管芯片11而呈碗状,以供该发光二极管芯片11利用该反射件12的斜面12a朝上(如图所示的箭头)发出光线,且该些导脚10a,10b延伸突出该反射件12下侧。
所述的硅胶13形成于该反射件12的碗状中以包覆该发光二极管芯片11与焊线15,其中,该硅胶13表面设有荧光层(图略)、或者该硅胶13中混合有荧光粉。
然而,传统LED封装结构1中,该导线架10的热传导路径长及热阻大,且厚度极厚(约0.2㎜),故该LED封装结构1的散热效果不佳,且不利于微小化的需求。
图1B揭示一种悉知EMC(Epoxy Molding Compound)面朝上型LED封装结构1’的剖面示意图。如图1B所示,该LED封装结构1’包括:一导线架10’、一发光二极管芯片11、一反射件12以及一环氧树脂(Epoxy)13’。
所述的导线架10’具有一置晶垫100及一导脚101,且该发光二极管芯片11设于该置晶垫100上。
所述的发光二极管芯片11具有相对的出光侧11a与接置侧11b,该出光侧11a具有电极110,以藉由焊线15打线连接至该导脚101上,且该发光二极管芯片11以其接置侧11b藉由结合层14(如黏胶)结合至该置晶垫100上,其中,该置晶垫100承载整个发光二极管芯片11,故该置晶垫100的版面面积大于该导脚101的版面面积,如图1B’所示。
所述的反射件12设于该导线架10’的上、下侧,并于上侧围绕该发光二极管芯片11而呈碗状,以供该发光二极管芯片11利用该反射件12的斜面12a朝上(如图所示的箭头)发出光线,且于下侧露出该置晶垫100的下表面与该导脚101的下表面。
所述的环氧树脂13’形成于该反射件12的碗状中以包覆该发光二极管芯片11与焊线15,其中,该环氧树脂13’表面设有荧光层(图略)、或者该环氧树脂13’中混合有荧光粉。
然而,悉知LED封装结构1’中,该发光二极管芯片11仅设于该置晶垫100上,故该置晶垫100的载重与应力均大于该导脚101的载重与应力,致使应力分布不平均,导致后续利用表面贴焊技术(Surface Mount Technology,简称SMT)制程,将该LED封装结构1’设于电路板(图略)上的过程中,结合于该置晶垫100下侧与该导脚101下侧的焊锡(图略)容易产生共面性(coplanarity)不良,因而使该LED封装结构1’倾斜设置于该电路板上。
此外,因该置晶垫100的矩形版面面积大于该导脚101的矩形版面面积,故于后续进行SMT制程时,结合于该置晶垫100下侧的焊锡的体积会大于结合于该导脚101下侧的焊锡的体积,导致该些焊锡的体积及高度的差距大,致使该些焊锡也容易产生共面性不良,因而使该LED封装结构1’倾斜设置于该电路板上。
又,该导线架10’的厚度也很厚,致使该置晶垫100与该导脚101之间的距离也难以缩小,故不利于微小化的需求。
因此,如何克服悉知技术中的种种问题,实已成目前亟欲解决的课题。
实用新型内容
鉴于上述悉知技术的缺失,本实用新型提供一种发光式封装结构,避免该发光式封装结构结合于电路板时发生倾斜问题或墓碑效应。
本实用新型的发光式封装结构包括:导线架,其具有两导脚,且该两导脚之间具有缝隙;发光元件,其具有相对的出光侧与接置侧,其中该接置侧跨越该缝隙而结合至该两导脚上;以及多个导电元件,其连接该发光元件与该导脚。
前述的发光式封装结构中,该两导脚的版面面积为相同。
前述的发光式封装结构中,该两导脚的版面形状为相同。
前述的发光式封装结构中,该出光侧具有多个电极。
前述的发光式封装结构中,该接置侧具有多个电极。
前述的发光式封装结构中,该导电元件为焊线。例如,所述焊线连接对向的该导脚。
前述的发光式封装结构中,还包括设于该导线架上并围绕该发光元件的反射件。
前述的发光式封装结构中,还包括包覆该发光元件与所述焊线的封装层。
前述的发光式封装结构中,还包括设于该封装层上的荧光层,亦或该封装层中含有荧光粉。
前述的发光式封装结构中,该发光元件的表面具有荧光层。
前述的发光式封装结构中,还包括结合该导线架的绝缘层,且令该导线架的部分表面外露于该绝缘层。
由上可知,本实用新型的发光式封装结构,主要藉由将该发光元件的接置侧结合至该两导脚上,使该两导脚均承受该发光元件的重量与应力,以平均分布应力,故相较于悉知技术,于后续SMT制程中,结合于该两导脚下侧的焊锡的共面性良好,因而能避免该发光式封装结构于电路板上发生倾斜或墓碑效应(Tombstoning)的问题。所谓的墓碑效应为元件两端的金属接点与板面焊垫之间在焊锡性上可能有差异存在或两端散热的速率不同,导致焊锡的固化速率不同,故当经红外线或热熔焊后,会出现一端焊牢而另一端被拉起的现象。
此外,该两导脚的版面面积为相同或接近,故于后续进行SMT制程时,结合于该两导脚下侧的焊锡的体积及高度大致相同,使该些焊锡的共面性良好,因而能避免该发光式封装结构于电路板上发生倾斜的问题。
又,本实用新型的导线架的热传导路径极短及热阻极小,且厚度极薄,故该发光式封装结构的散热效果极佳,且符合微小化的需求。
另外,本实用新型的发光元件因跨设于该两导脚上,使该发光元件较容易设于该发光式封装结构的中间处,故对于该出光侧的上方,该发光元件的出光侧所发出的光线能均匀分布,使该发光式封装结构的光形较佳。
附图说明
图1A为悉知LED封装结构的剖面示意图;
图1B为另一悉知LED封装结构的剖面示意图;
图1B’为图1B的LED封装结构的导线架的下视图;
图2A为本实用新型的发光式封装结构的第一实施例的剖面示意图;
图2A’为本实用新型的发光式封装结构的导线架的下视图;
图2B为图2A的另一实施例;
图3为本实用新型的发光式封装结构的第二实施例的剖面示意图;以及
图3’为图3的另一实施例。
符号说明
1,1’ LED封装结构
10,10’,20 导线架
100 置晶垫
10a,10b,101,200,201 导脚
11 发光二极管芯片
11a,21a,31a 出光侧
11b,21b,31b 接置侧
110,210,310 电极
12 反射件
12a 斜面
13 硅胶
13’ 环氧树脂
14,24 结合层
15 焊线
2,2’,3,3’ 发光式封装结构
202 缝隙
21,31 发光元件
22,22’ 绝缘层
220 开孔
23,23’ 封装层
25,35 导电元件
t 宽度。
具体实施方式
以下藉由特定的具体实施例说明本实用新型的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本实用新型的其他优点及功效。
须知,本说明书所附附图所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本实用新型可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本实用新型所能产生的功效及所能达成的目的下,均应仍落在本实用新型所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”及“一”等的用语,也仅为便于叙述的明了,而非用以限定本实用新型可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本实用新型可实施的范畴。
图2A为本实用新型的发光式封装结构2的第一实施例的剖面示意图。如图2A所示,该发光式封装结构2包括:一导线架20、一发光元件21、多个导电元件25以及一封装层23。
所述的导线架20具有两相互分离设置的导脚200,201,且该两导脚200,201为片状,两者的版面面积相同或接近,亦即该两导脚200,201的版面面积可相同或不相同。
于本实施例中,该两导脚200,201的版面形状相同或接近,如矩形,且该两导脚200,201之间具有一缝隙202。
所述的发光元件21为水平式的面朝上(face up)型LED,其具有相对的出光侧21a与接置侧21b,该接置侧21b藉由结合层24(如黏胶)结合至该两导脚200,201上,且该出光侧21a具有两电极210。
于本实施例中,该发光元件21为LED晶粒或已封装的LED封装件(如已将荧光层涂布于芯片表面的LED,俗称White chip),且该发光元件21的接置侧21b跨越该两导脚200,201间的缝隙202而结合至该两导脚200,201上。
所述的导电元件25为焊线,具有相对的两端接点,且单一焊线的两端接点分别连接该电极210与该导脚200,201。
于本实施例中,该些焊线连接同向的导脚200,201,即左边焊线连接左边导脚201。于其它实施例中,该些焊线也可连接对向的导脚200,201,即左边焊线连接右边导脚200,使各该焊线为相互交错跨设但并未不会相互接触。
所述的封装层23形成于该导线架20上以包覆该发光元件21与该些导电元件25。
于本实施例中,该封装层23表面可设具有荧光层(图略);或者,可将荧光层(图略)涂布于该发光元件21的表面上。于其它实施例中,如图2B所示的发光式封装结构2’,可于该封装层23’中混合有荧光粉。
此外,该封装层23的轮廓形状可为矩形(如图2A所示)、弧形(如镜面)或其它形状等,并无特别限制。
所述的发光式封装结构2还包括一结合该导线架20的绝缘层22,且令该导线架20的部分表面外露于该绝缘层22。
于本实施例中,该绝缘层22为防焊层(solder mask),其设于该导线架20下侧,且具有多个开孔220,以令各该导脚200,201的部分下表面外露于各该开孔220,以供结合焊锡(图略)。因此,该绝缘层22的开孔220能控制各该导脚200,201的外露面积。
于另一实施例中,如图2B所示的发光式封装结构2’,该绝缘层22可设于该导线架20上侧,且具有多个开孔220,以令各该导脚200,201的部分上表面外露于各该开孔220,以供结合该些导电元件25,而各该导脚200,201的下表面外露于该封装层23’以结合焊锡(图略)。
于另一实施例中,所述的发光式封装结构2,2’还包括一反射件(可参考图1A及图1B所示的反射件12),其设于该导线架20上侧并围绕该发光元件21而呈碗状结构,使该发光元件21利用该反射件的斜面朝上发出光线。
另外,本实用新型的发光元件21为打线式,其成本低,且该发光元件21的接置侧21b接触该两导脚200,201的面积越多,则散热效果越好,故该缝隙202的宽度t越小越好,如图2A’所示。
图3为本实用新型的发光式封装结构3的第二实施例的剖面示意图。本实施例与第一实施例的差异在于发光元件的种类,其它结构大致相同,故以下仅说明相异处,而不再赘述相同处。
如图3所示,依据图2A的结构改变,即该发光元件31为覆晶型LED,其具有相对的出光侧31a与接置侧31b,该接置侧31b具有两电极310,以令该接置侧31b的电极310藉由导电元件35结合至该两导脚200,201上。
于本实施例中,该导电元件35为焊锡、共晶接合结构、银胶、导电胶或其它导电材料等,并无特别限制。
此外,应可理解地,如图3’所示的发光式封装结构3’,亦可将图2B的发光元件与导电元件改为如图3所示的发光元件31与导电元件35。
综上所述,本实用新型的发光式封装结构2,2’,3,3’,主要藉由将该发光元件21,31的接置侧21b,31b结合至该两导脚200,201上,使该两导脚200,201同时承受该发光元件21,31的重量与应力,以平均分布应力,故于后续SMT制程中,结合于该两导脚200,201下侧的焊锡(图略)的共面性良好,因而能避免该发光式封装结构2,2’,3,3’于电路板上发生倾斜或墓碑效应(Tombstoning)的问题。
此外,由于该两导脚200,201的版面面积相同,故于后续进行SMT制程时,结合于该两导脚200,201下侧的焊锡(图略)的体积及高度大致相同,因而该些焊锡的共面性良好,进而能避免该发光式封装结构2,2’,3,3’于电路板上发生倾斜的问题。
又,该导线架20的导脚200,201为矩形片,因而热传导路径极短及热阻极小,且厚度极薄(约0.045㎜),故该发光式封装结构2,2’,3,3’的散热效果极佳,且符合微小化的需求。
另外,本实用新型的发光元件21,31因跨设于该两导脚200,201上,使该发光元件21,31较容易设于该发光式封装结构2,2’,3,3’的中间处,故对于该出光侧31a的上方,该发光元件21,31的出光侧31a所发出的光线能均匀分布,使该发光式封装结构2,2’,3,3’的光形较佳。
上述实施例仅用以例示性说明本实用新型的原理及其功效,而非用于限制本实用新型。任何本领域技术人员均可在不违背本实用新型的精神及范畴下,对上述实施例进行修改。因此本实用新型的权利保护范围,应如权利要求书所列。
Claims (13)
1.一种发光式封装结构,其特征为,该结构包括:
导线架,其具有两导脚,且该两导脚之间具有缝隙;
发光元件,其具有相对的出光侧与接置侧,其中该接置侧跨越该缝隙而结合至该两导脚上;以及
多个导电元件,其连接该发光元件与该导脚。
2.根据权利要求1所述的发光式封装结构,其特征为,该两导脚的版面面积相同。
3.根据权利要求1所述的发光式封装结构,其特征为,该两导脚的版面形状为相同。
4.根据权利要求1所述的发光式封装结构,其特征为,该出光侧具有多个电极。
5.根据权利要求1所述的发光式封装结构,其特征为,该接置侧具有多个电极。
6.根据权利要求1所述的发光式封装结构,其特征为,该导电元件为焊线。
7.根据权利要求6所述的发光式封装结构,其特征为,所述焊线连接对向的该导脚。
8.根据权利要求1所述的发光式封装结构,其特征为,该结构还包括设于该导线架上并围绕该发光元件的反射件。
9.根据权利要求1所述的发光式封装结构,其特征为,该结构还包括包覆该发光元件与所述导电元件的封装层。
10.根据权利要求9所述的发光式封装结构,其特征为,该结构还包括设于该封装层上的荧光层。
11.根据权利要求9所述的发光式封装结构,其特征为,该封装层中含有荧光粉。
12.根据权利要求1所述的发光式封装结构,其特征为,该发光元件的表面具有荧光层。
13.根据权利要求1所述的发光式封装结构,其特征为,该结构还包括结合该导线架的绝缘层,且令该导线架的部分表面外露于该绝缘层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105205378 | 2016-04-18 | ||
TW105205378U TWM526190U (zh) | 2016-04-18 | 2016-04-18 | 發光式封裝結構 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN205595374U true CN205595374U (zh) | 2016-09-21 |
Family
ID=56932208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201620393819.3U Active CN205595374U (zh) | 2016-04-18 | 2016-05-04 | 发光式封装结构 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20170301842A1 (zh) |
CN (1) | CN205595374U (zh) |
TW (1) | TWM526190U (zh) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWM475024U (zh) * | 2013-12-12 | 2014-03-21 | Lee-Sheng Yen | 可發光式封裝件及其承載結構 |
-
2016
- 2016-04-18 TW TW105205378U patent/TWM526190U/zh unknown
- 2016-05-04 CN CN201620393819.3U patent/CN205595374U/zh active Active
- 2016-07-01 US US15/200,650 patent/US20170301842A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20170301842A1 (en) | 2017-10-19 |
TWM526190U (zh) | 2016-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10801704B2 (en) | Light emitting device | |
CN104900634B (zh) | 封装结构及其所适用的堆栈式封装模块 | |
KR101035335B1 (ko) | 발광다이오드 패키지 | |
CN105895792A (zh) | 发光组件 | |
US8143634B2 (en) | Light emitting diode package with a phosphor substrate | |
US8247833B2 (en) | LED package and manufacturing method thereof | |
EP2381157A2 (en) | Luminaire and light-emitting apparatus with light-emitting device | |
TW201637244A (zh) | 發光二極體封裝結構及其製作方法 | |
US20130175559A1 (en) | Led module | |
US8900895B2 (en) | Method for manufacturing LED package | |
CN107026137A (zh) | 具有磁性装置的电子模块 | |
US20130062656A1 (en) | Thermally enhanced optical package | |
CN103050602B (zh) | 发光装置 | |
CN103190009A (zh) | 发光装置及发光装置用封装阵列 | |
CN102412212A (zh) | 电子/光电组件的散热装置 | |
JP2008288487A (ja) | 表面実装型発光ダイオード | |
CN205595374U (zh) | 发光式封装结构 | |
JP2013089717A (ja) | Ledモジュール | |
KR101628374B1 (ko) | 발광장치 | |
CN104064530B (zh) | 半导体封装件及其制法 | |
CN212676298U (zh) | 具有双面胶体的发光二极管封装结构 | |
KR101049490B1 (ko) | 발광소자 칩, 이를 구비한 발광소자 패키지 및 이를 구비한 백라이트 모듈 | |
CN203932109U (zh) | 可发光式封装件及其承载结构 | |
CN212033002U (zh) | 一种qfn封装导热焊盘及具有其的qfn封装结构 | |
JP2013004834A (ja) | Ledモジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |