TWM475024U - 可發光式封裝件及其承載結構 - Google Patents

可發光式封裝件及其承載結構 Download PDF

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TWM475024U
TWM475024U TW102223444U TW102223444U TWM475024U TW M475024 U TWM475024 U TW M475024U TW 102223444 U TW102223444 U TW 102223444U TW 102223444 U TW102223444 U TW 102223444U TW M475024 U TWM475024 U TW M475024U
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conductive trace
insulating portion
insulating
package
load
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TW102223444U
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Lee-Sheng Yen
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Lee-Sheng Yen
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Priority to TW102223444U priority Critical patent/TWM475024U/zh
Publication of TWM475024U publication Critical patent/TWM475024U/zh
Priority to CN201420189643.0U priority patent/CN203932109U/zh
Priority to US14/256,498 priority patent/US20150171296A1/en
Priority to KR1020140063466A priority patent/KR20150068886A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/644—Heat extraction or cooling elements in intimate contact or integrated with parts of the device other than the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Packaging Frangible Articles (AREA)

Description

可發光式封裝件及其承載結構
本創作係有關一種封裝件，尤指一種可發光式可發光式封裝件及其承載結構。
隨著電子產業的蓬勃發展，電子產品在型態上趨於輕薄短小，在功能上則逐漸邁入高性能、高功能、高速度化的研發方向。其中，發光二極體(Light Emitting Diodc,LED)因具有壽命長、體積小、高耐震性及耗電量低等優點，故廣泛地應用於照光需求之電子產品中，因此，於工業上、各種電子產品、生活家電之應用日趨普及。
第1圖係揭示一種習知LED封裝件1之剖面圖。該LED封裝件1係於一金屬導線架10上形成一具有一開口110之反射杯11，且於該開口110中設置一LED元件12，並以複數焊線120電性連接該金屬導線架10與LED元件12，再於該開口110中形成封裝材13，以包覆該LED元件12與焊線120。
惟，習知LED封裝件1使用該導線架10作為承載該LED元件12之方式，由於該導線架10之厚度L過厚(至少0.2mm)，使該LED封裝件1之整體厚度H(至少0.5mm)極厚，故該LED封裝件1難以符合薄化之需求。
再者，熱阻(thermal resistance)與厚度有關，即厚度愈薄，熱阻愈小，則熱傳效率愈好，如習知公式R=L/kA，其中，R為熱阻，L為熱傳距離(即該導線架10之厚度L)，A為熱傳面積，k為熱傳導係數，故該LED封裝件1因該導線架10之厚度難以薄化，而難以縮小熱阻，致使無法提升熱傳效率。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本創作提供一種承載結構，係包括：導電跡線，係具有相對之第一側與第二側、及相鄰該第一側與第二側之側面；絕緣部，係抵靠該導電跡線，且該導電跡線與該絕緣部係作為封裝基板；以及收納部，係設於該絕緣部上，且具有外露該第一側之開口。
本創作亦提供一種可發光式封裝件，係包括：前述之承載結構；至少一發光體，係設於該開口中並電性連接該導電跡線；以及封裝材，係形成於該開口中以包覆該發光體。
由上可知，本創作之可發光式封裝件及其承載結構，主要藉由該封裝基板之導電跡線作為承載發光體之方式，故相較於習知技術之導線架，本創作之可發光式封裝件能符合薄化之需求，且能提升熱傳效率。
再者，藉由該絕緣部抵靠該導電跡線，以強化該導電跡線承載該發光體的支撐力。
1‧‧‧LED封裝件
10‧‧‧導線架
11‧‧‧反射杯
110,210‧‧‧開口
12‧‧‧LED元件
120,220‧‧‧焊線
13,23‧‧‧封裝材
2,2’,2”,3,3’,3”,4‧‧‧可發光式封裝件
2a,2a’,2a”,3a,3a’,3a”‧‧‧承載結構
20,30‧‧‧導電跡線
20a‧‧‧第一側
20b‧‧‧第二側
20c‧‧‧側面
200‧‧‧凸部
201,202‧‧‧電性接觸墊
21‧‧‧收納部
22,42‧‧‧發光體
25,25’,25”,35,35’,35”‧‧‧絕緣部
251,351‧‧‧第一絕緣層
252,352‧‧‧第二絕緣層
420‧‧‧導電凸塊
L,H,T,t,r‧‧‧厚度
D‧‧‧距離
第1圖係為習知LED封裝件之剖面圖； 第2A至2C圖係為本創作之可發光式封裝件之第一實施例的各種態樣之剖面示意圖；其中，第2A’及2B’圖係分別為第2A及2B圖之另一態樣；第3A至3C圖係為本創作之可發光式封裝件之第二實施例的各種態樣之剖面示意圖；以及第4圖係為本創作之可發光式封裝件之第三實施例的剖面示意圖。
以下藉由特定的具體實施例說明本創作之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本創作之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。
第2A至2C圖係為本創作之可發光式封裝件2,2’,2”之第一實施例的各種態樣之剖面示意圖。所述之可發光式封裝件2,2’,2”係包括：一承載結構2a,2a’,2a”(包含一導電跡線20、 一絕緣部25,25’,25”、一收納部21)、一發光體22以及封裝材23。
所述之導電跡線20係具有相對之第一側20a與第二側20b、及相鄰該第一側20a與第二側20b之側面20c，且該導電跡線20係為凹凸型(如該第二側20b之凸部200)。於本實施例中，該導電跡線20之材質係為一般製作電路板之線路材質，如金屬材(常用為銅)，故其種類繁多，並無特別限制。
如第2A圖所示之承載結構2a，所述之絕緣部25係僅抵靠該導電跡線20之側面20c而外露該導電跡線20之第二側20b之凸部200，且該絕緣部25係為矽膠(silicon)、或如白色、黑色或其它顏色之環氧樹脂(epoxy)之絕緣體，其中，該介電材之材質係為含玻纖或玻璃布(cloth)之環氧樹脂膠(epoxy resin)。該絕緣部25亦可為介電材或防焊材。
所述之收納部21係設於該絕緣部25與該導電跡線20之部分該第一側20a上，且具有外露該第一側20a之一開口210，以令該收納部21作為反射杯。於本實施例中，該收納部21之材質係為矽膠或一般如白膠之環氧樹脂，即未含有玻纖。
所述之發光體22係為發光二極體，其設於該開口210中之第一側20a上並以打線方式(即藉由複數焊線220)電性連接該導電跡線20。
所述之封裝材23係形成於該開口210中以包覆該發光體22及焊線220。
於一態樣中，如第2B圖所示之承載結構2a’，其絕緣部25’係包含第一絕緣層251與第二絕緣層252，且該第一絕緣層251 係抵靠該導電跡線20之側面20c，而該第二絕緣層252係抵靠該導電跡線20之部分該第二側20b。
所述之第一絕緣層251係為介電材，例如含玻纖或玻璃布之環氧樹脂膠，且該第二絕緣層252係為防焊層。
於另一態樣中，如第2C圖所示之承載結構2a”，其絕緣部25”係為防焊材並僅抵靠該導電跡線20之部分該第二側20b，且該收納部21係設於該絕緣部25”與該導電跡線20之部分該第一側20a上並抵靠該導電跡線20之全部該側面20c。
於其它態樣中，如第2A’及2B’圖所示，該收納部21係抵靠該導電跡線20之部分該側面20c，使該絕緣部25,25’僅抵靠該導電跡線20之凸部200之側面20c。
於本創作中，該導電跡線20與該絕緣部25,25’,25”係使用封裝基板製程製作，且使用該導電跡線20作為承載該發光體22之方式，由於該導電跡線20之厚度t極薄(約0.035mm)，使該可發光式封裝件2,2’,2”之整體厚度T(至少0.325mm)降低，故該可發光式封裝件2,2’,2”(或該承載結構2a,2a’,2a”)能符合薄化之需求。
再者，該導電跡線20之厚度可依需求薄化，因而能縮小熱阻，藉以能提升熱傳效率。
又，藉由該絕緣部25,25’,25”抵靠該導電跡線20之側面20c，以強化該導電跡線20承載該發光體22的支撐力。
另外，當該絕緣部25,25’,25”包含防焊材料時，能防止水氣進入該收納部21，以避免該可發光式封裝件2,2’,2”之內部溼氣過重而腐蝕內部線路之問題。
第3A至3C圖係為本創作之可發光式封裝件3,3’,3”之第二實施例的各種態樣之剖面示意圖。本實施例與第一實施例之差異在於導電跡線之態樣，其它結構大致相同，故以下僅詳述相異處。
如第3A至3C圖所示之可發光式封裝件3,3’,3”(或承載結構3a,3a’,3a”)，其導電跡線30係為平板型，且該導電跡線30之厚度r極薄(約10μm)，故該可發光式封裝件3,3’,3”(或承載結構3a,3a’,3a”)能符合薄化之需求。
於本實施例中，如第3A圖所示，該絕緣部35係為感光介電材(photoimagable dielectric material)或防焊材。
於一態樣中，如第3B圖所示，該絕緣部35’係包含第一絕緣層351與第二絕緣層352，且該第一絕緣層351係為非感光性介電材，例如含玻纖或玻璃布之環氧樹脂膠，且該第二絕緣層352係為感光介電材或防焊材並抵靠該導電跡線20之部分該第二側20b與該第一絕緣層351。
於一態樣中，如第3C圖所示，該絕緣部35”係為感光介電材或防焊材，並僅抵靠該導電跡線20之部分該第二側20b，且該收納部21係設於該絕緣部35”與該導電跡線20之部分該第一側20a上而抵靠該導電跡線20之側面20c。
第4圖係為本創作之可發光式封裝件4之第三實施例之剖面示意圖。本實施例與上述兩實施例之差異在於發光體之結合方式，其它結構大致相同，故以下僅詳述相異處。
如第4圖所示，該發光體42藉由複數導電凸塊420覆晶結合並電性連接該導電跡線20。
於本創作中，使用該導電跡線20作為承載該發光體22之方 式，故該導電跡線20之兩電性接觸墊201,202之間的距離D可縮小，因而能將該承載結構2a應用至覆晶封裝之製程。因此，相較於習知導線架無法應用於覆晶封裝之製程，本創作之承載結構2a於應用上較為彈性化。
另外，於上述所有實施例中，該導電跡線20之表面可依需求形成表面處理層，且其材質可如金、銀、錫、有機保焊膜(Organic Solderability Preservative,OSP)等，但並不限於此。
綜上所述，本創作之可發光式封裝件及其承載結構，係藉由使用導電跡線取代習知導線架作為承載發光體之方式，以符合薄化之需求，且能提升熱傳效率。
再者，藉由該絕緣部抵靠該導電跡線，以強化該導電跡線承載該發光體的支撐力。
上述實施例係用以例示性說明本創作之原理及其功效，而非用於限制本創作。任何熟習此項技藝之人士均可在不違背本創作之精神及範疇下，對上述實施例進行修改。因此本創作之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧可發光式封裝件
2a‧‧‧承載結構
20‧‧‧導電跡線
20a‧‧‧第一側
20b‧‧‧第二側
20c‧‧‧側面
21‧‧‧收納部
210‧‧‧開口
22‧‧‧發光體
220‧‧‧焊線
23‧‧‧封裝材
25‧‧‧絕緣部
T,t‧‧‧厚度

Claims (27)

  1. 一種可發光式封裝件，係包括：導電跡線，係具有相對之第一側與第二側、及相鄰該第一側與第二側之側面；絕緣部，係抵靠該導電跡線，且該導電跡線與該絕緣部係作為封裝基板；收納部，係設於該絕緣部上，且具有外露該第一側之開口；至少一發光體，係設於該開口中並電性連接該導電跡線；以及封裝材，係形成於該開口中以包覆該發光體。
  2. 如申請專利範圍第1項所述之可發光式封裝件，其中，該導電跡線係為凹凸型或平板型。
  3. 如申請專利範圍第1項所述之可發光式封裝件，其中，該絕緣部係抵靠該導電跡線之側面。
  4. 如申請專利範圍第3項所述之可發光式封裝件，其中，該絕緣部復抵靠該導電跡線之部分該第二側。
  5. 如申請專利範圍第1項所述之可發光式封裝件，其中，該絕緣部係抵靠該導電跡線之部分該第二側。
  6. 如申請專利範圍第5項所述之可發光式封裝件，其中，該收納部係抵靠該導電跡線之側面。
  7. 如申請專利範圍第1項所述之可發光式封裝件，其中，該絕緣部係包含第一絕緣層與第二絕緣層，且該第一絕緣層係抵靠該導電跡線之側面，而該第二絕緣層係抵靠該導電跡線之部分該第二側。
  8. 如申請專利範圍第7項所述之可發光式封裝件，其中，該第二絕緣層係為防焊層。
  9. 如申請專利範圍第1項所述之可發光式封裝件，其中，該絕緣部係為矽膠、環氧樹脂、介電材或防焊材之絕緣體。
  10. 如申請專利範圍第9項所述之可發光式封裝件，其中，該絕緣部係為感光性介電材之絕緣體。
  11. 如申請專利範圍第1項所述之可發光式封裝件，其中，該收納部與該絕緣部係為不同材質。
  12. 如申請專利範圍第1項所述之可發光式封裝件，其中，該收納部與該絕緣部係為相同材質。
  13. 如申請專利範圍第1項所述之可發光式封裝件，其中，該發光體係以打線方式或覆晶方式電性連接該導電跡線。
  14. 如申請專利範圍第1項所述之可發光式封裝件，其中，該導電跡線之表面形成有表面處理層。
  15. 一種承載結構，係包括：導電跡線，係具有相對之第一側與第二側、及相鄰該第一側與第二側之側面；絕緣部，係抵靠該導電跡線，且該導電跡線與該絕緣部係作為封裝基板；以及收納部，係設於該絕緣部上，且具有外露該第一側之開口。
  16. 如申請專利範圍第15項所述之承載結構，其中，該導電跡線係為凹凸型或平板型。
  17. 如申請專利範圍第15項所述之承載結構，其中，該絕緣部係抵靠該導電跡線之側面。
  18. 如申請專利範圍第17項所述之承載結構，其中，該絕緣部復抵靠該導電跡線之部分該第二側。
  19. 如申請專利範圍第15項所述之承載結構，其中，該絕緣部係抵靠該導電跡線之部分該第二側。
  20. 如申請專利範圍第19項所述之承載結構，其中，該收納部係抵靠該導電跡線之側面。
  21. 如申請專利範圍第15項所述之承載結構，其中，該絕緣部係包含第一絕緣層與第二絕緣層，且該第一絕緣層係抵靠該導電跡線之側面，而該第二絕緣層係抵靠該導電跡線之部分該第二側。
  22. 如申請專利範圍第21項所述之承載結構，其中，該第二絕緣層係為防焊層。
  23. 如申請專利範圍第15項所述之承載結構，其中，該絕緣部係為矽膠、環氧樹脂、介電材或防焊材之絕緣體。
  24. 如申請專利範圍第23項所述之承載結構，其中，該絕緣部係為感光性介電材之絕緣體。
  25. 如申請專利範圍第15項所述之承載結構，其中，該收納部與該絕緣部係為不同材質。
  26. 如申請專利範圍第15項所述之承載結構，其中，該收納部與該絕緣部係為相同材質。
  27. 如申請專利範圍第15項所述之承載結構，其中，該導電跡線之表面形成有表面處理層。
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