CN205427042U

CN205427042U - CPLD frequency measurement module

Info

Publication number: CN205427042U
Application number: CN201620208276.3U
Authority: CN
Inventors: 刘梅华
Original assignee: Chongqing College of Electronic Engineering
Current assignee: Chongqing College of Electronic Engineering
Priority date: 2016-03-09
Filing date: 2016-03-09
Publication date: 2016-08-03
Anticipated expiration: 2026-03-09

Abstract

The utility model discloses a CPLD frequency measurement module, including the CPLD controller, first counter's counting clock input is connected with the clock input of D trigger end, and first counter's counting clock input is being surveyed signal input part, first counter's clear terminal starts signal input part for the frequency measurement, and first counter's clear terminal is connected with the clear terminal of D trigger, the data input end of D trigger is connected with positive VCC, the first input end of AND gate is connected with frequency division unit's output, and the second input of AND gate is connected with the output of D trigger, the input of first counter's carry output end NAND gate is connected, the output of AND gate with the counting clock input of second counter is connected, the clear terminal and the frequency measurement of second counter start signal input part and are connected. The utility model has the advantages of measurement accuracy is high, hardware circuit is simple and the operational reliability is high.

Description

A kind of CPLD frequency measurement module

Technical field

This utility model relates to a kind of frequency measurement module, and a kind of CPLD of employing hardware circuit carries out the frequency measurement module of frequency measurement, belongs to signal measurement technique field.

Background technology

Frequency measurement is extremely important for the electrical measurement of non-electrical quantity, and it can be measured by the physical quantity being generally convertible into electric impulse signal by the method measuring frequency.

Frequency measurement principle is generally divided into two kinds: Measuring Frequency Method and measuring period method.Measuring Frequency Method is exactly in the gate time determined in Tg, and period of change number (or pulse number) Nx of record measured signal, then the frequency of measured signal is: fx=Nx/Tg.Measuring period method needs frequency fs of standard signal, and in cycle T x of measured signal, the periodicity Ns of record standard frequency, then the frequency of measured signal is: fx=fs/Ns.The count value of both approaches can produce ± 1 word error, and measuring accuracy is relevant with the numerical value of record in enumerator.

Additionally, currently also there is another frequency measuring method: multicycle method.Multicycle method is closer to measuring period method principle, and difference is its multiple cycles as gate time using measured signal, counts standard signal, compare measuring period method, multicycle method can collect to obtain more measured signal sample, and this advantageously reduces error, improves certainty of measurement.But the hardware that realizes of multicycle method coordinates the measurement system of each Peripheral digital integrated circuit often with single-chip microcomputer for core in prior art, and it is typically with the enumerator within single-chip microcomputer and standard signal is carried out count measurement, this cause such scheme of the prior art exist following defect (1) due to single-chip microcomputer internal counter counter capacity less, and counter capacity can not be revised, this is a kind of restriction for improving measurement motility and precision；(2) could realize measuring owing to other digital integrated electronic circuits of needs (mainly counter chip, various gate circuit and trigger chip) match, which results in complex circuit designs；(3) low due to single-chip microcomputer functional reliability, the reset of moment will also result in serious consequence in some cases, and therefore systematic survey stability is the highest, and the raising of certainty of measurement is limited.

Utility model content

For deficiencies of the prior art, the purpose of this utility model is: how to provide the CPLD frequency measurement module that a kind of certainty of measurement is high, hardware circuit is simple and functional reliability is high.

To achieve these goals, this utility model have employed following technical scheme.

A kind of CPLD frequency measurement module, it is characterised in that: include CPLD controller, described CPLD controller include d type flip flop, the first enumerator, the second enumerator and with door；

Described have three inputs with door；Described first enumerator has counting clock input, clear terminal, terminal count output and carry output, the counting clock input of described first enumerator is that rising edge triggers, the clear terminal of described first enumerator is that high level is effective, described first enumerator is binary addition enumerator, the maximum count value of the first enumerator is N, maximum count value N of described first enumerator is natural number, N ＞ 2；Described second enumerator has counting clock input, clear terminal and terminal count output, and the clear terminal of described second enumerator is that high level is effective；Described d type flip flop has data input pin, clear terminal, input end of clock and outfan, and described d type flip flop input end of clock is that rising edge triggers, and the clear terminal of described d type flip flop is that high level is effective；

The counting clock input of described first enumerator is connected with the input end of clock of described d type flip flop, and the counting clock input of described first enumerator is measured signal input；

The clear terminal of described first enumerator is frequency measurement enabling signal input, and the clear terminal of described first enumerator is connected with the clear terminal of described d type flip flop；The data input pin of described d type flip flop is connected with positive source VCC；

Described being connected with the outfan of frequency unit with the first input end of door, the input of described frequency unit is connected with CPLD controller internal work clock signal terminal；Described it is connected with the outfan of described d type flip flop with the second input of door；The input of the carry output NAND gate of described first enumerator is connected, and the outfan of described not gate is connected with described the 3rd input with door；

Described and the outfan of door with described second enumerator counting clock input is connected；

The clear terminal of described second enumerator is connected with frequency measurement enabling signal input.

Further, described frequency measurement enabling signal input is connected with activate switch.

Compared to existing technology, this utility model has the advantage that

In this utility model, the count measurement of standard signal is completed by (1) by the second enumerator, to the measurement in multiple measured signal cycles to determine that " gate time " completes due to the first enumerator, owing to CPLD internal digital logic resource is the most powerful, realize above-mentioned two enumerator the most very easy, and can be according to measuring it needs to be determined that counter capacity, therefore this utility model has certainty of measurement and measures the advantage that motility is high；(2) this utility model need not the cooperation of Peripheral digital chip and can realize measuring, and therefore has the simple advantage of circuit structure；(3) count internal is measured and is utilized its abundant internal digital logic resource to realize by CPLD, owing to being that totally digital circuit hardware realizes, uses number of chips less, and therefore operational reliability is high, and working condition is stable.(in hardware designs; single-chip microcomputer is that the system of core would generally use a large amount of digit chip to coordinate minimum system to realize various function; it is low often to there is certainty of measurement in this hardware architecture; poor stability; and use a large amount of digit chip to realize the function that some single-chip microcomputer is not easily accomplished; therefore the area of pcb board and wiring difficulty all can increase, and functional reliability and design efficiency all can be restricted.)

Accompanying drawing explanation

Fig. 1 is circuit structure diagram of the present utility model；

Detailed description of the invention

With detailed description of the invention, this utility model is described in further detail below in conjunction with the accompanying drawings.

As it is shown in figure 1, this frequency measurement module is only by a piece of acp chip, that is to say that CPLD controller is constituted, (certainly must also possess the peripheral circuits such as clock circuit, reset circuit and power circuit needed for the work of CPLD controller).

CPLD controller be internally provided with d type flip flop, the first enumerator, the second enumerator and with door；

(1) with Men Weiyi three input and door, this unit can directly invoke predefined gate cell and realize；

(2) first enumerators have counting clock input, clear terminal, terminal count output and carry output, the counting clock input of the first enumerator is that rising edge triggers, the clear terminal of the first enumerator is that high level is effective, first enumerator is binary addition enumerator, its maximum count value is that N (can modify as required by this maximum count value, concrete can to use principle diagram design mode time call the enumerator of different counter capacity, can also be when using hardware description language to realize, relevant parameter in amendment code, synthesis tool will obtain the counter circuit structure of corresponding counts capacity).

(3) second enumerators have counting clock input, clear terminal and terminal count output, and the clear terminal of the second enumerator is that high level is effective；

Above-mentioned two counter unit can realize to utilize principle diagram design mode to call counter module.By hardware description language programming realization, and can also be created as schematic symbol for calling, no matter use which kind of mode, the instrument that the most all can be integrated into comprehensively is solidificated in CPLD chip for netlist circuit structure.

(4) d type flip flop has data input pin, clear terminal, input end of clock and outfan, and described d type flip flop input end of clock is that rising edge triggers, and the clear terminal of described d type flip flop is that high level is effective；This unit can be realized by calling corresponding schematic diagram unit.

(5) frequency unit, it is possible to use principle diagram design mode is called allocator module and realized

Circuit connecting relation between unit is as follows:

The counting clock input of the first enumerator is connected with the input end of clock of described d type flip flop, and the counting clock input of the first enumerator is measured signal input；The clear terminal of the first enumerator is frequency measurement enabling signal input, and the clear terminal of the first enumerator is connected with the clear terminal of described d type flip flop；Being connected with the outfan of frequency unit with the first input end of door, the input of frequency unit is connected with CPLD controller internal work clock signal terminal；It is connected with the outfan of described d type flip flop with the second input of door；The input of the carry output NAND gate of the first enumerator is connected, and the outfan of not gate is connected with described the 3rd input with door；It is connected with the counting clock input of the outfan of door with described second enumerator；The clear terminal of the second enumerator is connected with frequency measurement enabling signal input.

In order to input frequency measurement enabling signal, frequency measurement enabling signal input is connected with activate switch, and activate switch is toggle switch, can export low and high level.

Utility model works principle is as follows:

(1) when needing frequency measurement, stir activate switch to output high level position, owing to clear terminal, the clear terminal of the second enumerator of the first enumerator are all connected with activate switch with the clear terminal of d type flip flop, therefore above three device cell resets simultaneously, and this is ready for measuring.

(2) stirring activate switch to output low level position, the reset signal of above three device all disappears, and device can carry out other actions.

(2) when first rising edge of measured signal arrives, first enumerator starts counting up, d type flip flop also begins to gather the data of its data input pin simultaneously, owing to the data input pin of d type flip flop is connected with positive source VCC, therefore d type flip flop outfan output high level, and the now carry output output low level of the first enumerator, this low level is high level after being negated by not gate, that is to say that now three inputs are high level with the second input and the 3rd input of door, therefore the output signal (standard signal) of frequency unit can be by the second counting unit counts.

(3) when the n-th rising edge of measured signal trigger the first counting unit counts reach maximum count value N time, the carry output output high level of the first counting unit, this high level just make after being negated by not gate standard signal cannot by with door, therefore the terminal count output signal of the second counting unit stops change, measurement terminates, frequency fs of bidding calibration signal, in N-1 cycle (N-1) Tx of measured signal, the periodicity Ns of record standard signal, then the frequency of measured signal is determined by below equation: (N-1)/fx=Ns/fs.Although it should be noted that the first counting unit have recorded N number of rising edge of measured signal in above formula, but the actual measurement time (namely gate time of reality) only having N-1 the cycle that measured signal is complete.The amendment of N value has illustrated, the most no longer discusses.

The value of the only Ns of certain second counting unit output, the frequency values conversion of measured signal also to be completed by other intelligent parts, such as can call 51 cores (being equivalent to the CPU of singlechip chip) in the way of calling to use macroelement and complete above-mentioned conversion, it is also possible to directly utilize singlechip chip and complete.

This utility model provides a kind of frequency measurement module based on multicycle method in a word, can provide the important parameter for obtaining measured signal frequency values accurately: the periodicity Ns of record standard signal in N-1 cycle (N-1) Tx of measured signal.

Finally illustrate is, above example is only in order to illustrate the technical solution of the utility model and unrestricted, although this utility model being described in detail with reference to preferred embodiment, it will be understood by those within the art that, the technical solution of the utility model can be modified or equivalent, without deviating from objective and the scope of technical solutions of the utility model, it all should be contained in the middle of right of the present utility model.

Claims

1. a CPLD frequency measurement module, it is characterised in that: include CPLD controller, described CPLD controller include d type flip flop, the first enumerator, the second enumerator and with door；

A kind of CPLD frequency measurement module the most according to claim 1, it is characterised in that described frequency measurement enabling signal input is connected with activate switch.