CN205356305U - Serial data clock digit phase locking device - Google Patents
Serial data clock digit phase locking device Download PDFInfo
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- CN205356305U CN205356305U CN201521040518.4U CN201521040518U CN205356305U CN 205356305 U CN205356305 U CN 205356305U CN 201521040518 U CN201521040518 U CN 201521040518U CN 205356305 U CN205356305 U CN 205356305U
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Abstract
The utility model discloses a serial data clock digit phase locking device, the LED screen remote signal transmission system comprises a transmitting end and a receiving end, the transmitting terminal includes the the first clock generator, digital source and scrambler module, the receiving terminal includes the descrambling code module, the 2nd clock generator and clock recovery module, the scrambler module, descrambling code module and clock recovery module all set up in CPLD or FPGA, the the first clock generator produces and sends clock signal, digital source reception and transmition clock signal produces digital baseband signal, the scrambler module is received digital baseband signal and is obtained sending respectively behind the serial code stream signal descrambling code module and clock recovery module to its scrambler, the 2nd clock generator produces and is greater than the receipt clock signal who sends the clock signal frequency, the descrambling code module uses the recovered clock signal to carry out the descrambling code to the serial code stream signal. Implement the utility model discloses a serial data clock digit phase locking device has following beneficial effect: the destabilizing factor that the cost is lower, can reduce the system.
Description
Technical field
This utility model relates to clock field of synchronization, particularly to a kind of serial data clock digital phase lock device.
Background technology
In the communications in order to receive the data that opposite end transmission comes accurately, it is necessary to synchronize, i.e. the tranmitting data register same frequency homophase receiving clock and opposite end of local terminal.Realizing synchronization has two ways, one to be that opposite end tranmitting data register comes, and another kind is in local terminal recovered clock.First kind of way needs to increase by a road transmission line, and for long range propagation, cost is too big, and can, because the dither difference of transmission line, cause being unable to properly receive data when high speed.The method of local terminal recovered clock is currently mainly adopted to receive data, namely a pair bunchiness/deserializer (SerDes) is increased in sending and receiving end, it is used for doing clock recovery, general bunchiness/deserializer cost is higher, suitable for bigger systematic comparison, but for mini system, cost pressure is relatively larger, and when increasing hardware, also add trouble point accordingly, bring unstable factor to system.
Utility model content
The technical problems to be solved in the utility model is in that, for above-mentioned relatively costly, the defect that system exists unstable factor of prior art, it is provided that a kind of less costly, the serial data clock digital phase lock device of the unstable factor of system can be reduced.
This utility model solves its technical problem and be the technical scheme is that a kind of serial data clock digital phase lock device of structure, including transmitting terminal and receiving terminal, described transmitting terminal includes the first clock generator, digital source and scrambler module, described receiving terminal includes descrambling code module, second clock generator and clock recovery module, described scrambler module, descrambling code module and clock recovery module are arranged in CPLD or FPGA, described first clock generator produces tranmitting data register signal, the input of described digital source is connected with an outfan of described first clock generator, receive the described tranmitting data register signal of described first clock generator output and produce digital baseband signal, one input of described scrambler module is connected with the outfan of described digital source, receive the described digital baseband signal of described digital source output and described digital baseband signal is carried out scrambler obtain serial bit stream signal, another input of described scrambler module is connected with another outfan of described first clock generator, receive the described tranmitting data register signal of described first clock generator output, and by described tranmitting data register signal, described serial bit stream signal is separately sent to an input of described descrambling code module and an input of clock recovery module, described second clock generator produces to receive clock signal, and described reception clock signal is exported another input of described clock recovery module, another input of described descrambling code module receives the recovered clock signal of described clock recovery module output, by described recovered clock signal described serial bit stream signal carried out descrambling code and described digital baseband signal that output restores, the frequency of described reception clock signal is more than the frequency of described tranmitting data register signal.
In serial data clock digital phase lock device described in the utility model, described scrambler module includes the first d type flip flop, second d type flip flop, 3d flip-flop, four d flip-flop, 5th d type flip flop, 6th d type flip flop, 7th d type flip flop, first NOR gate circuit and the second NOR gate circuit, one input of described first NOR gate circuit is connected with the outfan of described digital source, another input of described first NOR gate circuit is connected with the outfan of described second d type flip flop, the outfan of described first NOR gate circuit is connected with the input of described 3d flip-flop, one input of described second NOR gate circuit is connected with an outfan of described 5th d type flip flop, another input of described second NOR gate circuit is connected with the outfan of described 7th d type flip flop, the outfan of described second NOR gate circuit is connected with the input of described first d type flip flop, the outfan of described first d type flip flop is connected with the input of described second d type flip flop, the outfan of described 3d flip-flop is connected with an input of described 5th d type flip flop by described four d flip-flop, another outfan of described 5th d type flip flop is connected with the input of described 7th d type flip flop by described 6th d type flip flop, described four d flip-flop is also connected with described descrambling code module and clock recovery module respectively.
In serial data clock digital phase lock device described in the utility model, described descrambling code module includes the 8th d type flip flop, 9th d type flip flop, tenth d type flip flop, 11st d type flip flop, tenth 2-D trigger, tenth 3d flip-flop, 3rd NOR gate circuit and the 4th NOR gate circuit, one input of described 3rd NOR gate circuit is connected with an outfan of described 8th d type flip flop, another input of described 3rd NOR gate circuit is connected with the outfan of described tenth 3d flip-flop, the described digital baseband signal of the outfan output reduction of described 3rd NOR gate circuit, one input of described 4th NOR gate circuit is connected with an outfan of described tenth d type flip flop, another input of described 4th NOR gate circuit is connected with the outfan of described tenth 2-D trigger, the outfan of described 4th NOR gate circuit is connected with the input of described tenth 3d flip-flop, another outfan of described 8th d type flip flop is connected with the input of described tenth d type flip flop by described 9th d type flip flop, the input of described 8th d type flip flop is connected with described scrambler module, another outfan of described tenth d type flip flop is connected with the input of described tenth 2-D trigger by described 11st d type flip flop.
In serial data clock digital phase lock device described in the utility model, in described clock recovery module, it is provided with enumerator.
In serial data clock digital phase lock device described in the utility model, described scrambler module, descrambling code module and clock recovery module are separately positioned in different CPLD or FPGA.
In serial data clock digital phase lock device described in the utility model, the frequency of described reception clock signal is equal to four times of the frequency of described tranmitting data register signal.
Implement serial data clock digital phase lock device of the present utility model, have the advantages that owing to transmitting terminal includes the first clock generator, digital source and scrambler module, receiving terminal includes descrambling code module, second clock generator and clock recovery module, scrambler module, descrambling code module and clock recovery module are arranged in CPLD or FPGA, thus can realize serial data clock at CPLD/FPGA to recover, CPLD/FPGA all can be used to do Digital Signal Processing due to general communication system, so cost will not additionally be increased, so it is less costly, simultaneously, owing to not needing bunchiness/deserializer, thus can reduce the unstable factor of system.
Accompanying drawing explanation
In order to be illustrated more clearly that this utility model embodiment or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structured flowchart in one embodiment of this utility model serial data clock digital phase lock device；
Fig. 2 is the structural representation of scrambler module in described embodiment；
Fig. 3 is the structural representation of descrambling code module in described embodiment.
Detailed description of the invention
Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is clearly and completely described, it is clear that described embodiment is only a part of embodiment of this utility model, rather than whole embodiments.Based on the embodiment in this utility model, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of this utility model protection.
In this utility model serial data clock digital phase lock device embodiment, the structural representation of its serial data clock digital phase lock device is as shown in Figure 1.In Fig. 1, this serial data clock digital phase lock device includes transmitting terminal 1 and receiving terminal 2, transmitting terminal 1 includes the first clock generator 11, digital source 12 and scrambler module 13, receiving terminal 2 includes descrambling code module 21, second clock generator 22 and clock recovery module 23, wherein, scrambler module 13, descrambling code module 21 and clock recovery module 23 are arranged in CPLD or FPGA, first clock generator 11 produces tranmitting data register signal, the input of digital source 12 and an outfan of the first clock generator 11 connect, digital source 12 receives the tranmitting data register signal of the first clock generator 11 output and produces digital baseband signal, one input of scrambler module 13 is connected with the outfan of digital source 12, scrambler module 13 receives the digital baseband signal of digital source 12 output and this digital baseband signal is carried out scrambler obtains serial bit stream signal, thus can long by even 0 and long by even 1 in limiting circuitry code, it is easy to from line signal and extracts clock signal, make the signal spectrum after scrambling more can be suitable for base band transmission, may also operate as the effect of secrecy.It is noted that in the present embodiment, scrambler module 13, descrambling code module 21 and clock recovery module 23 are separately positioned in different CPLD or FPGA.Certainly, under the certain situation of the present embodiment, scrambler module 13, descrambling code module 21 and clock recovery module 23 can also be arranged in same CPLD or FPGA, in practical application, can select accordingly as the case may be.
In the present embodiment, another input of scrambler module 13 and another outfan of the first clock generator 11 connect, scrambler module 13 receives the tranmitting data register signal of the first clock generator 11 output, and by tranmitting data register signal, serial bit stream signal is separately sent to an input of descrambling code module 21 and an input of clock recovery module 23, namely in the corresponding time, serial bit stream signal is separately sent to an input of descrambling code module 21 and an input of clock recovery module 23 according to the situation of change of tranmitting data register signal.Second clock generator 22 generation reception clock signal, and reception clock signal is exported another input of clock recovery module 23, the frequency of this reception clock signal is more than the frequency of tranmitting data register signal.It is noted that in the present embodiment, the frequency of reception clock signal is equal to four times of the frequency of tranmitting data register signal, certainly, under the certain situation of the present embodiment, the frequency of reception clock signal can also be other multiples of the frequency of tranmitting data register signal.Another input of descrambling code module 21 receives the recovered clock signal of clock recovery module 23 output, by recovered clock signal, serial bit stream signal is carried out descrambling code, restores digital baseband signal the digital baseband signal output that will restore.Owing to scrambler module 13, descrambling code module 21 and clock recovery module 23 are arranged in CPLD or FPGA, thus can realize serial data clock at CPLD/FPGA to recover, CPLD/FPGA all can be used to do Digital Signal Processing due to general communication system, so cost will not additionally be increased, so it is less costly, simultaneously as do not need bunchiness/deserializer, the unstable factor of system thus can be reduced.
Fig. 2 is the structural representation of scrambler module in the present embodiment, in Fig. 2, scrambler module 13 includes the first d type flip flop 131, second d type flip flop 132, 3d flip-flop 133, four d flip-flop 134, 5th d type flip flop 135, 6th d type flip flop 136, 7th d type flip flop 137, first NOR gate circuit 138 and the second NOR gate circuit 139, wherein, one input of the first NOR gate circuit 138 is connected with the outfan of digital source 12, another input of first NOR gate circuit 138 and the outfan of the second d type flip flop 132 connect, the outfan of the first NOR gate circuit 138 and the input of 3d flip-flop 133 connect, also it is equivalent to the value after by digital baseband signal and the second d type flip flop 132 XOR and exports to 3d flip-flop 133, one input of the second NOR gate circuit 139 and an outfan of the 5th d type flip flop 135 connect, another input of second NOR gate circuit 139 and the outfan of the 7th d type flip flop 137 connect, the outfan of the second NOR gate circuit 139 and the input of the first d type flip flop 131 connect, also the value after by the 5th d type flip flop 135 and the 7th d type flip flop 136 XOR it is equivalent to the first d type flip flop 131, the outfan of the first d type flip flop 131 and the input of the second d type flip flop 132 connect, the outfan of 3d flip-flop 133 is connected with an input of the 5th d type flip flop 135 by four d flip-flop 134, another outfan of 5th d type flip flop 135 is connected with the input of the 7th d type flip flop 137 by the 6th d type flip flop 136, four d flip-flop 134 is also connected with descrambling code module 21 and clock recovery module 23 respectively.Namely, four d flip-flop 134 exports serial bit stream signal, when the rising edge of clock signal arrives when sending, trigger first d type flip flop the 131, second d type flip flop 132,3d flip-flop 133, four d flip-flop the 134, the 5th d type flip flop the 135, the 6th d type flip flop 136 and the 7th d type flip flop 137 to shift, serial bit stream signal is made to move, it is achieved the scrambling of digital baseband signal.
Fig. 3 is the structural representation of descrambling code module in the present embodiment, in Fig. 3, this descrambling code module 21 includes the 8th d type flip flop 211, 9th d type flip flop 212, tenth d type flip flop 213, 11st d type flip flop 214, tenth 2-D trigger 215, tenth 3d flip-flop 216, 3rd NOR gate circuit 217 and the 4th NOR gate circuit 218, wherein, one input of the 3rd NOR gate circuit 217 and an outfan of the 8th d type flip flop 211 connect, another input of 3rd NOR gate circuit 217 and the outfan of the tenth 3d flip-flop 216 connect, the digital baseband signal of the outfan output reduction of the 3rd NOR gate circuit 217, also the value after by serial bit stream signal and the tenth 3d flip-flop 216 XOR it is equivalent to digital baseband signal, one input of the 4th NOR gate circuit 218 and an outfan of the tenth d type flip flop 213 connect, another input of 4th NOR gate circuit 218 and the outfan of the tenth 2-D trigger 215 connect, the outfan of the 4th NOR gate circuit 218 and the input of the tenth 3d flip-flop 216 connect, be equivalent to the value after by the tenth d type flip flop 213 and the tenth 2-D trigger 215 XOR to the tenth 3d flip-flop 216.Another outfan of 8th d type flip flop 211 is connected with the input of the tenth d type flip flop 213 by the 9th d type flip flop 212, the input of the 8th d type flip flop 211 is connected with scrambler module 13, and another outfan of the tenth d type flip flop 213 is connected with the input of the tenth 2-D trigger 215 by the 11st d type flip flop 214.When the rising edge of clock signal arrives when 330 receiving, trigger the 8th d type flip flop the 211, the 9th d type flip flop the 212, the tenth d type flip flop the 213, the 11st d type flip flop the 214, the tenth 2-D trigger the 215, the tenth 3d flip-flop 216 to shift, serial bit stream signal is made to move, realize the descrambling of serial bit stream signal, recover digital baseband signal.
In the present embodiment, in clock recovery module 23, it is provided with enumerator (not shown), when the rising edge of serial bit stream signal comes, makes counter O reset, when the rising edge of clock signal comes when sending, make enumerator cumulative 1.Finally produce recovered clock signal, when enumerator=00 or 11, recovered clock signal is low level, when enumerator=01 or 10, recovered clock signal is high level, thus produce the clock signal (i.e. recovered clock signal) of tranmitting data register signal four frequency dividing, and the rising edge of this recovered clock signal can with the code element justified of incoming serial signal bit stream, it is possible to correct each data reading serial bit stream signal.
In a word, in the present embodiment, it is arranged in CPLD or FPGA by scrambler module 13, descrambling code module 21 and clock recovery module 23, thus can realize serial data clock at CPLD/FPGA to recover, CPLD/FPGA all can be used due to general communication system to do Digital Signal Processing, so cost will not additionally be increased, so it is less costly, simultaneously as do not need bunchiness/deserializer, the unstable factor of system thus can be reduced.This utility model utilizes existing resource to reduce cost, it is achieved simple.
The foregoing is only preferred embodiment of the present utility model; not in order to limit this utility model; all within spirit of the present utility model and principle, any amendment of making, equivalent replacement, improvement etc., should be included within protection domain of the present utility model.
Claims (6)
1. a serial data clock digital phase lock device, it is characterized in that, including transmitting terminal and receiving terminal, described transmitting terminal includes the first clock generator, digital source and scrambler module, described receiving terminal includes descrambling code module, second clock generator and clock recovery module, described scrambler module, descrambling code module and clock recovery module are arranged in CPLD or FPGA, described first clock generator produces tranmitting data register signal, the input of described digital source is connected with an outfan of described first clock generator, receive the described tranmitting data register signal of described first clock generator output and produce digital baseband signal, one input of described scrambler module is connected with the outfan of described digital source, receive the described digital baseband signal of described digital source output and described digital baseband signal is carried out scrambler obtain serial bit stream signal, another input of described scrambler module is connected with another outfan of described first clock generator, receive the described tranmitting data register signal of described first clock generator output, and by described tranmitting data register signal, described serial bit stream signal is separately sent to an input of described descrambling code module and an input of clock recovery module, described second clock generator produces to receive clock signal, and described reception clock signal is exported another input of described clock recovery module, another input of described descrambling code module receives the recovered clock signal of described clock recovery module output, by described recovered clock signal described serial bit stream signal carried out descrambling code and described digital baseband signal that output restores, the frequency of described reception clock signal is more than the frequency of described tranmitting data register signal.
2. serial data clock digital phase lock device according to claim 1, it is characterized in that, described scrambler module includes the first d type flip flop, second d type flip flop, 3d flip-flop, four d flip-flop, 5th d type flip flop, 6th d type flip flop, 7th d type flip flop, first NOR gate circuit and the second NOR gate circuit, one input of described first NOR gate circuit is connected with the outfan of described digital source, another input of described first NOR gate circuit is connected with the outfan of described second d type flip flop, the outfan of described first NOR gate circuit is connected with the input of described 3d flip-flop, one input of described second NOR gate circuit is connected with an outfan of described 5th d type flip flop, another input of described second NOR gate circuit is connected with the outfan of described 7th d type flip flop, the outfan of described second NOR gate circuit is connected with the input of described first d type flip flop, the outfan of described first d type flip flop is connected with the input of described second d type flip flop, the outfan of described 3d flip-flop is connected with an input of described 5th d type flip flop by described four d flip-flop, another outfan of described 5th d type flip flop is connected with the input of described 7th d type flip flop by described 6th d type flip flop, described four d flip-flop is also connected with described descrambling code module and clock recovery module respectively.
3. serial data clock digital phase lock device according to claim 1 and 2, it is characterized in that, described descrambling code module includes the 8th d type flip flop, 9th d type flip flop, tenth d type flip flop, 11st d type flip flop, tenth 2-D trigger, tenth 3d flip-flop, 3rd NOR gate circuit and the 4th NOR gate circuit, one input of described 3rd NOR gate circuit is connected with an outfan of described 8th d type flip flop, another input of described 3rd NOR gate circuit is connected with the outfan of described tenth 3d flip-flop, the described digital baseband signal of the outfan output reduction of described 3rd NOR gate circuit, one input of described 4th NOR gate circuit is connected with an outfan of described tenth d type flip flop, another input of described 4th NOR gate circuit is connected with the outfan of described tenth 2-D trigger, the outfan of described 4th NOR gate circuit is connected with the input of described tenth 3d flip-flop, another outfan of described 8th d type flip flop is connected with the input of described tenth d type flip flop by described 9th d type flip flop, the input of described 8th d type flip flop is connected with described scrambler module, another outfan of described tenth d type flip flop is connected with the input of described tenth 2-D trigger by described 11st d type flip flop.
4. serial data clock digital phase lock device according to claim 3, it is characterised in that be provided with enumerator in described clock recovery module.
5. serial data clock digital phase lock device according to claim 1, it is characterised in that described scrambler module, descrambling code module and clock recovery module are separately positioned in different CPLD or FPGA.
6. serial data clock digital phase lock device according to claim 1, it is characterised in that the frequency of described reception clock signal is equal to four times of the frequency of described tranmitting data register signal.
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| CN201521040518.4U CN205356305U (en) | 2015-12-14 | 2015-12-14 | Serial data clock digit phase locking device |
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| CN201521040518.4U CN205356305U (en) | 2015-12-14 | 2015-12-14 | Serial data clock digit phase locking device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108337064A (en) * | 2017-01-19 | 2018-07-27 | 广州航天海特系统工程有限公司 | Digital multiplexing solution multiple devices based on CPLD/FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108337064A (en) * | 2017-01-19 | 2018-07-27 | 广州航天海特系统工程有限公司 | Digital multiplexing solution multiple devices based on CPLD/FPGA |
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