CN208227041U - Full duplex clocked data transfer system - Google Patents
Full duplex clocked data transfer system Download PDFInfo
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- CN208227041U CN208227041U CN201820648160.0U CN201820648160U CN208227041U CN 208227041 U CN208227041 U CN 208227041U CN 201820648160 U CN201820648160 U CN 201820648160U CN 208227041 U CN208227041 U CN 208227041U
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- 238000012546 transfer Methods 0.000 title claims abstract description 17
- 238000012545 processing Methods 0.000 claims abstract description 28
- 238000011084 recovery Methods 0.000 claims abstract description 24
- 238000005070 sampling Methods 0.000 claims abstract description 22
- 230000003321 amplification Effects 0.000 claims abstract description 9
- 238000000605 extraction Methods 0.000 claims abstract description 9
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 9
- 230000005540 biological transmission Effects 0.000 claims description 17
- 238000012549 training Methods 0.000 claims description 13
- 230000003993 interaction Effects 0.000 claims description 5
- 238000005457 optimization Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 5
- 230000002452 interceptive effect Effects 0.000 description 4
- 241001269238 Data Species 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 238000004891 communication Methods 0.000 description 1
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Abstract
The utility model provides a kind of full duplex clocked data transfer system.The system comprises duplexing source and duplexing receiving end, the duplex source and duplexing receiving end include: to send drive module and receiving processing module, for initializing to the data to be sent after coding；Clock Extraction amplification module, connect with receiving processing module, for carrying out clock recovery；Data tracking sampling module is received, is connect with receiving processing module, is used to analyze the received data carry out tracking sampling；Phase-locked loop module is connect with Clock Extraction amplification module, for carrying out locking and frequency multiplication to the clock of recovery；Clock and data recovery module is connect with reception data tracking sampling module and phase-locked loop module, for restoring to the clock from phase-locked loop module and from the data for receiving data tracking sampling module；It receives data decoding and sends data coding module, connect with clock and data recovery module, for carrying out encoding and decoding to the data from clock and data recovery module.
Description
Technical field
The utility model relates to IC design technical field more particularly to a kind of full duplex clocked data transfer systems
System.
Background technique
From the structure of the common cable of Ethernet (cat5/cat6), 4 pairs of high-speed datas can be transmitted, totally 8 line sequences.
In the agreement of high resolution audio and video, including 3 pairs of A/V link differential datas and 1 pair of differential clocks, while HDbase-T agreement is also
Define I2C.For common cable, exchange technology is extremely important, specifically includes that display data channel (Display
Data Channel, DDC), UART Universal Asynchronous Receiver Transmitter (Universal Asynchrpnous Receiver Transmitter,
UART), audio return channel (Audio Return Channel, ARC), infrared (Infra-Red, IR) technology, bi-directional data
Bus (Inter-Integrated Circuit, I2C), the number such as universal serial bus (Universal Serial Bus, USB)
According to interaction.
Current a solution is in printed circuit board (Printed Circuit Board, PCB) version grade one
It is coupled to differential clocks and a pair of of differential data with inductance, sends, pass through in SRCP (Source Port, source)
It crosses after cable, reuses inductance in SNKP (Sink Port, receiving end) and isolate clock signal and data-signal.It isolates
Clock signal needs to reuse signal amplifier by the passive filter of a band logical due to the interference by data-signal
Overcome the decaying on channel, can just be sent to the clock pins of chip.Institute can be transmitted as required by saving a pair of of the signal wire come out
The interactive signal needed.
The realization of PCB editions grades has some disadvantages: first is that discrete device is more, and the passive filter of high target, signal is needed to put
Big device etc.；Second is that device is more on plate, increased costs；Third is that the realization difficulty of the signal integrity between more discrete devices increases.This
Outside, can not meet the needs of auxiliary datas such as UART, ARC, IR, DDC communication simultaneously.
Utility model content
Full duplex clocked data transfer system provided by the utility model can be realized in transmission of video cable in chip
The two-way interactive of interior integrated clock and auxiliary data, guarantee receive clock performance while complete Various Complex signal with
Track restores.
In a first aspect, the utility model provides a kind of full duplex clocked data transfer system, the system comprises duplexing sources
End and duplexing receiving end, the duplex source are connect with the duplexing receiving end by cable, wherein the duplex source and duplex are received
End includes:
Drive module and receiving processing module are sent, is connected respectively with the decoding of reception data and transmission data coding module
It connects, and is connect by cable with opposite end, for the number to be sent after the decoding of reception data and transmission data coding module coding
According to being initialized；
Clock Extraction amplification module, connect with receiving processing module, for carrying out clock recovery；
Data tracking sampling module is received, is connect with receiving processing module, is used to analyze the received data carry out tracking sampling；
Phase-locked loop module is connect with Clock Extraction amplification module, for carrying out locking and frequency multiplication to the clock of recovery；
Clock and data recovery module is connect with reception data tracking sampling module and phase-locked loop module, for next
The clock of phase locked loop module and from receive data tracking sampling module data restored；
It receiving data decoding and sends data coding module, being connect with clock and data recovery module, when for coming from
The data of clock and data recovery module carry out encoding and decoding.
Optionally, the transmission drive module and receiving processing module are also used to carry out noise to sent data
Optimization processing, so that the receiving processing module that remains in of data to be sent keeps minimum.
Optionally, the duplexing receiving end, for by receiving data decoding and sending data coding module to the duplex
The training pattern of source loopback coding, and receive the training pattern that the duplexing source is sent；
The duplex source, for being sent to the duplexing receiving end after receiving the correct trained pattern of duplex transmission
In addition training pattern；
The duplex source and duplexing receiving end, for entering after receiving the correct trained pattern of predetermined number
Duplex data interacts normal mode of operation.
Full duplex clocked data transfer system provided by the embodiment of the utility model, it is embedded in chip-scale integration realization
The data interaction of accessory channel is passed through coding form, is embedded into clock signal by the clock transfer of data, saves version grade electricity
Road design, reduces information exchange complexity.Guarantee receive clock performance while, complete Various Complex signal with
Track restores.
Detailed description of the invention
Fig. 1 is duplexing source or duplexing receiving end in full duplex clocked data transfer system provided by the embodiment of the utility model
Structural block diagram；
Fig. 2 is the flow chart of full duplex clocked data transfer method provided by the embodiment of the utility model；
Fig. 3 is that logical signal provided by the embodiment of the utility model defines and receive signal trace locking schematic diagram；
Fig. 4 is that data provided by the embodiment of the utility model have codeless phaselocked loop output phase noise vs to scheme.
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is only the utility model a part of the embodiment, instead of all the embodiments.Based in the utility model
Embodiment, every other embodiment obtained by those of ordinary skill in the art without making creative efforts, all
Belong to the range of the utility model protection.
The utility model embodiment provides a kind of full duplex clocked data transfer system, the system comprises duplexing source and
Duplexing receiving end, the CCA+ and CCA- of the duplex source are connect with the CCA+ and CCA- of the duplexing receiving end by cable respectively,
Wherein, as shown in Figure 1, the duplex source and duplexing receiving end include:
Drive module M101 and receiving processing module M102 is sent, decodes and send respectively data encoding with reception data
Module M107 connection, and connect by cable with opposite end, for receiving, data to be decoded and transmission data coding module M107 is compiled
Data after code are initialized；
Clock Extraction amplification module M103, connect with receiving processing module M102, for carrying out clock recovery；
Data tracking sampling module M104 is received, is connect with receiving processing module M102, is used to analyze the received data progress
Tracking sampling；
Phaselocked loop (Phase Locked Loop, PLL) module M106, connect with Clock Extraction amplification module M103, is used for
Locking and frequency multiplication are carried out to the clock of recovery；
Clock and data recovery module M105 connects with data tracking sampling module M104 and phase-locked loop module M106 is received
It connects, it is extensive for being carried out to the clock from phase-locked loop module M106 and from the data for receiving data tracking sampling module M104
It is multiple；
It receives data decoding and sends data coding module M107, connect, be used for clock and data recovery module M105
Encoding and decoding are carried out to the data from clock and data recovery module M105.
Further, the transmission drive module M101 and receiving processing module M102, is also used to sent number
According to noise optimization processing is carried out, so that the receiving processing module M102 that remains in of data to be sent keeps minimum.
Further, the duplexing receiving end, for by receiving data decoding and sending data coding module M107 to institute
The training pattern of duplexing source loopback coding is stated, and receives the training pattern that the duplexing source is sent；
The duplex source, for being sent to the duplexing receiving end after receiving the correct trained pattern of duplex transmission
In addition training pattern；
The duplex source and duplexing receiving end, for entering after receiving the correct trained pattern of predetermined number
Duplex data interacts normal mode of operation.
Full duplex clocked data transfer system provided by the embodiment of the utility model, it is embedded in chip-scale integration realization
The data interaction of accessory channel is passed through coding form, is embedded into clock signal by the clock transfer of data, saves version grade electricity
Road design, reduces information exchange complexity.Guarantee receive clock performance while, complete Various Complex signal with
Track restores.
The utility model embodiment also provides a kind of full duplex clocked data transfer method, as depicted in figs. 1 and 2, described
Full duplex clocked data transfer method includes:
The reception data of duplexing source decode and send data coding module M107 and carry out logic coding to data to be sent,
The data to be sent after coding are initialized in transmission drive module M101 and receiving processing module M102 simultaneously, and excellent
Changing noise makes the receiving processing module M102 that remains in of data to be sent keep minimum, then sends through transferring grade and cable
To the receiving processing module M102 of duplexing receiving end；
It is extensive that the Clock Extraction amplification module M103 of duplexing receiving end carries out clock to the data from receiving processing module M102
Multiple, phase-locked loop module M106 carries out locking and frequency multiplication to the clock of recovery, receives data tracking sampling module M104 to from connecing
The data for receiving processing module M102 carry out tracking sampling, and clock and data recovery module M105 is to from phase-locked loop module M106's
Clock and from receive data tracking sampling module M104 data restored, receive data decoding and send data encoding
Module M107 carries out encoding and decoding to the data from clock and data recovery module.
Reception data decoding in duplexing receiving end simultaneously and the training pattern for sending data coding module M107 loopback coding
I, transmission drive module M101 and receiving processing module M102 in duplexing receiving end carry out noise optimization processing, so that loopback number
Good state can be kept according to reception data.After duplexing source receives correctly training pattern I, start to send midamble code
Type II.Duplexing receiving end retransmits trained pattern III after receiving correctly training pattern II, and duplexing receiving end is waiting one section
After time, into duplex data interaction normal mode of operation.After duplexing source receives correctly training pattern III, into double
Number is according to interactive mode.Duplexing source/duplex receiving end both sides start to send the interactive information such as DDC, UART, IR, ARC.
As shown in figure 3, describing the definition of logic level " 0 " and " 1 ".Logical zero indicates duty in a signal period
High level than 25%；Logical one indicates the high level of duty ratio 75% in a signal period.Receiving data indicates in source
Or the data that receiving end receives, this data has cut the data of local terminal transmission, and adjusting parameter optimizes noise, so that hair
The residual of data is sent to keep minimum.SCLK clock is the high power clock after phase lock loop locks, is receiving data tracking sampling module
Before sampling receives data in M104, first adjustment phase place, the variation of tracking data rising edge, re-sampling recovery data.
As shown in figure 4, thering are codeless phaselocked loop output phase noise vs to scheme for data, wherein curve 1 is no coding
Phaselocked loop output phase noise curve figure, curve 2 be coding after phaselocked loop output phase noise curve figure.
Full duplex clocked data transfer method provided by the embodiment of the utility model, based on 0/1 data are re-defined, with utilization
Phaselocked loop list is theoretical along locking, realizes data and clock in physical link grade and sends from duplexing source, independent in duplexing receiving end
Recovered clock handles locking data；Simultaneously the data in duplexing receiving end are encoded passback as required, tracks and solve in duplexing source
The data of code passback.While guaranteeing to receive the performance of clock, the tracking for completing Various Complex signal restores.
Above description is only a specific implementation of the present invention, but the protection scope of the utility model is not limited to
In this, anyone skilled in the art within the technical scope disclosed by the utility model, the change that can be readily occurred in
Change or replace, should be covered within the scope of the utility model.Therefore, the protection scope of the utility model should be with power
Subject to the protection scope that benefit requires.
Claims (3)
1. a kind of full duplex clocked data transfer system, which is characterized in that the system comprises duplexing source and duplexing receiving end, institutes
It states duplexing source and is connect with the duplexing receiving end by cable, wherein the duplex source and duplexing receiving end include:
Drive module and receiving processing module are sent, is connect respectively with the decoding of reception data and transmission data coding module, and
It is connect by cable with opposite end, for being carried out to the data to be sent after the decoding of reception data and transmission data coding module coding
Initialization；
Clock Extraction amplification module, connect with receiving processing module, for carrying out clock recovery；
Data tracking sampling module is received, is connect with receiving processing module, is used to analyze the received data carry out tracking sampling；
Phase-locked loop module is connect with Clock Extraction amplification module, for carrying out locking and frequency multiplication to the clock of recovery；
Clock and data recovery module is connect with reception data tracking sampling module and phase-locked loop module, for self-locking to coming
The clock of phase ring moulds block and from receive data tracking sampling module data restored；
Receive data decoding and send data coding module, connect with clock and data recovery module, for from clock with
The data of data recovery module carry out encoding and decoding.
2. system according to claim 1, which is characterized in that the transmission drive module and receiving processing module, also
For carrying out noise optimization processing to sent data, so that the receiving processing module that remains in of data to be sent is kept most
It is small.
3. system according to claim 1 or 2, which is characterized in that the duplex receiving end, for by receiving data decoding
The training pattern encoded with transmission data coding module to the duplexing source loopback, and receive the duplexing source transmission
Training pattern；
The duplex source, for being sent in addition to the duplexing receiving end after receiving the correct trained pattern of duplex transmission
Training pattern；
The duplex source and duplexing receiving end, for after receiving the correct trained pattern of predetermined number, into duplex
Data interaction normal mode of operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820648160.0U CN208227041U (en) | 2018-05-02 | 2018-05-02 | Full duplex clocked data transfer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820648160.0U CN208227041U (en) | 2018-05-02 | 2018-05-02 | Full duplex clocked data transfer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208227041U true CN208227041U (en) | 2018-12-11 |
Family
ID=64510385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820648160.0U Withdrawn - After Issue CN208227041U (en) | 2018-05-02 | 2018-05-02 | Full duplex clocked data transfer system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108390751A (en) * | 2018-05-02 | 2018-08-10 | 基石酷联微电子技术（北京）有限公司 | Full duplex clocked data transfer system and method |
| US10778405B2 (en) * | 2018-07-13 | 2020-09-15 | Realtek Semiconductor Corporation | Clock generating circuit and hybrid circuit |
-
2018
- 2018-05-02 CN CN201820648160.0U patent/CN208227041U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108390751A (en) * | 2018-05-02 | 2018-08-10 | 基石酷联微电子技术（北京）有限公司 | Full duplex clocked data transfer system and method |
| CN108390751B (en) * | 2018-05-02 | 2023-12-22 | 基石酷联微电子技术（北京）有限公司 | Full duplex clock data transmission system and method |
| US10778405B2 (en) * | 2018-07-13 | 2020-09-15 | Realtek Semiconductor Corporation | Clock generating circuit and hybrid circuit |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20181211 Effective date of abandoning: 20231222 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20181211 Effective date of abandoning: 20231222 |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |