CN205211793U - LED support - Google Patents
LED support Download PDFInfo
- Publication number
- CN205211793U CN205211793U CN201520696596.3U CN201520696596U CN205211793U CN 205211793 U CN205211793 U CN 205211793U CN 201520696596 U CN201520696596 U CN 201520696596U CN 205211793 U CN205211793 U CN 205211793U
- Authority
- CN
- China
- Prior art keywords
- circuit substrate
- top layer
- layer circuit
- led support
- led
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Abstract
The utility model discloses a LED support, including top layer circuit substrate and bottom circuit substrate, it has the through -hole to bore on the top layer circuit substrate, and the bottom circuit substrate is openly electroplated with back etching and is formed with LED wafer brilliant circuit admittedly, and the top layer circuit substrate is adhere in the front of bottom circuit substrate, the utility model discloses LED support is formed by the bonding of top layer circuit substrate and bottom circuit substrate, and the etching of bottom circuit substrate is electroplated has the solid brilliant circuit of LED wafer, and it has the through -hole to bore on the top layer circuit substrate, and not only die sinking expense is very low, low in manufacturing cost, does not have the clearance moreover between top layer circuit substrate and the bottom circuit substrate, can influence the work of LED wafer because of the access of humidity contacts the LED wafer, need not to be water repellent, and use cost hangs down, production efficiency and yields height.
Description
Technical field
The utility model relates to technical field of semiconductor illumination, is specifically related to a kind of LED support.
Background technology
Current existing LED support is generally made up of metal terminal and plastic layer, and metal terminal is wrapped in plastic layer by the mode of injection moulding by plastic layer, and during encapsulation, LED wafer die bond bonding wire is electrically connected with metal terminal, then drips rubber seal dress; But the LED support of this kind of structure not only die sinking is costly, and in the external force situation such as to expand with heat and contract with cold, easily produce gap between metal terminal and plastic layer, moisture during use in air can enter contact LED wafer by this gap, causes LED wafer not work; The LED support waterproof ability of said structure is also very poor, needs to do water-proofing treatment separately to it during use, adds use cost; And the LED support production of said structure comprises procedure of processings such as rushing metal terminal, plating, injection-molded plastic layer and folding pin, needs various processing equipment to coordinate, the finished product consistency produced is poor, yields is low, production efficiency is also low.
Summary of the invention
For the deficiencies in the prior art, the utility model aims to provide a kind of low cost of manufacture, without the need to doing, water-proofing treatment, production efficiency are high, moisture cannot enter the LED support formed by two-tier circuit base plate bonding affecting LED wafer work.
For achieving the above object, the utility model adopts following technical scheme:
A kind of LED support, comprise top layer circuit substrate and bottom circuit substrate, described top layer circuit substrate is drilled with through hole, and described bottom circuit substrate front and back etching plating is formed with LED wafer die bond circuit, and top layer circuit substrate is bonded in the front of bottom circuit substrate.
Further, the edge markedness of described top layer circuit substrate.
Further, described top layer circuit substrate front is printed with coating.
The utility model has following beneficial effect:
The utility model LED support is bonded by top layer circuit substrate and bottom circuit substrate and is formed, bottom circuit substrate etching is electroplate with LED wafer die bond circuit, top layer circuit substrate is drilled with through hole, not only die sinking expense is very low, low cost of manufacture, and it is very close to each other between top layer circuit substrate and bottom circuit substrate, can not affect LED wafer work because moisture enters contact LED wafer, also without the need to doing water-proofing treatment, use cost is low; There is the advantage that production efficiency is high, finished product LED support quality conformance is good and yields is high simultaneously.
Accompanying drawing explanation
Fig. 1 is the left surface structural representation of a kind of LED support of the utility model;
Fig. 2 is the finished product front schematic view of a kind of LED support of the utility model;
Fig. 3 is the structural representation of the top layer circuit substrate of a kind of LED support of the utility model;
Fig. 4 is the Facad structure schematic diagram of the bottom circuit substrate of a kind of LED support of the utility model;
Fig. 5 is the structure schematic diagram of the bottom circuit substrate of a kind of LED support of the utility model.
In figure: 1, top layer circuit substrate; 2, bottom circuit substrate; 11, through hole; 12, mark; 21, LED wafer die bond circuit.
Embodiment
Below in conjunction with drawings and the specific embodiments, the utility model will be further described, understands the technological thought that the utility model is claimed so that clearer.
A kind of LED support of the utility model as Figure 1-5, comprise top layer circuit substrate 1 and bottom circuit substrate 2, top layer circuit substrate 1 is drilled with through hole 11, the edge markedness 12 of top layer circuit substrate 1, top layer circuit substrate 1 front is printed with coating, bottom circuit substrate 2 front and back etching plating is formed with LED wafer die bond circuit 21, and top layer circuit substrate 1 is bonded in the front of bottom circuit substrate 2.
Operation principle of the present utility model is: LED support is bonded by top layer circuit substrate 1 and bottom circuit substrate 2 and formed, bottom circuit substrate 2 etching is electroplate with LED wafer die bond circuit 21, top layer circuit substrate 1 is drilled with through hole 11, not only die sinking expense is very low, low cost of manufacture, very close to each other between top layer circuit substrate 1 and bottom circuit substrate 2, can not affect LED wafer work because moisture enters contact LED wafer, also without the need to doing water-proofing treatment, use cost is low; Coordinate processing without the need to too many process equipment during production, production efficiency finished product LED support quality conformance that is high, that produce is good, yields is high.
For a person skilled in the art, according to technical scheme described above and design, other various corresponding change and distortion can be made, and all these change and distortion all should belong within the protection range of the utility model claim.
Claims (3)
1. a LED support, it is characterized in that: comprise top layer circuit substrate (1) and bottom circuit substrate (2), described top layer circuit substrate (1) is drilled with through hole (11), described bottom circuit substrate (2) front and back etching plating is formed with LED wafer die bond circuit (21), and top layer circuit substrate (1) is bonded in the front of bottom circuit substrate (2).
2. a kind of LED support as claimed in claim 1, is characterized in that: the edge markedness (12) of described top layer circuit substrate (1).
3. a kind of LED support as claimed in claim 1 or 2, is characterized in that: described top layer circuit substrate (1) front is printed with coating.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520696596.3U CN205211793U (en) | 2015-09-09 | 2015-09-09 | LED support |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520696596.3U CN205211793U (en) | 2015-09-09 | 2015-09-09 | LED support |
Publications (1)
Publication Number | Publication Date |
---|---|
CN205211793U true CN205211793U (en) | 2016-05-04 |
Family
ID=55849492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201520696596.3U Expired - Fee Related CN205211793U (en) | 2015-09-09 | 2015-09-09 | LED support |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN205211793U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105206734A (en) * | 2015-09-09 | 2015-12-30 | 梁高华 | LED support and manufacturing method thereof |
-
2015
- 2015-09-09 CN CN201520696596.3U patent/CN205211793U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105206734A (en) * | 2015-09-09 | 2015-12-30 | 梁高华 | LED support and manufacturing method thereof |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160504 Termination date: 20190909 |