CN205123755U

CN205123755U - Be applied to B sign indicating number decoder module in electric power time service

Info

Publication number: CN205123755U
Application number: CN201520809784.2U
Authority: CN
Inventors: 史占强; 段敬红
Original assignee: Tianjin 764 Communication and Navigation Technology Corp
Current assignee: Tianjin 764 Communication and Navigation Technology Corp
Priority date: 2015-10-20
Filing date: 2015-10-20
Publication date: 2016-03-30
Anticipated expiration: 2025-10-20

Abstract

The utility model discloses a be applied to B sign indicating number decoder module in electric power time service. This module includes a FPGA, ARM7, two way light module interface and RS232 module interface of the same kind, wherein, FPGA passes through the bus and is connected with ARM7, the two tunnel solely module interface is connected with FPGA, the RS232 module interface that goes the same way is connected with ARM7. The utility model discloses produced beneficial effect is: this module can accurately be separated steadily and appeared the time information that carries in the B sign indicating number, owing to use the optical fiber transmission B coded data certificate, so the strong anti -interference ability that increases that can be very big.

Description

Be applied to the B code decoder module in electric power time service

Technical field

The utility model relates to optical signal data transmission, particularly relates to a kind of B code decoder module be applied in electric power time service.

Background technology

IRIG-B IRIG-B format time code (being called for short B code) is international time format code, for the time synchronized of system.The frame rate of B code is 1 frame per second, can carry the information of 100.The carry information amount of B code is large, can obtain BCD(BCD after decoding) temporal information of encoding and controlling functions information, have very high resolution, the B code bandwidth after modulation is applicable to long-distance transmissions.

In the department such as electric power, telecommunications owing to needing time that precision is very high as synchronously, B code, with its actual outstanding superior function, becomes the standard pattern of timing equipment first-selection.

B code transmission means the most frequently used is at present Transistor-Transistor Logic level, but the electromagnetic interference of the department such as electric power, telecommunications is a lot, and Transistor-Transistor Logic level under electromagnetism complex environment or long range propagation time be easily interfered, cause error in data.And the interference that light signal is subject under the electromagnetic environment of complexity is very little, and long range propagation is also very little to the decay of light signal, so the B code source transmission means that this module externally receives is light signal.

Summary of the invention

In view of prior art Problems existing and defect, this practical property provides a kind of B code decoder module be applied in electric power time service.

The technical scheme that the utility model is taked is: a kind of B code decoder module be applied in electric power time service, it is characterized in that: this module comprises one piece of FPGA, one piece of ARM7, two-way optical module interface and road RS232 module interface, wherein, FPGA is connected with ARM7 by bus, two-way optical module interface is connected with FPGA, and a road RS232 module interface is connected with ARM7.

The beneficial effect that the utility model produces is: this module can parse the temporal information of carrying in B code accurately and stably, owing to using Optical Fiber Transmission B code data, so can strengthen antijamming capability greatly.

Accompanying drawing explanation

Fig. 1 is the utility model B code schematic diagram;

Fig. 2 is the utility model catenation principle block diagram.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail:

With reference to Fig. 1, B code form and specification: B code is the time string code of 1 frame per second, and each symbol width is 10ms, and a time frame cycle comprises 100 code elements, is pulsewidth coding.During " on time " reference point of code element, its pulse front edge, the reference mark of time frame is made up of a location recognition mark and adjacent reference symbols sn, and its width is 8ms; Every 10 code elements have a location recognition mark, and they are 8ms width; PR is frame reference point, binary system ' 1 ' and ' 0 ' pulsewidth be 5ms and 2ms.

With reference to Fig. 2, this module comprises one piece of FPGA, and one piece of ARM7, two-way optical module interface and road RS232 module interface, wherein, FPGA is connected with ARM7 by bus, and two-way optical module interface is connected with FPGA, and a road RS232 module interface is connected with ARM7.

Wherein FPGA model is EP2C8T144, ARM7 model is LPC2138, and two-way optical module connecter type is FLAF-1300-40X.

Utility model works principle: the decoding of this module to B code is exactly the information such as the Hour Minute Second comprised in B code extracted, the form becoming other module or equipment to identify by protocol packing.The key of decoding is the high level width detecting each code element in B code, the position of the code element appearance that continuous two 8ms are wide first will be detected, and then monitoring 30 symbol pulses width subsequently, to determine Hour Minute Second equal time information.

Optical module is converted to being received from the extraneous optical information carrying B code information the Transistor-Transistor Logic level carrying B code information, and is passed to FPGA.Via FPGA decoding, then wherein will pass to ARM7 by carry information, ARM7 is sent after data processing by RS232 module again.

FPGA detects the Transistor-Transistor Logic level of A, B two-way B code respectively to when becoming high level from low level, starts timing.FPGA judges the width of high level according to timing time.According to width, each pulse of B code is decoded, form the binary-coded decimal of Hour Minute Second, stored in the RAM opened up in FPGA, A, B two-way B code data calculated is waited for that ARM7 reads.FPAG adopts Double buffer mode to store data, and when FPGA reads data for ARM7 after first buffering write data, then the B code temporal information of next frame is deposited in another buffer memory, guarantees that, when reading cache data, current cache data can not change.

The temporal information read is carried out com-parison and analysis by ARM7, and the time data choosing the better road of signal quality packing of being encoded is sent by RS232 module again.

Claims

1. one kind is applied to the B code decoder module in electric power time service, it is characterized in that: this module comprises one piece of FPGA, one piece of ARM7, two-way optical module interface and road RS232 module interface, wherein, FPGA is connected with ARM7 by bus, two-way optical module interface is connected with FPGA, and a road RS232 module interface is connected with ARM7.

2. the B code decoder module be applied in electric power time service according to claim 1, is characterized in that: FPGA model is EP2C8T144, ARM7 model is LPC2138, and two-way optical module connecter type is FLAF-1300-40X.