CN103490841A - Clock recovery method based on distributed frame header in multi-path E1 multiplexing system - Google Patents
Clock recovery method based on distributed frame header in multi-path E1 multiplexing system Download PDFInfo
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- CN103490841A CN103490841A CN201310441103.7A CN201310441103A CN103490841A CN 103490841 A CN103490841 A CN 103490841A CN 201310441103 A CN201310441103 A CN 201310441103A CN 103490841 A CN103490841 A CN 103490841A
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Abstract
The invention relates to a clock recovery method based on a distributed frame header in a multi-path E1 multiplexing system. The clock recovery method includes the steps that data frames of multiple paths of E1 are combined into a data frame by a sending end, frame header information is distributed in the data frame at equal intervals, and then the data frame is sent at the rate synchronous with the rate of a TDM service clock; the frame header of the received data frame is analyzed by a receiving end, frame data of the analyzed data frame are written in an FIFO buffer area, and a read pointer transmits data in the buffer area to a terminal device according to the rate of a transmitter clock extracted from an HDB3 code. The phase difference of the read pointer and a write pointer is used as compensation for recovering the clock, compensation frequency and accuracy are improved through the distributed frame header design, and the clock recovered at the receiving end has good jittering and drifting indexes.
Description
Technical field
The present invention relates to Communication and Information Systems class network transmission technology field, the clock recovery method based on distributed frame head in especially a kind of E1 multiplex system.
Background technology
Digital communication has become the important means of present information transmission, in order to enlarge transmission capacity and to improve efficiency of transmission, usually to be merged into a high-speed channel to several low speed digital signals, and then transmit by IA High Speed Channel, by the digital multiplexing technology, realize collecting of this digital signal.
The digital multiplexing technology is not only the know-how mutually arranged side by side with information source coding, Digital Transmission, numeral exchange, but also is the time-division basis of technology such as continue in framing control, the line sharing in line concentrator and the numeral exchange of net in synchronous.Multiplexing equipment receives Frame, need to give recovered clock level and smooth and up to specification when the resolution data frame, the general method adopted is to use the clock phase detector to be used as the basis of phase-locked loop phase demodulation, and being exactly resolution, the shortcoming of such phase detector can only reach a bit, when recovered clock approaches very much, differ and be accumulated to a bit and need long time, this has just produced larger jitter and wander.
Summary of the invention
The object of the present invention is to provide and a kind ofly make clock that receiving terminal recovers there is good shake and drift index, can obtain the clock recovery method based on distributed frame head in the E1 multiplex system of high performance recovered clock.
For achieving the above object, the present invention has adopted following technical scheme: the clock recovery method based on distributed frame head in a kind of E1 multiplex system, and the method comprises the step of following order:
(1) transmitting terminal will need the clock sent to pass through the HDB3 encoding setting in Frame, and this Frame is sent to receiving terminal by optical fiber;
(2) transmitting terminal is merged into a Frame by the Frame of multichannel E1, and by frame originating point information to be spacedly distributed in Frame;
(3) receiving terminal carries out reading and decoding of clock, level and smooth through code quick-recovery circuit and internal digital phase-locked loop circuit, carries out the recovery of clock;
(4) receiving terminal is resolved the frame head of the Frame that receives, and the frame data of parsing are write in the FIFO elastic caching;
(5) receiving terminal sends the data of FIFO elastic caching to terminal equipment by read pointer according to the clock rate of extracting from the HDB3 code.
Transmitting terminal is divided into 4 sections by the frame originating point information of 2 bytes, and every section is 4 bits, and 4 sections frame originating point informations are distributed in Frame according to equally spaced mode.
Receiving terminal is resolved the Frame received, and by write pointer, frame data is write in the FIFO elastic caching; Read pointer is read away data send to terminal equipment according to the clock recovered from HDB3 from the FIFO elastic caching.
Poor detecting value is set a set point to give the read-write pointer, when the detecting value is greater than set point, the clock recovered is done to the reduction of speed compensation, otherwise, do and accelerate compensation.
The poor detecting value of read-write pointer is greater than the maximum of frame head length.
As shown from the above technical solution, the transmitting terminal in the present invention is merged into a Frame by the Frame of multichannel E1, and frame originating point information is distributed in Frame in mode uniformly-spaced, the synchronous rate sending data frame with the TDM business clock; Receiving terminal is resolved the frame head of the Frame that receives, and the frame data of the Frame of parsing are write in fifo buffer, and read pointer sends the data in buffering area to terminal equipment according to the speed of the tranmitting data register extracted from the HDB3 code.The present invention utilizes the phase difference of reading and writing pointer to carry out the compensation as recovered clock, and has improved frequency and the precision of compensation by the design of distributed frame head, can make the clock recovered at receiving terminal have good shake and drift index.
The accompanying drawing explanation
Fig. 1 is system configuration schematic diagram of the present invention;
Fig. 2 is that in the present invention, transmitting terminal is merged into the multi-channel E 1 data frame in the merging schematic diagram of a Frame;
Fig. 3 is the parsing schematic diagram that in the present invention, receiving terminal is resolved the Frame frame head received;
Fig. 4 is the schematic diagram that accelerates compensation and reduction of speed compensation in the present invention.
Embodiment
Clock recovery method based on distributed frame head in a kind of E1 multiplex system, the method comprises the step of following order: (1) transmitting terminal will need the clock sent to pass through the HDB3 encoding setting in Frame, and this Frame is sent to receiving terminal by optical fiber; (2) transmitting terminal is merged into a Frame by the Frame of multichannel E1, and by frame originating point information to be spacedly distributed in Frame; (3) receiving terminal carries out reading and decoding of clock, level and smooth through code quick-recovery circuit and internal digital phase-locked loop circuit, carries out the recovery of clock; (4) receiving terminal is resolved the frame head of the Frame that receives, and the frame data of parsing are write in the FIFO elastic caching; (5) receiving terminal sends the data of FIFO elastic caching to terminal equipment by read pointer according to the clock rate of extracting from the HDB3 code.
Describe the method for the invention in detail below in conjunction with Fig. 1,2,3,4.
As shown in Figure 1, comprise following equipment:
Sending ending equipment: be merged into a Frame for the Frame by multichannel E1, and by frame originating point information to be spacedly distributed in Frame, the synchronous rate sending data frame with the TDM business clock, pattern is HDB3.
Receiving device: the frame head to the Frame that receives is resolved, and the frame data of the Frame of parsing are write in fifo buffer, and read pointer sends the data in buffering area to terminal equipment according to the speed of the tranmitting data register extracted from HDB3.
As shown in Figure 2, transmitting terminal is merged into a Frame by the Frame of multichannel E1, and the frame originating point information of 2 bytes is divided into to 4 sections, and every section is 4 bits, 4 sections frame originating point informations are distributed in Frame according to equally spaced principle, thereby reduce the length of every section frame originating point information.
As shown in Figure 3, receiving terminal is resolved the Frame received, and by write pointer, frame data is write in the FIFO elastic caching, and therefore, the speed of write pointer equal the speed that Frame arrives from network, should equal under normal circumstances the speed that transmitting terminal sends; Read pointer is read away data send to terminal equipment according to the clock recovered from HDB3 from the FIFO elastic caching.Due to when resolving frame head, the frame head of Frame is not write the FIFO elastic caching, and the while read pointer is in the continual data of reading away from the FIFO elastic caching, be tending towards reading sky for the FIFO elastic caching is unlikely to, need to guarantee that the poor detecting value of read-write pointer is greater than the maximum of frame head length.Due to the impact of jitter and wander, the speed that the speed that the receiving terminal Frame arrives goes out with clock recovery can not be well consistent, need to the clock recovered be compensated.To the compensation of recovered clock according to the poor detecting value of read-write pointer, close relationship being arranged.
To pointer, poor detecting is worth a set point as shown in Figure 4, when the detecting value is greater than set point, the clock recovered is done to the reduction of speed compensation, otherwise, do and accelerate compensation.By single order, the second-order low-pass filter of phase-locked loop, just can realize tracking and the locking to clock, and can obtain good jitter and wander performance so again.Receiving terminal sends the data of FIFO elastic caching to terminal equipment by the read pointer according in constantly adjusting according to the clock rate of extracting from HDB3.
In sum, core of the present invention is: at transmitting terminal, the Frame of multichannel E1 is merged into to a Frame, and by frame originating point information to be spacedly distributed in Frame, the synchronous rate sending data frame with the TDM business clock, pattern is HDB3.Receiving terminal is resolved the frame head of the Frame that receives, and the frame data of the Frame of parsing are write in fifo buffer, and read pointer sends the data in buffering area to terminal equipment according to the speed of the tranmitting data register extracted from HDB3.Utilize the phase difference of read-write pointer to carry out the compensation as recovered clock, and improved frequency and the precision of compensation by the design of distributed frame head.
Claims (5)
1. the clock recovery method based on distributed frame head in an E1 multiplex system, the method comprises the step of following order:
(1) transmitting terminal will need the clock sent to pass through the HDB3 encoding setting in Frame, and this Frame is sent to receiving terminal by optical fiber;
(2) transmitting terminal is merged into a Frame by the Frame of multichannel E1, and by frame originating point information to be spacedly distributed in Frame;
(3) receiving terminal carries out reading and decoding of clock, level and smooth through code quick-recovery circuit and internal digital phase-locked loop circuit, carries out the recovery of clock;
(4) receiving terminal is resolved the frame head of the Frame that receives, and the frame data of parsing are write in the FIFO elastic caching;
(5) receiving terminal sends the data of FIFO elastic caching to terminal equipment by read pointer according to the clock rate of extracting from the HDB3 code.
2. the clock recovery method based on distributed frame head in multichannel E1 multiplex system according to claim 1, it is characterized in that: transmitting terminal is divided into 4 sections by the frame originating point information of 2 bytes, every section is 4 bits, and 4 sections frame originating point informations are distributed in Frame according to equally spaced mode.
3. the clock recovery method based on distributed frame head in multichannel E1 multiplex system according to claim 1, it is characterized in that: receiving terminal is resolved the Frame received, and by write pointer, frame data is write in the FIFO elastic caching; Read pointer is read away data send to terminal equipment according to the clock recovered from HDB3 from the FIFO elastic caching.
4. the clock recovery method based on distributed frame head in multichannel E1 multiplex system according to claim 1, it is characterized in that: the detecting value poor to the read-write pointer set a set point, when the detecting value is greater than set point, the clock recovered done to the reduction of speed compensation, otherwise, do and accelerate compensation.
5. the clock recovery method based on distributed frame head in multichannel E1 multiplex system according to claim 4, it is characterized in that: the poor detecting value of read-write pointer is greater than the maximum of frame head length.
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| CN104393962A (en) * | 2014-12-12 | 2015-03-04 | 成都朗锐芯科技发展有限公司 | Multi-way E1 deframing system |
| CN104486038A (en) * | 2014-12-12 | 2015-04-01 | 成都朗锐芯科技发展有限公司 | Multi-path E1 deframing method |
| CN104486039A (en) * | 2014-12-12 | 2015-04-01 | 成都朗锐芯科技发展有限公司 | Multi-channel E1 frame decoder system |
| CN105656599A (en) * | 2014-11-27 | 2016-06-08 | 航天恒星科技有限公司 | Method and device for continuously adjusting data transmission clock |
| CN106603216A (en) * | 2016-12-06 | 2017-04-26 | 广东高云半导体科技股份有限公司 | E1 timing recovery device of wireless microwave telecommunication system and application thereof |
| CN111277327A (en) * | 2020-01-21 | 2020-06-12 | 国网四川省电力公司 | Line protection communication channel fault area identification method |
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| CN111277327A (en) * | 2020-01-21 | 2020-06-12 | 国网四川省电力公司 | Line protection communication channel fault area identification method |
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Application publication date: 20140101 |