CN104486038B - A kind of multichannel E1 solves frame method - Google Patents
A kind of multichannel E1 solves frame method Download PDFInfo
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Abstract
The present invention relates to a kind of communications field, more particularly to a kind of multichannel E1 solutions frame method, including multichannel HDB3 decoder modules, multiplexer MUX modules, fifo module and E1 deframer modules；Wherein multichannel HDB3 decoder modules are connected with path multiplexer MUX modules successively；The other end of path multiplexer MUX modules is connected with one end of fifo module, and the other end of fifo module is connected with one end of E1 deframer modules；The E1 deframer modules E1_DEFRAMER other end is connected with the next device；Multichannel E1 solution frame data are assembled into serial data stream through multiplexer, so only need an E1 deframer, E1 solution frames can be carried out to recover, reassemble into multi-channel E 1 data, tradition is avoided to be required for an independent deframer per road E1, logic unit needed for E1 deframers is greatlyd save, the bandwidth expansion and communication speed-raising to be communicated based on E1 provide highly effective new way.
Description
Technical field
The present invention relates to a kind of communications field, more particularly to a kind of multichannel E1 solutions frame method.
Background technology
In data communication field, it is most basic frame processing that E1 signals framing, which conciliates frame, according to G.704, per basic frame by
32 channel time slots（ts0-ts31）Composition, each channel time slot, are made up of 8bit codes, and basic frame frame frequency is 8000 frames/second, i.e.,
2.048Mbit/s data press fixed frame structure and carry out framing transmission, receive frame solution frame.
According to《Designs of the E1 into/deframer》（Hunan University's physics and microelectronics science institute, Li Pengcheng, Yan Yonghong are handsome
Jin Xiao, Guo Youhong）E1 includes e1_framer, tri- modules of e1_deframer, e1pi, e1_framer modules into/deframer
G.704 E1 frame structures as defined in agreement are met to the data composition of transmission；E1_deframer modules are to the data that receive
Solution frame is carried out, i.e., frame part separate and explained；E1pi modules are responsible for transmitting data to line side same
When data are received from circuit, among these include data are detected, clock is recovered from data（Debit to）, carry out code
The conversion of type（Hdb3 encoding and decoding）, coded violation, CV is checked.
E1 relatively describes single channel E1 framing solution frame methods and process in detail into/deframer, but in actual applications, E1 transmitting-receivings
Road is often relatively more, and our conventional 16 road E1 are received and dispatched, if using single channel separate processing approach, it would be desirable to a large amount of logical resources,
To save logical resource, the present invention is assembled into serial data stream through multiplexer using multichannel E1 solution frame data, so only needs one
Individual E1 deframers, so that it may carry out E1 solution frames and recover, reassemble into multi-channel E 1 data, avoid tradition from being required for an independent solution per road E1
Frame device, thus greatly save logic unit needed for E1 deframers.
The content of the invention
It is an object of the invention to overcome the above-mentioned deficiency in the presence of prior art, there is provided a kind of multichannel E1 solution frames system
System.Multichannel E1 solution frame data are assembled into serial data stream through multiplexer, so only need an E1 deframer, so that it may carry out E1
Solve frame to recover, reassemble into multi-channel E 1 data, avoid tradition from being required for an independent deframer per road E1, greatly save E1 deframers
Required logic unit.
In order to realize foregoing invention purpose, the invention provides following technical scheme：
A kind of multichannel E1 solves frame system, including multichannel HDB3 decoder modules, multiplexer MUX modules, fifo module and
E1 deframer modules E1_DEFRAMER；Wherein multichannel HDB3 decoder modules are connected with path multiplexer MUX modules successively；Road is multiplexed
The other end of device MUX modules is connected with one end of fifo module, the other end and the E1 deframer modules E1_ of fifo module
DEFRAMER one end is connected；The E1 deframer modules E1_DEFRAMER other end is connected with the next device.
Further, the HDB3 decoder modules, comprising HDB3 decoders, cv_check modules, los_det modules and
Ais_det modules；Wherein HDB3 decoders are respectively connected with cv_check modules, los_det modules and ais_det modules；
In work, per road E1 after the decoding of HDB3 modules, coded violation, CV is detected by cv_check modules respectively, by los_
Det modules detect dropout（los）, detected complete " 1 " by ais_det modules（ais）Alarm；And above-mentioned loss is alerted
Signal Los, fault alarm signal Cv_err and complete " 1 " alarm signal Ais directly send alarming processing.HDB3 codes are a kind of AMI codes
Modified, not only overcome when occurring the shortcomings that even " 0 " code timing detection difficult in AMI codes, and there is spectrum energy master
Concentrate on below fundamental frequency, the advantages of band occupancy is narrower.
Further, the HDB3 decoder modules, also comprising Clk-recovery modules, the Clk-recovery modules
For with recovered clock E1_clk_2M rising edges, and then the recovered clock generated per road enables E1_clk_2M_en, E1_clk_
2M_en；Clk-recovery modules complete HDB3 adaptive clock recoveries, recover the MHz clocks of this road E1 2.048,.
A kind of this course of work following steps of multichannel E1 solutions frame system：
（1）Multi-channel E 1 signal is separately input to per in HBD3 modules all the way；
（2）Decoded per road E1 through HDB3 modules, recover E1 data；Detect whether to have complete " 1 " alarm signal Ais, lose
Alarm signal Los, fault alarm signal Cv_err, such as described complete " 1 " alarm signal Ais, the loss alarm signal Los, institute
State any one of fault alarm signal Cv_err to be detected, then send the alarm signal to alarming processing；
（3）Multiplexer MUX modules carry out circulating sampling, generation multichannel E1_data strings to each road E1 signals by passage
Row data flow,
(4) multiplexer MUX modules write the E1_data serial data streams in FIFO；
（5）E1 deframers module from FIFO read data carry out solve frame processing, respectively generate LOF, LOM, FAS-ERR,
CRC-ERR is alerted and passage E1_data data output is into the next device.
Multichannel E1 solution frame data are assembled into serial data stream by the system through multiplexer, so only need an E1 solution frame
Device, so that it may carry out E1 solution frames and recover, reassemble into multi-channel E 1 data, avoid tradition from being required for an independent deframer per road E1, greatly
It is big to save logic unit needed for E1 deframers.
Further, multiplexer MUX modules in the system, use each channel frequence of high-frequency clock circulating sampling for
2.048 MHz E1 signals, recover every road E1 clocks E1_clk_2M and per road E1 data E1_data.
Further, the multiplexer MUX modules, when used multiplexing clock 81.92MHz and passage E1 is sampled
Clock is identical；Data E1_data of the loop cycle multiplexing per road E1, adds the serial data for per road e1 port number, forming multichannel
Stream into FIFO.
Further, the multi-channel serial data of generation are streamed recurrent wrIting FIFO by the multiplexer MUX modules
In.
Further, the FIFO selects 32*5bit, wherein+1 data of 4bit port numbers；FIFO is set according to system
Meter requirement is selected.
Further, during work, the E1 deframer module cycles the next FIFO read the data stored in FIFO；E1 is solved
The way for the E1 signals that the selection of frame device module read cycle is selected according to system and set.
Further, the E1 deframers module cycle reads data fifo, according to data terminal slogan, takes out deframer RAM block
In data, be put into common shift register Shift_reg, data displacement, data are write back in original RAM after displacement, in RAM
Deposit each tunnel ends slogan, data, slot count（ts_cnt）, basic frame count（bf_cnt）, multi-frame counting（mf_cnt）,
Position counts（bit_cnt）, CRC countings（crc_cnt）.Deframer output LOF, LOM, FAS_ERR, CRC_ERR alarm, port and
Port solves frame data.Deframer deposits all passage ephemeral datas using RAM, and such other parts can be shared, and realization is patrolled
Collect making full use of for resource.
Further, solution frame data RAM is output in data buffer storage by Byte and passage.
Further, the system includes 16 road E1 signals.
Further, the system includes 32 road E1 signals.
Compared with prior art, beneficial effects of the present invention：E1 solutions frame design of the prior art is believed per E1 all the way
Number a set of solution frame system of correspondence, i.e., need to include an independent FIFO and E1 deframer module per E1 signals all the way,
So by taking 16 road E1 signals as an example, 16 FIFO and 16 E1 deframer modules are just at least needed, and 32 road E1 signals just need
At least 32 FIFO and 32 E1 deframer modules, with the increase of the bandwidth of system and the quickening of speed, required solution frame
The scale of system is also more and more huger, and similarly the logic unit required for these huge solution frame systems also greatly increases, and increases
Add the complexity of system, and this is also one of the important factor in order of limitation based on the speed-raising of E1 signal communications and spread bandwidth,
The present invention provides a kind of multichannel E1 solutions frame system, and structure includes multichannel HDB3 decoder modules, multiplexer MUX modules, FIFO
Module and E1 deframer modules E1_DEFRAMER；Wherein multichannel HDB3 decoder modules are connected with path multiplexer MUX modules successively；
The other end of path multiplexer MUX modules is connected with one end of fifo module, the other end and the E1 deframer modules E1_ of fifo module
DEFRAMER one end is connected；The E1 deframer modules E1_DEFRAMER other end is connected with the next device；Multichannel E1 is solved into frame
Data are assembled into serial data stream through multiplexer, so only need an E1 deframer, so that it may carry out E1 solution frames and recover, reassemble into
Multi-channel E 1 data, avoid tradition from being required for an independent deframer per road E1, greatly save E1 deframers needed for logic unit, be
Bandwidth expansion and communication speed-raising based on E1 signal communications provide highly effective new way, can be applied to various based on E1 letters
Number communication system in.
Brief description of the drawings：
Fig. 1 is that this multichannel E1 solves frame system structural representation.
Fig. 2 is HDB3 decoder module structural representations.
Fig. 3 is that this multichannel E1 solves frame system method flow schematic diagram.
Fig. 4 is the structural representation of embodiment 1.
Fig. 5 is the structural representation of embodiment 2.
Embodiment
With reference to test example and embodiment, the present invention is described in further detail.But this should not be understood
Following embodiment is only limitted to for the scope of the above-mentioned theme of the present invention, it is all that this is belonged to based on the technology that present invention is realized
The scope of invention.
It is an object of the invention to overcome the above-mentioned deficiency in the presence of prior art, there is provided a kind of multichannel E1 solution frames system
System, multichannel E1 solution frame data are assembled into serial data stream through multiplexer, so only need an E1 deframer, so that it may carry out E1
Solve frame to recover, reassemble into multi-channel E 1 data, avoid tradition from being required for an independent deframer per road E1, greatly save E1 deframers
Required logic unit.
In order to realize foregoing invention purpose, the invention provides following technical scheme：
A kind of multichannel E1 solves frame system, as shown in figure 1, including multichannel HDB3 decoder modules, multiplexer MUX modules,
Fifo module and E1 deframer modules E1_DEFRAMER；Wherein multichannel HDB3 decoder modules successively with path multiplexer MUX module phases
Even；The other end of path multiplexer MUX modules is connected with one end of fifo module, the other end and the E1 deframer modules of fifo module
E1_DEFRAMER one end is connected；The E1 deframer modules E1_DEFRAMER other end is connected with the next device.
Further, the HDB3 decoder modules, as shown in Fig. 2 comprising HDB3 decoders, Clk-recovery modules,
Cv_check modules, los_det modules and ais_det modules；Wherein HDB3 decoders and cv_check modules, Clk-
Recovery modules, los_det modules and ais_det modules are respectively connected with；
Zhong Mei road E1 work after the decoding of HDB3 modules, coded violation, CV is detected by cv_check modules respectively, by los_
Det modules detect dropout（los）, detected complete " 1 " by ais_det modules（ais）Alarm；And above-mentioned loss is alerted
Signal Los, fault alarm signal Cv_err and complete " 1 " alarm signal Ais directly send alarming processing.
Further, as shown in Fig. 2 when working, the Clk-recovery modules in HDB3 decoder modules, for recovery
Clock E1_clk_2M rising edges, and then the recovered clock generated per road enables E1_clk_2M_en, E1_clk_2M_en.
Further, E1_clk_2M_en controls E1 data E1_data synchronized sampling.
A kind of this method of work of multichannel E1 solutions frame system includes following steps as shown in Figure 3：
（1）Multi-channel E 1 signal is separately input to per in HBD3 modules all the way；
（2）Decoded per road E1 through HDB3 modules, recover E1 data；Detect whether to have complete " 1 " alarm signal Ais, lose
Alarm signal Los, fault alarm signal Cv_err, such as described complete " 1 " alarm signal Ais, the loss alarm signal Los, institute
State any one of fault alarm signal Cv_err to be detected, then send the alarm signal to alarming processing；
（3）Multiplexer MUX modules carry out circulating sampling by passage to E1 signals, generate multichannel E1_data serial numbers
According to stream;
(4) multiplexer MUX modules write the E1_data serial data streams in FIFO；
（5）E1 deframers module from FIFO read data carry out solve frame processing, respectively generate LOF, LOM, FAS-ERR,
CRC-ERR is alerted and passage E1_data data output is into the next device.
Multichannel E1 solution frame data are assembled into serial data stream by the system through multiplexer, so only need an E1 solution frame
Device, so that it may carry out E1 solution frames and recover, reassemble into multi-channel E 1 data, avoid tradition from being required for an independent deframer per road E1, greatly
It is big to save logic unit needed for E1 deframers.
Further, the multiplexer MUX modules, when used multiplexing clock 81.92MHz and passage E1 is sampled
Clock is identical；Data E1_data of the loop cycle multiplexing per road E1, adds the serial data for per road e1 port number, forming multichannel
Stream into FIFO.
Further, the multi-channel serial data of generation are streamed recurrent wrIting FIFO by the multiplexer MUX modules
In.
Further, the FIFO selects 32*5bit, wherein+1 data of 4bit port numbers；FIFO is set according to system
Meter requirement is selected.
Further, during work, the E1 deframer module cycles the next FIFO read the data stored in FIFO；E1 is solved
The way for the E1 signals that the selection of frame device module read cycle is selected according to system and set.
Further, the E1 deframers module cycle reads data fifo, according to data terminal slogan, takes out deframer RAM block
In data, be put into common shift register Shift_reg, data displacement, data are write back in original RAM after displacement, in RAM
Deposit each tunnel ends slogan, data, slot count（ts_cnt）, basic frame count（bf_cnt）, multi-frame counting（mf_cnt）,
Position counts（bit_cnt）, CRC countings（crc_cnt）.Deframer output LOF, LOM, FAS_ERR, CRC_ERR alarm, port and
Port solves frame data.Deframer deposits all passage ephemeral datas using RAM, and such other parts can be shared, and realization is patrolled
Collect making full use of for resource.
Further, solution frame data RAM is output in data buffer storage by Byte and passage.
Embodiment 1
System includes the E1 signals on 16 tunnels, as shown in figure 4, including 16 road HDB3 decoder modules, multiplexer MUX moulds
Block, fifo module and E1 deframer modules E1_DEFRAMER；Wherein 16 road HDB3 decoder modules successively with path multiplexer MUX moulds
Block is connected；The other end of path multiplexer MUX modules is connected with one end of fifo module, the other end and the E1 deframers of fifo module
Module E1_DEFRAMER one end is connected；The E1 deframer modules E1_DEFRAMER other end and the next data cache module
It is connected.
Remaining system architecture and method of work are identical with embodiment, repeat no more.
Embodiment 2
System includes the E1 signals on 32 tunnels, as shown in figure 5, including 32 road HDB3 decoder modules, multiplexer MUX moulds
Block, fifo module and E1 deframer modules E1_DEFRAMER；Wherein 32 road HDB3 decoder modules successively with path multiplexer MUX moulds
Block is connected；The other end of path multiplexer MUX modules is connected with one end of fifo module, the other end and the E1 deframers of fifo module
Module E1_DEFRAMER one end is connected；The E1 deframer modules E1_DEFRAMER other end and the next data cache module
It is connected.
Remaining system architecture and method of work are identical with embodiment, repeat no more.
In a word, E1 solutions frame design of the prior art is all to correspond to a set of solution frame system per E1 signals all the way, i.e., per all the way
E1 signals need to include an independent FIFO and E1 deframer module, so by taking 16 road E1 signals as an example, just at least
16 FIFO and 16 E1 deframer modules are needed, and 32 road E1 signals just need at least 32 FIFO and 32 E1 deframer moulds
Block, with the increase of the bandwidth of system and the quickening of speed, the scale of required solution frame system is also more and more huger, similarly this
Logic unit required for a little huge solution frame systems also greatly increases, and adds the complexity of system, and this is also limitation
One of important factor in order based on the speed-raising of E1 signal communications and spread bandwidth, a kind of multichannel E1 solve frame system, and structure includes more
Road HDB3 decoder modules, multiplexer MUX modules, fifo module and E1 deframer modules E1_DEFRAMER；Wherein multichannel
HDB3 decoder modules are connected with path multiplexer MUX modules successively；The other end of path multiplexer MUX modules and one end of fifo module
It is connected, the other end of fifo module is connected with E1 deframer modules E1_DEFRAMER one end；E1 deframer modules E1_
The DEFRAMER other end is connected with the next device；Multichannel E1 solution frame data are assembled into serial data stream through multiplexer, so
Only need an E1 deframer, so that it may carry out E1 solution frames and recover, reassemble into multi-channel E 1 data, avoid tradition from being required for one per road E1
Individual independent deframer, greatlys save logic unit needed for E1 deframers, is carried for the bandwidth expansion based on E1 signal communications and communication
Speed provides highly effective new way, can be applied in the various communication systems based on E1 signals.
Claims (4)
1. a kind of multichannel E1 solves frame method, it is characterized in that, comprise the steps of：
(1) multi-channel E 1 signal is separately input to per in HBD3 modules all the way；
(2) decoded per road E1 through HDB3 modules, recover E1 data；Complete " 1 " the alarm signal Ais of detection, lose alarm signal
Los, fault alarm signal Cv_err, by described complete " 1 " alarm signal Ais, lose alarm signal Los, fault alarm signal Cv_
Err directly inputs the next device and handled；
(3) multiplexer MUX modules carry out circulating sampling by passage to E1 signals, generate multichannel E1_data serial data streams；
(4) multiplexer MUX writes the E1_data serial data streams in FIFO；
(5) E1 deframers module reads data from FIFO and carries out solving frame processing, generates LOF, LOM, FAS-ERR, CRC-ERR respectively
Alarm and passage E1_data data output are into the next device；
Step (2) the Zhong Mei roads E1 detects coded violation, CV by cv_check modules respectively after the decoding of HDB3 modules, by
Los_det modules detect loss of signal alarm, and complete " 1 " alarm is detected by ais_det modules；
The step (2) alerts above-mentioned loss, fault alarm signal and complete " 1 " alarm signal directly send alarming processing；
HDB3 decoder modules use an each channel frequence of high-frequency clock circulating sampling as 2.048MHz's in the step (2)
E1 signals, recover every road E1 clocks E1_clk_2M and per road E1 data E1_data；
Multiplexer MUX modules described in the step (3), the sampling clock phase of used multiplexing clock and passage E1
Together；Data E1_data of the loop cycle multiplexing per road E1, adds the serial data stream for per road e1 port number, forming multichannel；
The E1 deframer module cycles read the data stored in FIFO described in the step (5), according to data terminal slogan, take
The E1-DATA data and status information gone out in deframer RAM module respective channel, are put into common shift register Shift_reg,
The E1-DATA data of this reading are placed on last position.
2. a kind of multichannel E1 solutions frame method as claimed in claim 1, it is characterized in that, shift register in the step (5)
Shift_reg shifts data, and data are write back in RAM after displacement；The next device is output to after being filled with 8.
3. a kind of multichannel E1 solutions frame method as claimed in claim 1, it is characterized in that, E1 deframer modules in the step (5)
In RAM in storage configuration information, including data, slot count, basic frame count, multi-frame counted, and position is counted and CRC is counted.
4. a kind of multichannel E1 solutions frame method as claimed in claim 2, it is characterized in that, in the step (5), E1 deframer modules
In RAM solution frame data by Byte and passage be output to bottom data buffer storage in.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1406021A (en) * | 2001-09-17 | 2003-03-26 | Lg电子株式会社 | Channel distribution device of optical monitoring channel-unit in wave-division multiplexing system |
| EP1734701A1 (en) * | 2005-06-17 | 2006-12-20 | Alcatel | Encapsulation of E1 frames within Ethernet |
| CN103490841A (en) * | 2013-09-25 | 2014-01-01 | 科大智能（合肥）科技有限公司 | Clock recovery method based on distributed frame header in multi-path E1 multiplexing system |
-
2014
- 2014-12-12 CN CN201410761790.5A patent/CN104486038B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1406021A (en) * | 2001-09-17 | 2003-03-26 | Lg电子株式会社 | Channel distribution device of optical monitoring channel-unit in wave-division multiplexing system |
| EP1734701A1 (en) * | 2005-06-17 | 2006-12-20 | Alcatel | Encapsulation of E1 frames within Ethernet |
| CN103490841A (en) * | 2013-09-25 | 2014-01-01 | 科大智能（合肥）科技有限公司 | Clock recovery method based on distributed frame header in multi-path E1 multiplexing system |
Non-Patent Citations (1)
| Title |
|---|
| E1成/解帧器的设计;李鹏程等;《微计算机信息》;20090823;第2节 * |
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