CN104486039B - A kind of multichannel E1 deframer systems - Google Patents
A kind of multichannel E1 deframer systems Download PDFInfo
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Abstract
The present invention relates to a kind of communications field, more particularly to a kind of multichannel E1 deframer systems, including E1 synchronous processing modules, RAM module, shift reg modules, CRC CHECK modules；Wherein described E1 synchronous processing modules circulate reading data from upper device, the E1 DATA data of respective channel are read from RAM module according to port numbers, move into successively in shift reg modules, and this 1bit read from upper device E1 DATA data are moved into the last position of shift reg modules；New E1 DATA data are written in the respective channel of RAM module；Exported until being filled with after 8.Only need to an E1 deframer, so that it may which the E1 solution frames for carrying out multichannel recover, and reassemble into multi-channel E 1 data, it is to avoid the problem of tradition is required for independent deframer per road E1, greatly save logic unit needed for E1 deframers.
Description
Technical field
The present invention relates to a kind of communications field, more particularly to a kind of multichannel E1 deframer systems.
Background technology
In data communication field, it is most basic frame processing that E1 signals framing, which conciliates frame, according to G.704, per basic frame by
32 channel time slots（ts0-ts31）Composition, each channel time slot, is made up of 8bit codes, and basic frame frame frequency is 8000 frames/second, i.e.,
2.048Mbit/s data press fixed frame structure and carry out framing transmission, receive frame solution frame.
According to《Designs of the E1 into/deframer》（Hunan University's physics and microelectronics science institute, Li Pengcheng, Yan Yonghong are handsome
Jin Xiao, Guo Youhong）E1 includes e1_framer, e1_deframer, tri- modules of e1pi, e1_framer modules into/deframer
G.704 E1 frame structures as defined in agreement are met to the data composition of transmission；E1_deframer modules are to the data that receive
Solution frame, the i.e. progress to frame part is carried out to separate and explained；E1pi modules are responsible for transmitting data to line side same
When data are received from circuit, among these including being detected to data, clock being recovered from data（Debit to）, carry out code
The conversion of type（Hdb3 encoding and decoding）, coded violation, CV is checked.
E1 relatively describes single channel E1 framing solution frame methods and process in detail into/deframer, but in actual applications, E1 transmitting-receivings
Road often compares many, and our conventional 16 road E1 are received and dispatched, if using single channel separate processing approach, it would be desirable to a large amount of logical resources,
To save logical resource, the present invention is assembled into serial data stream through multiplexer using multichannel E1 solution frame data, so only needs to one
Individual E1 deframers, so that it may carry out E1 solution frames and recover, reassemble into multi-channel E 1 data, it is to avoid tradition is required for an independent solution per road E1
Frame device, thus greatlys save logic unit needed for E1 deframers.
The content of the invention
It is an object of the invention to overcome in the presence of prior art above-mentioned not enough there is provided a kind of multichannel E1 deframers system
System.Multichannel E1 is solved into frame data and is assembled into serial data stream through multiplexer, an E1 deframer is so only needed to, so that it may carry out E1
Solve frame to recover, reassemble into multi-channel E 1 data, it is to avoid tradition is required for an independent deframer per road E1, greatlys save E1 deframers
Required logic unit.
In order to realize foregoing invention purpose, the invention provides following technical scheme：
A kind of multichannel E1 deframer systems, including E1 synchronous processing modules, RAM module, shift-reg modules, CRC-
CHECK modules；Wherein, the E1 synchronous processing modules are connected with the RAM module；The E1 synchronous processing modules with it is described
Shift-reg modules are connected；The RAM module is connected with the shift-reg modules；
The E1 synchronous processing modules circulate reading from upper device includes port numbers PORT and 1bit E1-DATA numbers
According to E1 data；
At first according to the E1-DATA data and status information of respective channel in port numbers reading RAM module to E1 synchronizations
Manage in module；
E1 synchronous processing modules carry out corresponding position according to the situation of this E1-DATA data to the status information read
Reason；And write the status information after processing in the respective channel of RAM module；
The E1-DATA data that E1 synchronous processing modules will be read from RAM module, are moved into shift-reg modules successively, and
This 1bit read from upper device E1-DATA data are moved into the last position of shift-reg modules；
E1-DATA data new in shift-reg modules are written in the respective channel of RAM module；
Until the E1-DATA data of respective channel are filled with the next device exported after 8.Sent out by E1 synchronous processing modules
Go out to enable signal by all data and port numbers of above-mentioned passage from RAM module is output to corresponding the next device, so
Just complete the solution frame respectively of multi-channel E 1 signal.
Further, the status information includes slot count, basic frame count, multi-frame counting, position counting and CRC-
RESULT。
Further, the E1 synchronous processing modules, including df_timer modules, wherein E1 synchronous processing modules are from upper
Read in device after data, slot count is provided for other modules by df_timer modules（TS-CNT）, basic frame count（BF-
CNT）, multi-frame counting（MF-CNT）And position is counted（bit-cnt）；Thereafter E1 synchronous processing modules, by described according to port numbers
By above-mentioned slot count（TS-CNT）, basic frame count（BF-CNT）, multi-frame counting（MF-CNT）And position is counted（BIT-CNT）
Result be written in RAM corresponding passage.
Further, the E1 synchronous processing modules, including crc_cnt modules；Wherein crc_cnt modules completion pair
The counting of crc error codes, and the result of counting is input in CRC-CHECK modules, crc inspection is completed by CRC-CHECK modules
Test, produce corresponding CRC-RESULT and be input in the respective channel position of RAM module.
Further, the E1 synchronous processing modules, including df_fsm modules；Basic frame and multi-frame synchronization are wherein completed,
Then alarm is produced.
Specifically, the processing procedure of the status information is, the E1 synchronous processing modules are read from upper device every time
The E1 data for the E1-DATA data for including port numbers PORT and 1bit are taken, first according to port numbers PORT, reads in RAM module and deposits
The E1-DATA data and status information of the respective channel of storage are into E1 synchronous processing modules；Df_ in E1 synchronous processing modules
Timer modules, crc_cnt modules and df_fsm modules, according to the situation of this data of E1-DATA, to the RAM moulds of reading
The slot count stored in block（TS-CNT）, basic frame count（BF-CNT）, multi-frame counting（MF-CNT）, position is counted（BIT-
CNT）, crc error code meters are handled accordingly, and result of calculation is re-write in the respective channel of RAM module.
Further, multichannel E1 solution frame system also includes warning processing module, the warning processing module with it is described
E1 synchronous processing modules are connected, and the slot count according to produced by the E1 synchronous processing modules（TS-CNT）, basic frame
Count（BF-CNT）, multi-frame counting（MF-CNT）, position count（bit-cnt）, crc error code count results, the corresponding every E1 of output
The alarm signal such as including LOF, LOM, FAS-ERR, CRC-ERR of signal.
Further, the RAM module in the multichannel E1 solutions frame system is output to down frame data are solved by Byte and passage
In the device of position.
Further, the E1 synchronous processing modules read E1 data from fifo module.
Further, the system includes 16 road E1 signals.
Further, when system includes 16 road E1 signals, the FIFO selects 32*5bit, wherein 4bit port numbers+
1bit data；FIFO is selected according to the design requirement of system.
Further, when system includes 16 road E1 signals, the system is using a 81.92MHz high-frequency clock.
Further, the system includes 32 road E1 signals.
Further, when system includes 32 road E1 signals, the FIFO selects 32*6bit, wherein 5bit port numbers+
1bit data；FIFO is selected according to the design requirement of system.
Further, when system includes 32 road E1 signals, the system is adopted using a 163.84MHz high-frequency clocks circulation
The each channel frequence of sample is 2.048 MHz E1 signals.
Further, the system can be additionally used in 1 tunnel, 2 tunnels, 4 tunnels, 8 road E1 signal solution frame systems.
A kind of multichannel E1 solution frame implementation methods based on the system are provided, comprised the following steps：
（1）The E1 synchronous processing modules circulate reading from upper device includes port numbers PORT and 1bit E1-
The E1 data of DATA data；
（2）According to the E1-DATA data and status information of respective channel in port numbers reading RAM module to E1 synchronization process
In module；
（3）The E1-DATA data that E1 synchronous processing modules will be read from RAM module, move into shift-reg modules successively
In, and this 1bit read from upper device E1-DATA data are moved into the last position of shift-reg modules；
（4）E1-DATA data new in shift-reg modules are written in the respective channel of RAM module；
（5）Judge whether the data in the respective channel of RAM module are filled with 8；
（6）If the data of respective channel are filled with 8 in RAM module；It is then that the data in the respective channel of RAM module are defeated
Go out into the next device；The data being now output in the next device include 8bit E1-DATA data and corresponding port numbers.
Further,（3-2）It is shown by the step（2）In status information, E1 synchronous processing modules are according to this E1-
The situation of DATA data carries out respective handling to the status information read；
（4-2）By in the respective channel of the status information write-in RAM module after processing.
Further, the step（3-2）In, the next device according to status information output include LOF, LOM, FAS-ERR,
The alarm signals such as CRC-ERR.
Compared with prior art, beneficial effects of the present invention：E1 solutions frame design of the prior art is believed per E1 all the way
Number a set of solution frame system of correspondence, i.e., need comprising an independent E1 deframers module, so with 16 road E1 per E1 signals all the way
Exemplified by signal, 16 E1 deframer modules are just at least needed, and 32 road E1 signals need at least 32 E1 deframer modules, with
The increase of system E1 signalling channels, required deframer scale is also more and more huger, and required for these huge deframers
Logic unit also greatly increase（These usual deframer functions are all realized that deframer is more by FPGA, required
Logic unit inside FPGA is more）.
A kind of multichannel E1 deframer systems, including E1 synchronous processing modules, RAM module, shift-reg modules, CRC-
CHECK modules；Wherein, the E1 synchronous processing modules are connected with the RAM module；The E1 synchronous processing modules with it is described
Shift-reg modules are connected；The RAM module is connected with the shift-reg modules；The E1 synchronous processing modules are from upper
The E1 data for the E1-DATA data for including port numbers PORT and 1bit are read in circulation in device；First RAM is read according to port numbers
The E1-DATA data and status information of respective channel are into E1 synchronous processing modules in module；E1 synchronous processing modules are according to this
The situation of secondary E1-DATA data carries out respective handling to the status information read；And the status information after processing is write into RAM
In the respective channel of module；The E1-DATA data that E1 synchronous processing modules will be read from RAM module, move into shift-reg successively
In module, and this 1bit read from upper device E1-DATA data are moved into the last position of shift-reg modules；Will
New E1-DATA data are written in the respective channel of RAM module in shift-reg modules；Until the E1-DATA of respective channel
Data are filled with the next device exported after 8.
So only need to an E1 deframer system, so that it may which the E1 solution frames for carrying out multichannel recover, and reassemble into multi-channel E 1 data,
Avoid tradition from being required for an independent deframer per road E1, logic unit needed for E1 deframers is greatlyd save, for based on E1 signals
The bandwidth expansion of communication and communication speed-raising provide highly effective new way, can be applied to the various communication systems based on E1 signals
In system.
Brief description of the drawings：
Fig. 1 is that this multichannel E1 solves frame system structural representation.
Fig. 2 is that this multichannel E1 solves frame system method flow schematic diagram.
Embodiment
With reference to test example and embodiment, the present invention is described in further detail.But this should not be understood
Following embodiment is only limitted to for the scope of above-mentioned theme of the invention, it is all that this is belonged to based on the technology that present invention is realized
The scope of invention.
It is an object of the invention to overcome in the presence of prior art above-mentioned not enough there is provided a kind of multichannel E1 deframers system
System.Multichannel E1 is solved into frame data and is assembled into serial data stream through multiplexer, an E1 deframer is so only needed to, so that it may carry out E1
Solve frame to recover, reassemble into multi-channel E 1 data, it is to avoid tradition is required for an independent deframer per road E1, greatlys save E1 deframers
Required logic unit.
In order to realize foregoing invention purpose, the invention provides following technical scheme：
A kind of multichannel E1 deframer systems, as shown in figure 1, including E1 synchronous processing modules, RAM module, shift-reg moulds
Block, CRC-CHECK modules；Wherein, the E1 synchronous processing modules are connected with the RAM module；The E1 synchronous processing modules
It is connected with the shift-reg modules；The RAM module is connected with the shift-reg modules；
The E1 synchronous processing modules circulate reading from upper device includes port numbers PORT and 1bit E1-DATA numbers
According to E1 data；
At first according to the E1-DATA data and status information of respective channel in port numbers reading RAM module to E1 synchronizations
Manage in module；
E1 synchronous processing modules carry out corresponding position according to the situation of this E1-DATA data to the status information read
Reason；And write the status information after processing in the respective channel of RAM module；
The E1-DATA data that E1 synchronous processing modules will be read from RAM module, are moved into shift-reg modules successively, and
This 1bit read from upper device E1-DATA data are moved into the last position of shift-reg modules；
E1-DATA data new in shift-reg modules are written in the respective channel of RAM module；
Until the E1-DATA data of respective channel are filled with the next device exported after 8.Sent out by E1 synchronous processing modules
Go out to enable signal by all data and port numbers of above-mentioned passage from RAM module is output to corresponding the next device, so
Just complete the solution frame respectively of multi-channel E 1 signal.(in Fig. 1, CLK is sampling clock, and TS-CNT is that slot count, BF-CNT are base
This frame count, MF-CNT are that multi-frame is counted, BIT-CNT is that position is counted；WR-EN is writes enable, and WR-ADDR is write address, RE-EN
To read to enable, RE-ADDR enables for reading).
Further, the status information includes slot count, basic frame count, multi-frame counting, position counting and CRC-
RESULT。
Further, the E1 synchronous processing modules, including df_timer modules, wherein E1 synchronous processing modules are from upper
Read in device after data, slot count is provided for other modules by df_timer modules（TS-CNT）, basic frame count（BF-
CNT）, multi-frame counting（MF-CNT）, position is counted（BIT-CNT）；Thereafter E1 synchronous processing modules by it is described will be upper according to port numbers
State slot count（TS-CNT）, basic frame count（BF-CNT）, multi-frame counting（MF-CNT）, position is counted（BIT-CNT）As a result write
Enter into RAM respective channel.
Further, the E1 synchronous processing modules, including crc_cnt modules；Wherein crc_cnt modules completion pair
The counting of crc error codes, and the result of counting is input in CRC-CHECK modules, crc inspection is completed by CRC-CHECK modules
Test, produce corresponding CRC-RESULT and be input in the respective channel position of RAM module.
Further, the E1 synchronous processing modules, including df_fsm modules；Basic frame and multi-frame synchronization are wherein completed,
Then alarm is produced.
Specifically, the processing procedure of the status information is, the E1 synchronous processing modules are read from upper device every time
The E1 data for the E1-DATA data for including port numbers PORT and 1bit are taken, first according to port numbers PORT, reads in RAM module and deposits
The E1-DATA data and status information of the respective channel of storage are into E1 synchronous processing modules；Df_ in E1 synchronous processing modules
Timer modules, crc_cnt modules and df_fsm modules, according to the situation of this data of E1-DATA, to the RAM moulds of reading
The slot count stored in block（TS-CNT）, basic frame count（BF-CNT）, multi-frame counting（MF-CNT）, position is counted（BIT-
CNT）, crc error code meters are handled accordingly, and result of calculation is re-write in the respective channel of RAM module.
Further, multichannel E1 solution frame system also includes warning processing module, the warning processing module with it is described
E1 synchronous processing modules are connected, and the slot count according to produced by the E1 synchronous processing modules（TS-CNT）, basic frame
Count（BF-CNT）, multi-frame counting（MF-CNT）, position is counted（BIT-CNT）, crc error code count results, the corresponding every E1 of output
The alarm signal such as including LOF, LOM, FAS-ERR, CRC-ERR of signal.
Further, the RAM module in the multichannel E1 solutions frame system is output to down frame data are solved by Byte and passage
In the device of position.
Further, the E1 synchronous processing modules read upper data from fifo module.
Further, the system includes 16 road E1 signals.
Further, when system includes 16 road E1 signals, the FIFO selects 32*5bit, wherein 4bit port numbers+
1bit data；FIFO is selected according to the design requirement of system.
Further, when system includes 16 road E1 signals, the system is using a 81.92MHz high-frequency clock.
Further, the system includes 32 road E1 signals.
Further, when system includes 32 road E1 signals, the FIFO selects 32*6bit, wherein 5bit port numbers+
1bit data；FIFO is selected according to the design requirement of system.
Further, when system includes 32 road E1 signals, the system is adopted using a 163.84MHz high-frequency clocks circulation
The each channel frequence of sample is 2.048 MHz E1 signals.
Further, the system can be additionally used in 1 tunnel, 2 tunnels, 4 tunnels, 8 road E1 signal solution frame systems.
A kind of multichannel E1 solution frame implementation methods based on the system are provided, following steps as shown in Figure 2 are included：
（1）The E1 synchronous processing modules circulate reading from upper device includes port numbers PORT and 1bit E1-
The E1 data of DATA data；
（2）According to the E1-DATA data and status information of respective channel in port numbers reading RAM module to E1 synchronization process
In module；
（3）The E1-DATA data that E1 synchronous processing modules will be read from RAM module, move into shift-reg modules successively
In, and this 1bit read from upper device E1-DATA data are moved into the last position of shift-reg modules；
（4）E1-DATA data new in shift-reg modules are written in the respective channel of RAM module；
（5）Judge whether the data in the respective channel of RAM module are filled with 8；Discontented then return to step（1）；
（6）If the data of respective channel are filled with 8 in RAM module；It is then that the data in the respective channel of RAM module are defeated
Go out into the next device；The data being now output in the next device include 8bit E1-DATA data and corresponding port numbers.
Such as Fig. 2（3-2）It is shown by the step（2）In status information, E1 synchronous processing modules are according to this E1-DATA
The situation of data carries out respective handling to the status information read；（4-2）By the status information write-in RAM module after processing
In respective channel.
Further, the next device includes the alarm letter such as LOF, LOM, FAS-ERR, CRC-ERR according to status information output
Number, such as Fig. 2（3-3）It is shown.
In a word, E1 solutions frame design of the prior art is all per a set of solution frame system of the correspondence of E1 signals all the way, i.e., per all the way
E1 signals need comprising independent E1 deframers module, so by taking 16 road E1 signals as an example, just at least need 16 E1 solutions
Frame device module, and 32 road E1 signals need at least 32 E1 deframer modules, it is required with the increase of system E1 signalling channels
Deframer scale it is also more and more huger, and the logic unit required for these huge deframers also greatly increases（Generally
These deframer functions are all realized that deframer is more by FPGA, and the logic unit inside required FPGA is more）.
A kind of multichannel E1 deframer systems, including E1 synchronous processing modules, RAM module, shift-reg modules, CRC-
CHECK modules；Wherein, the E1 synchronous processing modules are connected with the RAM module；The E1 synchronous processing modules with it is described
Shift-reg modules are connected；The RAM module is connected with the shift-reg modules；The E1 synchronous processing modules are from upper
The E1 data for the E1-DATA data for including port numbers PORT and 1bit are read in circulation in device；First RAM is read according to port numbers
The E1-DATA data and status information of respective channel are into E1 synchronous processing modules in module；E1 synchronous processing modules are according to this
The situation of secondary E1-DATA data carries out respective handling to the status information read；And the status information after processing is write into RAM
In the respective channel of module；The E1-DATA data that E1 synchronous processing modules will be read from RAM module, move into shift-reg successively
In module, and this 1bit read from upper device E1-DATA data are moved into the last position of shift-reg modules；Will
New E1-DATA data are written in the respective channel of RAM module in shift-reg modules；Until the E1-DATA of respective channel
Data are filled with the next device exported after 8.
So only need to an E1 deframer system, so that it may which the E1 solution frames for carrying out multichannel recover, and reassemble into multi-channel E 1 data,
Avoid tradition from being required for an independent deframer per road E1, logic unit needed for E1 deframers is greatlyd save, for based on E1 signals
The bandwidth expansion of communication and communication speed-raising provide highly effective new way, can be applied to the various communication systems based on E1 signals
In system.
Claims (10)
1. a kind of multichannel E1 deframer systems, it is characterized in that, including E1 synchronous processing modules, RAM module, shift-reg modules
With CRC-CHECK modules；Wherein, the E1 synchronous processing modules are connected with the RAM module；The E1 synchronous processing modules with
The shift-reg modules are connected；The RAM module is connected with the shift-reg modules；
The E1 synchronous processing modules circulate reading from upper device includes the E1 data of port numbers and 1 E1-DATA data；
The E1-DATA data and status information of respective channel in RAM module are read into E1 synchronous processing modules according to port numbers first；
The situation for the E1-DATA data that E1 synchronous processing modules are read according to this from RAM module is believed the state read
Breath carries out respective handling；And write the status information after processing in the respective channel of RAM module；
The E1-DATA data that E1 synchronous processing modules will be read from RAM module, are moved into shift-reg modules successively, and incite somebody to action this
The secondary E1-DATA data of 1 read from upper device move into the last position of shift-reg modules；
E1-DATA data new in shift-reg modules are written in the respective channel of RAM module；
It is output to until the E1-DATA data of respective channel are filled with after 8 in the next device.
2. a kind of multichannel E1 deframer systems as claimed in claim 1, it is characterized in that, the status information includes time slot meter
Several, basic frame count, multi-frame are counted, position is counted and CRC-RESULT.
3. a kind of multichannel E1 deframer systems as claimed in claim 2, it is characterized in that, the E1 synchronous processing modules include
Df_timer modules, the df_timer modules carry out slot count, basic frame count, and multi-frame is counted and position is counted.
4. a kind of multichannel E1 deframer systems as claimed in claim 3, it is characterized in that, the E1 synchronous processing modules include
Crc_cnt modules, the crc_cnt modules complete the counting to crc error codes.
5. a kind of multichannel E1 deframer systems as claimed in claim 4, it is characterized in that, the E1 synchronous processing modules include
Df_fsm modules, for completing basic frame and multi-frame synchronization, then produce alarm.
6. a kind of multichannel E1 deframer systems as claimed in claim 5, it is characterized in that, the system includes alarming processing mould
Block, the warning processing module is connected with the E1 synchronous processing modules；Believed according to the output of the situation of status information per E1 all the way
Number LOF LOFs, LOM Loss Of Multiframes, FAS-ERR frame alignment signals mistake and CRC-ERR cyclic redundancy check errors accuse
It is alert.
7. a kind of multichannel E1 deframer systems as claimed in claim 6, it is characterized in that, the E1 synchronous processing modules pass through institute
The fifo module for stating system reads upper data from upper device.
8. a kind of multichannel E1 deframer systems as described in one of claim 1 to 7, it is characterized in that, including 16 road E1 signals；Choosing
With the FIFO of 5, wherein+1 data of bit port No. 4.
9. a kind of multichannel E1 deframer systems as described in one of claim 1 to 7, it is characterized in that, including 32 road E1 signals；Choosing
With the FIFO of 6, wherein+1 data of bit port No. 5.
10. a kind of multichannel E1 deframer systems as claimed in claim 9, it is characterized in that, the RAM is according to the ports of E1 signals
Number is chosen.
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| CN204244255U (en) * | 2014-12-12 | 2015-04-01 | 成都朗锐芯科技发展有限公司 | A kind of multichannel E1 deframer system |
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| CN103490841A (en) * | 2013-09-25 | 2014-01-01 | 科大智能（合肥）科技有限公司 | Clock recovery method based on distributed frame header in multi-path E1 multiplexing system |
| CN204244255U (en) * | 2014-12-12 | 2015-04-01 | 成都朗锐芯科技发展有限公司 | A kind of multichannel E1 deframer system |
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