CN104468016B - A kind of multichannel E1 solves frame implementation method - Google Patents
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Abstract
The present invention relates to a kind of communications field, more particularly to a kind of multichannel E1 solves frame implementation method, including E1 synchronous processing module, RAM module, shift reg module, CRC CHECK module；Wherein described E1 synchronous processing module circulates reading data from upper device, the E1 DATA data of respective channel are read according to port numbers from RAM module, move in shift reg module successively, and the E1 DATA data of this 1bit read from upper device are moved into the last position of shift reg module；New E1 DATA data are written in the respective channel of RAM module；Export after being filled with 8.Only need to an E1 deframer, so that it may which the E1 solution frame for carrying out multichannel recovers, and reassembles into multi-channel E 1 data, it is to avoid tradition is required for the problem of independent deframer per road E1, greatlys save logical block needed for E1 deframer.
Description
Technical field
The present invention relates to a kind of communications field, more particularly to a kind of multichannel E1 solution frame implementation method.
Background technology
In data communication field, it is that most basic frame is processed that E1 signal framing conciliates frame, according to G.704, per basic frame by
32 channel time slots（ts0-ts31）Composition, each channel time slot are made up of 8bit code, and basic frame frame frequency is 8000 frames/second, i.e.,
2.048Mbit/s data carry out framing transmission by fixing frame structure, receive frame solution frame.
According to《E1 becomes/design of deframer》（Hunan University's physics and microelectronics science institute, Li Pengcheng, Yan Yonghong are handsome
Jin Xiao, Guo Youhong）E1 becomes/and deframer includes tri- modules of e1_framer, e1_deframer, e1pi, e1_framer module
Data composition to sending meets the E1 frame structure that G.704 agreement specifies；E1_deframer module is to the data that receive
Carry out solution frame, i.e. the carrying out to frame part to separate and be further explained；E1pi module is responsible for transmitting data to line side together
When from circuit receiving data, include among these data are carried out detecting, recover clock from data（Debit to）, carry out code
The conversion of type（Hdb3 encoding and decoding）, coded violation, CV is checked.
E1 becomes/and deframer describes single channel E1 framing solution frame method and process in greater detail, but in actual applications, E1 is received and dispatched
Road is often relatively more, and we commonly use 16 road E1 transmitting-receiving, if adopting single channel separate processing approach, it would be desirable to a large amount of logical resources,
And prior art, this is such solution frame mode, is to save logical resource, and the present invention is using multichannel E1 solution frame data through multiplexer
Serial data stream is assembled into, so only needs to an E1 deframer, so that it may carry out E1 solution frame and recover, multi-channel E 1 data is reassembled into,
Avoid tradition from an independent deframer being required for per road E1, thus greatly save logical block needed for E1 deframer.
Content of the invention
It is an object of the invention to the above-mentioned deficiency in the presence of overcoming prior art, provides a kind of multichannel E1 deframer system
System.Multichannel E1 solution frame data are assembled into serial data stream through multiplexer, so only need to an E1 deframer, so that it may carry out E1
Solution frame recovers, and reassembles into multi-channel E 1 data, it is to avoid tradition is required for an independent deframer per road E1, greatlys save E1 deframer
Required logical block.
In order to realize foregoing invention purpose, the invention provides technical scheme below：
A kind of multichannel E1 deframer system, including E1 synchronous processing module, RAM module, shift-reg module, CRC-
CHECK module；Wherein, the E1 synchronous processing module is connected with the RAM module；The E1 synchronous processing module with described
Shift-reg module is connected；The RAM module is connected with the shift-reg module；
The E1 synchronous processing module is circulated from upper device and reads the E1-DATA number for including port numbers PORT and 1bit
According to E1 data；
First according to the E1-DATA data of respective channel in port numbers reading RAM module and status information at E1 synchronization
In reason module；
E1 synchronous processing module carries out corresponding position according to the situation of this E1-DATA data to the status information for being read
Reason；And by the respective channel of the status information write RAM module after process；
The E1-DATA data read from RAM module are moved in shift-reg module by E1 synchronous processing module successively, and
The E1-DATA data of this 1bit read from upper device are moved into the last position of shift-reg module；
New E1-DATA data in shift-reg module are written in the respective channel of RAM module；
Until the E1-DATA data of respective channel are filled with the next device exported after 8.Sent out by E1 synchronous processing module
Go out to enable signal to export in corresponding bottom device, so all data of above-mentioned passage and port numbers from RAM module
The respectively solution frame of multi-channel E 1 signal is just completed.
Further, the status information includes that slot count, basic frame count, multi-frame are counted, position counts and CRC-
RESULT.
Further, the E1 synchronous processing module, including df_timer module, wherein E1 synchronous processing module is from upper
After data being read in device, slot count is provided by df_timer module for other modules（TS-CNT）, basic frame count（BF-
CNT）, multi-frame counting（MF-CNT）And position counts（bit-cnt）；Thereafter E1 synchronous processing module, by described according to port numbers
By above-mentioned slot count（TS-CNT）, basic frame count（BF-CNT）, multi-frame counting（MF-CNT）And position counts（BIT-CNT）
Result be written in the corresponding passage of RAM.
Further, the E1 synchronous processing module, including crc_cnt module；Wherein crc_cnt module completes right
The counting of crc error code, and the result of counting is input to the inspection for being completed crc in CRC-CHECK module by CRC-CHECK module
Test, produce corresponding CRC-RESULT and be input in the respective channel position of RAM module.
Further, the E1 synchronous processing module, including df_fsm module；Basic frame and multi-frame synchronization are wherein completed,
Then alarm is produced.
Specifically, the processing procedure of the status information is, the E1 synchronous processing module, reads every time from upper device
The E1 data of the E1-DATA data for including port numbers PORT and 1bit are taken, first according to port numbers PORT, is read in RAM module and deposits
The E1-DATA data and status information of the respective channel of storage are in E1 synchronous processing module；Df_ in E1 synchronous processing module
Timer module, crc_cnt module and df_fsm module, according to the situation of this secondary data of E1-DATA, to the RAM mould for reading
The slot count stored in block（TS-CNT）, basic frame count（BF-CNT）, multi-frame counting（MF-CNT）, position counts（BIT-
CNT）, crc error code meter is processed accordingly, and result of calculation is re-write in the respective channel of RAM module.
Further, multichannel E1 solution frame system also includes warning processing module, the warning processing module with described
E1 synchronous processing module is connected, and the slot count according to produced by the E1 synchronous processing module（TS-CNT）, basic frame
Count（BF-CNT）, multi-frame counting（MF-CNT）, position count（bit-cnt）, crc error code count results, export accordingly every E1
The alarm signal such as including LOF, LOM, FAS-ERR, CRC-ERR of signal.
Further, the RAM module in the multichannel E1 solution frame system will solve frame data and arrive down by Byte and passage output
In the device of position.
Further, the E1 synchronous processing module reads E1 data from fifo module.
Further, the system includes 16 road E1 signals.
Further, when system includes 16 road E1 signal, the FIFO selects 32*5bit, wherein 4bit port numbers+
1bit data；FIFO is selected according to the design requirement of system.
Further, when system includes 16 road E1 signal, the system adopts a 81.92MHz high-frequency clock.
Further, the system includes 32 road E1 signals.
Further, when system includes 32 road E1 signal, the FIFO selects 32*6bit, wherein 5bit port numbers+
1bit data；FIFO is selected according to the design requirement of system.
Further, when system includes 32 road E1 signals, the system is adopted using a 163.84MHz high-frequency clock circulation
Each channel frequence of sample is the E1 signal of 2.048 MHz.
Further, the system can be additionally used in 2 tunnels, 4 tunnels, in 8 road E1 signal solution frame systems.
A kind of multichannel E1 based on the system is provided frame implementation method is solved, comprise the steps of：
（1）The E1 synchronous processing module is circulated from upper device and reads the E1- for including port numbers PORT and 1bit
The E1 data of DATA data；
（2）According to the E1-DATA data of respective channel and status information in port numbers reading RAM module to E1 synchronization process
In module；
（3）The E1-DATA data read from RAM module are moved into shift-reg module by E1 synchronous processing module successively
In, and the E1-DATA data of this 1bit read from upper device are moved into the last position of shift-reg module；
（4）New E1-DATA data in shift-reg module are written in the respective channel of RAM module；
（5）Judge whether the data in the respective channel of RAM module are filled with 8；
（6）If the data of respective channel are filled with 8 in RAM module；Then will be defeated for the data in the respective channel of RAM module
Go out in the next device；Now exporting the data in the next device includes the E1-DATA data of 8bit and corresponding port numbers.
Further,（3-2）Shown by the step（2）In status information, E1 synchronous processing module is according to this E1-
The situation of DATA data carries out respective handling to the status information for being read；
（4-2）By in the respective channel of the status information write RAM module after process.
Further, the step（3-2）In, the next device according to status information output include LOF, LOM, FAS-ERR,
The alarm signals such as CRC-ERR.
Compared with prior art, beneficial effects of the present invention：E1 solution frame design of the prior art is all each road E1 letter
Number a set of solution frame system of correspondence, i.e., the E1 signal demand on each road include an independent E1 deframer module, so with 16 road E1
As a example by signal, 16 E1 deframer modules are just at least needed, and 32 road E1 at least 32 E1 deframer modules of signal demand, with
The increase of system E1 signalling channel, required deframer scale are also more and more huger, and required for these huge deframers
Logical block also greatly increase（Generally these deframer functions are all realized by FPGA, and deframer is more, required
Logical block inside FPGA is more）.
A kind of multichannel E1 deframer system, including E1 synchronous processing module, RAM module, shift-reg module, CRC-
CHECK module；Wherein, the E1 synchronous processing module is connected with the RAM module；The E1 synchronous processing module with described
Shift-reg module is connected；The RAM module is connected with the shift-reg module；The E1 synchronous processing module is from upper
In device, the E1 data of the E1-DATA data for including port numbers PORT and 1bit are read in circulation；RAM is read first according to port numbers
In module, the E1-DATA data of respective channel and status information are in E1 synchronous processing module；E1 synchronous processing module is according to this
The situation of secondary E1-DATA data carries out respective handling to the status information for being read；And the status information after process is write RAM
In the respective channel of module；The E1-DATA data read from RAM module are moved into shift-reg by E1 synchronous processing module successively
In module, and the E1-DATA data of this 1bit read from upper device are moved into the last position of shift-reg module；Will
New E1-DATA data in shift-reg module are written in the respective channel of RAM module；E1-DATA until respective channel
Data are filled with the next device exported after 8.
An E1 deframer system is so only needed to, so that it may which the E1 solution frame for carrying out multichannel recovers, and reassembles into multi-channel E 1 data,
Avoid tradition from being required for an independent deframer per road E1, greatly save logical block needed for E1 deframer, be based on E1 signal
The bandwidth expansion of communication and communication speed-raising provide highly effective new way, can be applicable to the various communication system based on E1 signal
In system.
Description of the drawings：
Fig. 1 is that this multichannel E1 solves frame system structural representation.
Fig. 2 is that this multichannel E1 solves frame system method flow schematic diagram.
Specific embodiment
With reference to test example and specific embodiment, the present invention is described in further detail.But this should not be understood
Below example is only limitted to for the scope of the above-mentioned theme of the present invention, all technology that is realized based on present invention belong to this
The scope of invention.
It is an object of the invention to the above-mentioned deficiency in the presence of overcoming prior art, provides a kind of multichannel E1 deframer system
System.Multichannel E1 solution frame data are assembled into serial data stream through multiplexer, so only need to an E1 deframer, so that it may carry out E1
Solution frame recovers, and reassembles into multi-channel E 1 data, it is to avoid tradition is required for an independent deframer per road E1, greatlys save E1 deframer
Required logical block.
In order to realize foregoing invention purpose, the invention provides technical scheme below：
A kind of multichannel E1 deframer system, as shown in figure 1, including E1 synchronous processing module, RAM module, shift-reg mould
Block, CRC-CHECK module；Wherein, the E1 synchronous processing module is connected with the RAM module；The E1 synchronous processing module
It is connected with the shift-reg module；The RAM module is connected with the shift-reg module；
The E1 synchronous processing module is circulated from upper device and reads the E1-DATA number for including port numbers PORT and 1bit
According to E1 data；
First according to the E1-DATA data of respective channel in port numbers reading RAM module and status information at E1 synchronization
In reason module；
E1 synchronous processing module carries out corresponding position according to the situation of this E1-DATA data to the status information for being read
Reason；And by the respective channel of the status information write RAM module after process；
The E1-DATA data read from RAM module are moved in shift-reg module by E1 synchronous processing module successively, and
The E1-DATA data of this 1bit read from upper device are moved into the last position of shift-reg module；
New E1-DATA data in shift-reg module are written in the respective channel of RAM module；
Until the E1-DATA data of respective channel are filled with the next device exported after 8.Sent out by E1 synchronous processing module
Go out to enable signal to export in corresponding bottom device, so all data of above-mentioned passage and port numbers from RAM module
The respectively solution frame of multi-channel E 1 signal is just completed.(in Fig. 1, CLK is sampling clock, and TS-CNT is slot count, BF-CNT is base
This frame count, MF-CNT are counted for multi-frame, BIT-CNT is counted for position；For writing enable, WR-ADDR is write address to WR-EN, RE-EN
For reading to enable, RE-ADDR is for reading to enable).
Further, the status information includes that slot count, basic frame count, multi-frame are counted, position counts and CRC-
RESULT.
Further, the E1 synchronous processing module, including df_timer module, wherein E1 synchronous processing module is from upper
After data being read in device, slot count is provided by df_timer module for other modules（TS-CNT）, basic frame count（BF-
CNT）, multi-frame counting（MF-CNT）, position counts（BIT-CNT）；Thereafter E1 synchronous processing module by described will be upper according to port numbers
State slot count（TS-CNT）, basic frame count（BF-CNT）, multi-frame counting（MF-CNT）, position counts（BIT-CNT）As a result write
Enter in the respective channel of RAM.
Further, the E1 synchronous processing module, including crc_cnt module；Wherein crc_cnt module completes right
The counting of crc error code, and the result of counting is input to the inspection for being completed crc in CRC-CHECK module by CRC-CHECK module
Test, produce corresponding CRC-RESULT and be input in the respective channel position of RAM module.
Further, the E1 synchronous processing module, including df_fsm module；Basic frame and multi-frame synchronization are wherein completed,
Then alarm is produced.
Specifically, the processing procedure of the status information is, the E1 synchronous processing module, reads every time from upper device
The E1 data of the E1-DATA data for including port numbers PORT and 1bit are taken, first according to port numbers PORT, is read in RAM module and deposits
The E1-DATA data and status information of the respective channel of storage are in E1 synchronous processing module；Df_ in E1 synchronous processing module
Timer module, crc_cnt module and df_fsm module, according to the situation of this secondary data of E1-DATA, to the RAM mould for reading
The slot count stored in block（TS-CNT）, basic frame count（BF-CNT）, multi-frame counting（MF-CNT）, position counts（BIT-
CNT）, crc error code meter is processed accordingly, and result of calculation is re-write in the respective channel of RAM module.
Further, multichannel E1 solution frame system also includes warning processing module, the warning processing module with described
E1 synchronous processing module is connected, and the slot count according to produced by the E1 synchronous processing module（TS-CNT）, basic frame
Count（BF-CNT）, multi-frame counting（MF-CNT）, position counts（BIT-CNT）, crc error code count results, export accordingly every E1
The alarm signal such as including LOF, LOM, FAS-ERR, CRC-ERR of signal.
Further, the RAM module in the multichannel E1 solution frame system will solve frame data and arrive down by Byte and passage output
In the device of position.
Further, the E1 synchronous processing module reads upper data from fifo module.
Further, the system includes 16 road E1 signals.
Further, when system includes 16 road E1 signal, the FIFO selects 32*5bit, wherein 4bit port numbers+
1bit data；FIFO is selected according to the design requirement of system.
Further, when system includes 16 road E1 signal, the system adopts a 81.92MHz high-frequency clock.
Further, the system includes 32 road E1 signals.
Further, when system includes 32 road E1 signal, the FIFO selects 32*6bit, wherein 5bit port numbers+
1bit data；FIFO is selected according to the design requirement of system.
Further, when system includes 32 road E1 signals, the system is adopted using a 163.84MHz high-frequency clock circulation
Each channel frequence of sample is the E1 signal of 2.048 MHz.
Further, the system can be additionally used in 2 tunnels, 4 tunnels, in 8 road E1 signal solution frame systems.
A kind of multichannel E1 based on the system is provided frame implementation method is solved, comprising following steps as shown in Figure 2：
（1）The E1 synchronous processing module is circulated from upper device and reads the E1- for including port numbers PORT and 1bit
The E1 data of DATA data；
（2）According to the E1-DATA data of respective channel and status information in port numbers reading RAM module to E1 synchronization process
In module；
（3）The E1-DATA data read from RAM module are moved into shift-reg module by E1 synchronous processing module successively
In, and the E1-DATA data of this 1bit read from upper device are moved into the last position of shift-reg module；
（4）New E1-DATA data in shift-reg module are written in the respective channel of RAM module；
（5）Judge whether the data in the respective channel of RAM module are filled with 8；
（6）If the data of respective channel are filled with 8 in RAM module；Then will be defeated for the data in the respective channel of RAM module
Go out in the next device；Now exporting the data in the next device includes the E1-DATA data of 8bit and corresponding port numbers.
As Fig. 2（3-2）Shown by the step（2）In status information, E1 synchronous processing module is according to this E1-DATA
The situation of data carries out respective handling to the status information for being read；（4-2）By the status information write RAM module after process
In respective channel.
Further, the next device includes the alarm letter such as LOF, LOM, FAS-ERR, CRC-ERR according to status information output
Number, such as Fig. 2（3-3）Shown.
In a word, E1 solution frame design of the prior art is all that each road E1 signal corresponds to a set of solution frame system, i.e., each road
E1 signal demand include an independent E1 deframer module, so by taking 16 road E1 signals as an example, just at least need 16 E1 solution
Frame device module, and 32 road E1 at least 32 E1 deframer modules of signal demand, with the increase of system E1 signalling channel, required
Deframer scale also more and more huger, and these logical blocks required for huge deframer also greatly increase（Generally
These deframer functions are all realized by FPGA, and deframer is more, and the logical block inside required FPGA is more）.
A kind of multichannel E1 deframer system, including E1 synchronous processing module, RAM module, shift-reg module, CRC-
CHECK module；Wherein, the E1 synchronous processing module is connected with the RAM module；The E1 synchronous processing module with described
Shift-reg module is connected；The RAM module is connected with the shift-reg module；The E1 synchronous processing module is from upper
In device, the E1 data of the E1-DATA data for including port numbers PORT and 1bit are read in circulation；RAM is read first according to port numbers
In module, the E1-DATA data of respective channel and status information are in E1 synchronous processing module；E1 synchronous processing module is according to this
The situation of secondary E1-DATA data carries out respective handling to the status information for being read；And the status information after process is write RAM
In the respective channel of module；The E1-DATA data read from RAM module are moved into shift-reg by E1 synchronous processing module successively
In module, and the E1-DATA data of this 1bit read from upper device are moved into the last position of shift-reg module；Will
New E1-DATA data in shift-reg module are written in the respective channel of RAM module；E1-DATA until respective channel
Data are filled with the next device exported after 8.
An E1 deframer system is so only needed to, so that it may which the E1 solution frame for carrying out multichannel recovers, and reassembles into multi-channel E 1 data,
Avoid tradition from being required for an independent deframer per road E1, greatly save logical block needed for E1 deframer, be based on E1 signal
The bandwidth expansion of communication and communication speed-raising provide highly effective new way, can be applicable to the various communication system based on E1 signal
In system.
Claims (10)
1. a kind of multichannel E1 solves frame implementation method, it is characterized in that, comprises the steps of：
(1) the E1 synchronous processing module is circulated from upper device and reads the E1 number for including port numbers and 1 E1-DATA data
According to；
(2) according to the E1-DATA data of respective channel and status information in port numbers reading RAM module to E1 synchronous processing module
In；
(3) the E1-DATA data read from RAM module are moved in shift-reg module by E1 synchronous processing module successively, and
The E1-DATA data of this 1bit read from upper device are moved into the last position of shift-reg module；
(4) new E1-DATA data in shift-reg module are written in the respective channel of RAM module；
(5) judge whether the data in the respective channel of RAM module are filled with 8；
(6) if the data of respective channel are filled with 8 in RAM module；Then the data output in the respective channel of RAM module is arrived
In the next device.
2. a kind of multichannel E1 solves frame implementation method as claimed in claim 1, it is characterized in that, the state of step (2)
Information includes that slot count, basic frame count, multi-frame are counted, position counts and CRC-RESULT.
3. a kind of multichannel E1 solves frame implementation method as claimed in claim 2, it is characterized in that, in step (2), at E1 synchronization
Reason module carries out respective handling according to the situation of this E1-DATA data to the status information for being read；And by the shape after process
In the respective channel of state information write RAM module.
4. a kind of multichannel E1 solves frame implementation method as claimed in claim 3, it is characterized in that, E1 synchronous processing module, according to shape
The situation of state information exports LOF, LOM, FAS-ERR and CRC-ERR alarm of each road E1.
5. a kind of multichannel E1 solves frame implementation method as claimed in claim 4, it is characterized in that, press in step (6) Byte with
Passage exports the solution frame data of RAM module in the next device.
6. a kind of multichannel E1 solves frame implementation method as claimed in claim 5, it is characterized in that, the E1 synchronous processing module from
Upper data are read in fifo module.
7. a kind of multichannel E1 solution frame implementation method as described in one of claim 1 to 6, is characterized in that, for 16 road E1 signals
Solution frame；From the FIFO of 5, wherein 4bit port numbers+1bit data.
8. a kind of multichannel E1 solution frame implementation method as described in one of claim 1 to 6, is characterized in that, for 32 road E1 signals
Solution frame；From the FIFO of 6, wherein 5bit port numbers+1bit data.
9. a kind of multichannel E1 solution frame implementation method as described in one of claim 1 to 6, is characterized in that, for 2 tunnels, 4 tunnels or 8
In the E1 signal solution frame system of road.
10. a kind of multichannel E1 solves frame implementation method as claimed in claim 9, it is characterized in that, the RAM is according to the end of E1 signal
Mouth number is chosen.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201699708U (en) * | 2010-02-24 | 2011-01-05 | 厦门福信光电集成有限公司 | E1 optical modem |
| WO2013125621A1 (en) * | 2012-02-22 | 2013-08-29 | 日本電信電話株式会社 | Multi-lane transmission device and multi-lane transmission method |
| CN103595689A (en) * | 2012-08-13 | 2014-02-19 | 成都思迈科技发展有限责任公司 | Multi-interface to E1 protocol converter |
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| US8274961B2 (en) * | 2003-10-24 | 2012-09-25 | Sony Corporation | Apparatus and associated methodology of adjusting a RTS/CTS transmission protocol |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201699708U (en) * | 2010-02-24 | 2011-01-05 | 厦门福信光电集成有限公司 | E1 optical modem |
| WO2013125621A1 (en) * | 2012-02-22 | 2013-08-29 | 日本電信電話株式会社 | Multi-lane transmission device and multi-lane transmission method |
| CN103595689A (en) * | 2012-08-13 | 2014-02-19 | 成都思迈科技发展有限责任公司 | Multi-interface to E1 protocol converter |
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