CN101146102B - HDLC data uplink and downlink method and communication device in RRU network - Google Patents
HDLC data uplink and downlink method and communication device in RRU network Download PDFInfo
- Publication number
- CN101146102B CN101146102B CN2007101239382A CN200710123938A CN101146102B CN 101146102 B CN101146102 B CN 101146102B CN 2007101239382 A CN2007101239382 A CN 2007101239382A CN 200710123938 A CN200710123938 A CN 200710123938A CN 101146102 B CN101146102 B CN 101146102B
- Authority
- CN
- China
- Prior art keywords
- data
- buffer unit
- rru
- frame
- hdlc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000004891 communication Methods 0.000 title claims abstract description 27
- 230000005540 biological transmission Effects 0.000 claims abstract description 12
- 238000011144 upstream manufacturing Methods 0.000 claims abstract description 9
- 230000008569 process Effects 0.000 claims description 30
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 238000013461 design Methods 0.000 claims description 13
- 239000000284 extract Substances 0.000 claims description 13
- 230000004044 response Effects 0.000 claims description 9
- 238000001514 detection method Methods 0.000 claims description 8
- 238000003780 insertion Methods 0.000 claims description 7
- 230000037431 insertion Effects 0.000 claims description 7
- 238000012217 deletion Methods 0.000 claims description 3
- 230000037430 deletion Effects 0.000 claims description 3
- 238000012360 testing method Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 238000012856 packing Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 230000006855 networking Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000005039 memory span Effects 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Images
Abstract
The invention discloses a HDLC data downstream and upstream method and a communication device in a RRU network. The data downstream method includes: FPGA receives data frames, and detects whether the data frames are corresponding level data or next level data, according to the data frames address information, after determining the data frames contain valid data; if the data frames are the corresponding level data, perform decoding and CRC examination, store in a cache unit and notify CPU to read out the corresponding level data in the cache unit; if the data frames are the next level data, send to next level RRU. The invention also provides the data upstream method and the data downstream and upstream communication device. The invention adopts FPGA, implements separated processing to the downstream or the upstream corresponding level data and non corresponding level data, reduces CPU work load and can adopt low speed CPU with cost reduction. If the CPU on the corresponding level breaks down, the transmission of the next level data will not be influenced. The invention improves data transmission stability.
Description
[technical field]
The present invention relates to communication technique field, relate in particular to the middle-and-high-ranking data link of remote radio unit (RRU) (RRU) network control (HDLC) data downstream, up method and communication device.
[background technology]
High-Level Data Link Control (HDLC) is a kind of host-host protocol of communication field.In remote radio unit (RRU) (RRU) network system, the HDLC transfer of data no longer is simple ad hoc mode, need carry out the multiple connection and the tap of HDLC frame according to network topology structure and RRU address information.As shown in Figure 1, in present a kind of RRU network system that adopts the chain networking pattern, be to the multiple connection and the tap mode of HDLC frame:
For descending HDLC link, RRU0 at first deciphers from the light mouth 0 descending HDLC data of reception and to it, from decoding data, extract HDLC data at the corresponding levels according to RRU at the corresponding levels address then and be sent to signaling receiver module at the corresponding levels, simultaneously to being sent to RRU1 by light mouth 1 after the non-HDLC digital coding at the corresponding levels, thereby finish the tap of HDLC frame;
For up HDLC link, RRU0 receives HDLC data that back level RRU sends here and it is deciphered from light mouth 1, then itself and the up HDLC data that produce at the corresponding levels are carried out time division multiplexing, to data encode the back be sent to base band resource pool (BBU) by light mouth 0, thereby finish the multiple connection of HDLC frame.
In said system, because HDLC chip itself can not identification address, generally carry out tap and multiple connection by CPU, so take more cpu resource, and in the RRU system, the HDLC link rate is 480～1920 kilobits/second, and general CPU can't finish such high speed processing, generally need to adopt high-speed CPU, cost is very high.
Secondly, because the data of at the corresponding levels and the non-corresponding levels all are to handle by CPU is unified, as long as the cpu fault of one-level will cause transmission to be interrupted.
Once more, the data inside chips memory span is limited, has only not multibyte push-up storage (FIFO) available usually, when needs enlarge the capacity of metadata cache, can only asic chip external memorizer or other circuit more not only be raised the cost, and increase the complexity of system.
[summary of the invention]
Goal of the invention of the present invention provides HDLC data downstream in the RRU network, up method and communication device, reduces cost, improves the purpose of data communication stability to reach.
To achieve the above object of the invention, the present invention proposes following technical scheme:
The method of HDLC data downstream in a kind of RRU network comprises:
The FPGA receiving data frames, judge that described Frame contains valid data after, detecting this Frame according to the address information of described Frame is data at the corresponding levels or back level data;
If data at the corresponding levels, then decipher and CRC check, and deposit buffer unit in, when the data number of storing in the described buffer unit greater than the threshold value of setting or when time of interrupting during greater than the threshold value set apart from last time, send interrupt signal and notify CPU to read data at the corresponding levels in the buffer unit;
If back level data then are sent to back level RRU.
Wherein, described testing process is specially:
Frame to described reception is deciphered, and extract the address information of this Frame and compare with the address of RRU at the corresponding levels, if address unanimity then this Frame is data at the corresponding levels, otherwise be back level data.
Wherein, described detection is after the data at the corresponding levels, specifically comprises:
Data at the corresponding levels are carried out the delay compensation of address detected process;
Data behind the delay compensation are carried out serial/parallel conversion, CRC check, inserted frame head and the postamble set, deposit buffer unit in;
Send the data that interrupt signal notice CPU reads described buffer unit.
Wherein, in the process of described insertion frame head and postamble,, then after the sequence of these data, insert recognition sequence if the sequence that contains in the frame head of the sequence in the described data and insertion or the postamble is identical;
When CPU response interrupts reading above-mentioned data, with the recognition sequence deletion of inserting.
Wherein, described detection is back level data, and the detailed process that is sent to back level RRU comprises:
Level data in back are deciphered delay compensation with the address detected process, when detecting, be sent to back level RRU, otherwise send flag sequence that sequencer generates to back level RRU to back level data.
The method of HDLC data uplink in a kind of RRU network comprises:
FPGA produces written allowance signal, CPU inquires about this signal and effectively writes Frame to first buffer unit of described FPGA in the back, FPGA reading of data and carry out CRC check, parallel/serial conversion, coding from described first buffer unit deposits the data behind the coding in second buffer unit;
The Frame that receives back level RRU generation carries out payload and extracts, and deposits the 3rd buffer unit in;
Sequence generator generates the flag sequence of Frame;
Send the data at the corresponding levels of described second buffer unit, the back level data of the 3rd buffer unit or the flag sequence of sequence generator by up link.
Wherein, the detailed process of said write Frame is:
The capacity of described first buffer unit and second buffer unit is according to the maximum length design of Frame, and CPU is disposable to write first buffer unit with Frame.
Wherein, the detailed process of described transmission is:
Send after the back level data of described the 3rd buffer unit, send the data at the corresponding levels of second buffer unit, when second buffer unit and the 3rd buffer unit free of data, send the flag sequence of sequence generator.
The communication device of HDLC data downstream in a kind of RRU network, this device adopt FPGA to design, and comprising:
The address detected unit, the address information that is used for the Frame that will receive compares with the address of RRU at the corresponding levels, and detecting this Frame is data at the corresponding levels or back grade data;
Data downstream at the corresponding levels unit, be used for data at the corresponding levels are deciphered and CRC check, and deposit buffer unit in, when the data number of storing in the described buffer unit greater than the threshold value of setting or when time of interrupting during greater than the threshold value set apart from last time, send interrupt signal and notify CPU to read data at the corresponding levels in the buffer unit;
Back level data downstream units is used for back level data are sent to back level RRU.
Wherein, described data downstream at the corresponding levels unit comprises:
Decoding unit is used for data at the corresponding levels are deciphered;
Time delay at the corresponding levels unit is used for the data at the corresponding levels after the decoding are carried out the delay compensation of address detected process;
Packaged unit is used for the data behind the delay compensation being carried out serial/parallel conversion, CRC check, inserting frame head and the postamble set;
Buffer unit is used to store the data that described packaged unit sends;
Interrupt location is used for sending interrupt signal to CPU, and notice CPU reads the data of described buffer unit.
Wherein, a described back grade data downstream units comprises:
Back level time delay unit is used for back level data are deciphered delay compensation with the address detected process, and sends to MUX;
Sequencer is used to generate flag sequence;
MUX is used for when described address detected unit detects current data for back level data, and the back level data that will carry out behind the delay compensation send to the RRU of subordinate, otherwise send the flag sequence that described sequencer generates.
The communication device of HDLC data uplink in a kind of RRU network, this device adopt FPGA to design, and comprising:
Data uplink at the corresponding levels unit, comprise first buffer unit and second buffer unit, be used to produce written allowance signal, first buffer unit to described FPGA deposits the Frame that CPU inquires about the effective back transmission of this signal in, and from described first buffer unit reading of data and carry out CRC check, parallel/serial conversion, coding, with storage second buffer unit behind the coding;
Back level data upstream cell, the Frame that level RRU takes place after being used to receive carries out payload and extracts, and buffer memory;
Sequence generator is used to generate the flag sequence of Frame;
Up MUX is used for sending the data at the corresponding levels of described second buffer unit, the back level data of the 3rd buffer unit or the flag sequence of sequence generator by up link.
Wherein, described data uplink at the corresponding levels unit comprises first buffer unit and second buffer unit, the capacity of described first buffer unit and second buffer unit is according to the maximum length design of Frame, CPU is disposable to write first buffer unit with Frame, and the data of carrying out behind CRC check, parallel/serial conversion, the coding deposit in second buffer unit.
Wherein, described up MUX sends after the back level data of described the 3rd buffer unit, sends the data at the corresponding levels of second buffer unit, when second buffer unit and the 3rd buffer unit free of data, sends the flag sequence of sequence generator.
As can be seen from the above technical solutions, in technical solution of the present invention, but owing to adopted the FPGA of identification address, and data at the corresponding levels and non-data at the corresponding levels to upstream or downstream are separate processes, on the one hand, FPGA carries out the processing of data tapping and multiple connection, has significantly reduced the workload of CPU, thereby can adopt the CPU of low speed, reduce cost.On the other hand, because data at the corresponding levels and back level data are separate processes, and without CPU, even problem has appearred in CPU at the corresponding levels, can not have influence on the transmission of back level data yet, improved stability of data transmission.In addition, FPGA can also design its capacity according to the maximum length of Frame, is convenient to enlarge the capacity of metadata cache.
[description of drawings]
Fig. 1 is the structured flowchart of the RRU network system of available technology adopting chain networking pattern;
Fig. 2 is the flow chart of the method for HDLC data downstream in the RRU network of the present invention;
Fig. 3 is the flow chart of the method for HDLC data uplink in the RRU network of the present invention;
Fig. 4 is the structured flowchart of the communication device of HDLC data downstream in the RRU network of the present invention;
Fig. 5 is the structured flowchart of the communication device of HDLC data uplink in the RRU network of the present invention.
[embodiment]
Below in conjunction with specific embodiment technical scheme of the present invention is described in detail.
Reduce cost, improve the purpose of transmission stability for reaching, basic ideas of the present invention are, adopt FPGA replaced C PU to transmit the tap and the multiple connection of data, and therefore offloading the CPU only needs to adopt the CPU of low speed to get final product; In addition, also data at the corresponding levels and non-data at the corresponding levels are separately handled, do not needed to handle for non-data CPU at the corresponding levels, but directly send to next stage,, also can not influence the transmission of non-data at the corresponding levels even CPU at the corresponding levels breaks down.
The invention provides the method for HDLC data downstream in a kind of RRU network, as shown in Figure 2, comprising:
Step S201, FPGA receiving data frames, judge that described Frame contains valid data after, detecting this Frame according to the address information of described Frame is data at the corresponding levels or back level data.
Step S202 and deposits buffer unit in if data at the corresponding levels are then deciphered and CRC check, and notice CPU reads the data at the corresponding levels in the buffer unit.
Step S203 is if back level data then are sent to back level RRU.
Its course of work and principle be, for down link, FPGA receives the data that send over from BBU or previous stage RRU, after judging that these data contain valid data, whether after extracting the address information of this Frame, this address information and RRU at the corresponding levels address are compared, detecting is data at the corresponding levels; If data at the corresponding levels then decipher and CRC check, and deposit buffer unit in, notice CPU reads the data at the corresponding levels in the buffer unit, otherwise directly is sent to back level RRU.
For the HDLC data communication in the RRU network system, the solution that the present invention proposes has low, the stable advantages of higher of cost.In the scheme that the present invention proposes, CPU only need read HDLC data at the corresponding levels, has not only greatly reduced the data traffic of CPU external bus interface, and can reduce because the processor resource that metadata cache and copy are consumed.With a Chain Network system that comprises 8 RRU is example, and concerning single RRU, HDLC data volume at the corresponding levels only accounts for 1/6～1/8 of HDLC link data flow.This also means and need not adopt high-speed CPU to handle the HDLC data, thereby reduces the CPU cost.
Adopt FPGA to substitute CPU and finish the multiple connection of HDLC frame and tap work and can also reduce influence, even the CPU of certain one-level RRU breaks down, also can not influence the transfer of data of back level RRU, thereby improve the stability of whole network system the RRU cascaded communication.In the RRU network system, the time-multiplexed mode of HDLC The data of RRU at different levels is shared the HDLC link.
In addition, development along with microelectronics designing technique and technology, the gate that monolithic FPGA is contained and the capacity of on-chip memory are done bigger and bigger, the programmable logic chip of 1,000,000 gate leves has become ordinary product, therefore the FPGA on-chip memory can be finished the buffer memory of multichannel HDLC data, and need not external memorizer or other circuit.
For step S201, described testing process is specially: the Frame to described reception is deciphered, and extract the address information of this Frame and compare with the address of RRU at the corresponding levels, if address unanimity then this Frame is data at the corresponding levels, otherwise be back level data.
For guaranteeing the correctness of transfer of data, in technical scheme of the present invention, also the process that data are handled is carried out delay compensation.For step S202, after described detection is data at the corresponding levels, specifically comprise: the delay compensation that data at the corresponding levels is carried out the address detected process; Data behind the delay compensation are carried out serial/parallel conversion, CRC check, inserted frame head and the postamble set, deposit buffer unit in; Send the data that interrupt signal notice CPU reads described buffer unit.
For step S203, described detection is back level data, the detailed process that is sent to back level RRU comprises: back level data are deciphered delay compensation with the address detected process, be sent to back level RRU when detecting to back level data, otherwise send flag sequence that sequencer generates to back level RRU.
In the process of described insertion frame head and postamble,, then after the sequence of these data, insert recognition sequence if the sequence that contains in the frame head of the sequence in the described data and insertion or the postamble is identical; When CPU response interrupts reading above-mentioned data, with the recognition sequence deletion of inserting.
For example, frame head and postamble are made as " 0 * 4,142 0 * 4344 " and " 0 * 4,142 0 * 4345 " respectively, can certainly set other form, then the data behind the delay compensation are carried out serial/parallel conversion and CRC check.In packing process, be frame head or postamble for fear of CPU with the erroneous judgement of hdlc valid data, if occur 0 * 4142 in the hdlc valid data, so just insert recognition sequence 0 * 0 thereafter, obviously this recognition sequence also can be set at other forms.The reading of data in the deposit receipt unit of postponing of having no progeny in the CPU response, and carry out the location of HDLC frame according to frame head and postamble.Delete 0 * 0 of 0 * 4142 back during occurrence sequence in detecting the HDLC frame data " 0 * 4,142 0 * 0 ", to recover original HDLC valid data.
As a further improvement on the present invention, in each embodiment, described FPGA can have two to the condition that CPU sends interrupt signal:
When the data number of storing in the described buffer unit during, send interrupt signal, the reading of data of having no progeny in the CPU response greater than the threshold value set; Or,
The time of interrupting when distance last time sends interrupt signal, the reading of data of having no progeny in the CPU response during greater than the threshold value set.
When arbitrary condition satisfied, FPGA can produce CPU and interrupt, and can reduce interruption times under the prerequisite that satisfies the HDLC real-time property like this, the expense when reducing CPU response interruption.Certainly, also can realize interrupting,, when arrive in break period, interrupt such as setting a fixing break period in other mode.
The present invention also provides the method for HDLC data uplink in a kind of RRU network, as shown in Figure 3, comprising:
Step S301, FPGA produce written allowance signal, and CPU inquires about this signal and effectively writes Frame to first buffer unit of described FPGA in the back, and FPGA carries out CRC check, parallel/serial conversion, coding, deposits second buffer unit in.
The Frame that step S302, reception back level RRU take place carries out payload and extracts, and deposits the 3rd buffer unit in.
Step S303, sequence generator generate the flag sequence of Frame.
Step S304, the back level data of data at the corresponding levels, the 3rd buffer unit that send described second buffer unit by up link or the flag sequence of sequence generator.
Its course of work and principle are, for data at the corresponding levels, FPGA produces CPU written allowance signal cpu_write_grant, before sending the HDLC data, at first inquires about CPU the cpu_write_grant signal, if this signal is effective, CPU writes a complete HDLC frame continuously to FPGA, otherwise continues inquiry after waiting for certain hour, till signal effectively.The generation principle of written allowance signal cpu_write_grant is: when in first buffer unit and second buffer unit all during free of data, cpu_write_grant is changed to effective status, otherwise is changed to disarmed state.After CPU has write frame data, FPGA reading of data and carry out CRC check, parallel/serial conversion and the HDLC coding from first buffer unit, the HDLC data after will encoding then write second buffer unit.Wherein, the capacity of described first buffer unit and second buffer unit is according to the maximum length design of Frame, and CPU can disposablely write first buffer unit with Frame.
Upstream data for back level RRU produces at first extracts the HDLC payload, then it is deposited in the 3rd buffer unit.
According to the HDLC agreement, when free of data is transmitted, also need to send bell idles, sequence generator generates the flag sequence 01111110 of HDLC frame.
Above-mentioned three kinds of data all send to MUX, and MUX sends the data at the corresponding levels of described second buffer unit, the back level data of the 3rd buffer unit or the flag sequence of sequence generator by up link.
For the HDLC data communication in the RRU network system, the solution that the present invention proposes has low, the stable advantages of higher of cost.In the scheme that the present invention proposes, CPU only need read HDLC data at the corresponding levels, has not only greatly reduced the data traffic of CPU external bus interface, and can reduce because the processor resource that metadata cache and copy are consumed.With a Chain Network system that comprises 8 RRU is example, and concerning single RRU, HDLC data volume at the corresponding levels only accounts for 1/6～1/8 of HDLC link data flow.This also means and need not adopt high-speed CPU to handle the HDLC data, thereby reduces the CPU cost.
Adopt FPGA to substitute CPU and finish the multiple connection of HDLC frame and tap work and can also reduce influence, even the CPU of certain one-level RRU breaks down, also can not influence the transfer of data of back level RRU, thereby improve the stability of whole network system the RRU cascaded communication.In the RRU network system, the time-multiplexed mode of HDLC The data of RRU at different levels is shared the HDLC link.
In addition, development along with microelectronics designing technique and technology, the gate that monolithic FPGA is contained and the capacity of on-chip memory are done bigger and bigger, the programmable logic chip of 1,000,000 gate leves has become ordinary product, therefore the FPGA on-chip memory can be finished the buffer memory of multichannel HDLC data, and need not external memorizer or other circuit.
In a preferred embodiment, the data decimation principle of MUX is: preferentially choose the data in the 3rd buffer unit, next selects the data in second buffer unit, when in these two buffer units all during free of data, selects the data of sequence generator.
According to the course of work and the principle of the method for HDLC data downstream in the RRU network, the present invention also provides the communication device of HDLC data downstream in a kind of RRU network, and this device adopts FPGA to design, and as shown in Figure 4, this communication device comprises:
Address detected unit 403, the address information that is used for the Frame that will receive compares with the address of RRU at the corresponding levels, and detecting this Frame is data at the corresponding levels or back grade data;
Data downstream at the corresponding levels unit is used for data at the corresponding levels are deciphered and CRC check, and deposits buffer unit in, and notice CPU reads the data at the corresponding levels in the buffer unit;
Back level data downstream units is used for back level data are sent to back level RRU.
In more excellent embodiment, described data downstream at the corresponding levels unit comprises: decoding unit 402 is used for data at the corresponding levels are deciphered; Time delay at the corresponding levels unit 404 is used for the data at the corresponding levels after the decoding are carried out the delay compensation of address detected process; Packaged unit 405 is used for the data behind the delay compensation being carried out serial/parallel conversion, CRC check, inserting frame head and the postamble set; Buffer unit 406 is used to store the data that described packaged unit 405 sends; Interrupt location 407 is used for sending interrupt signal to CPU, and notice CPU reads the data of described buffer unit 406.
In a preferred embodiment, the condition that described interrupt location 407 sends interrupt signals is: when the data number of storage in the described buffer unit 406 during greater than the threshold value set, send interrupt signal to CPU; Or,
The time of interrupting when distance last time sends interrupt signal to CPU during greater than the threshold value set.
In more excellent embodiment, a described back level downstream units comprises: level time delay unit, back 408 is used for back level data are deciphered delay compensation with the address detected process, and sends to MUX 410; Sequencer 409 is used to generate flag sequence; MUX 410 is used for when described address detected unit detects current data for back level data, and the back level data that will carry out behind the delay compensation send to the RRU of subordinate, otherwise send the flag sequence that described sequencer 410 generates.
In a preferred embodiment, its concrete course of work is, Mark Detection unit 401 is according to the identity code of HDLC agreement " 01111110 " the descending HDLC signal dl_hdlc_link that imports is detected, generate HDLC data index signal payload_flag, when payload_flag was high level, the dateout hdlc_data of Mark Detection unit 401 was the HDLC payload.After deciphering, 402 pairs of HDLC payloads of decoding unit obtain the decode_hdlc signal.Address detected unit 403 from the decode_hdlc signal, extract the HDLC frame address information and and the address of RRU at the corresponding levels compare, judge whether to HDLC data at the corresponding levels and produce index signal local_hdlc_flag.When local_hdlc_flag was ' 1 ', the expression present frame was HDLC data at the corresponding levels, otherwise is non-HDLC data at the corresponding levels.
For HDLC data at the corresponding levels, time delay at the corresponding levels unit 404 postpones to obtain signal decode_hdlc_delay according to the processing delay of address detecting unit 403 to the decode_hdlc signal.Packaged unit 405 is carried out serial/parallel conversion, CRC check, insertion frame head postamble according to index signal local_hdlc_flag to signal decode_hdlc_delay, and the data after will packing write in the buffer unit 406.Wherein, frame head and postamble are respectively " 0 * 4,142 0 * 4344 " and " 0 * 4,142 0 * 4345 ", and the HDLC valid data are that signal decode_hdlc_delay is carried out the data that obtain after serial/parallel conversion and the CRC check.In packing process, be frame head or postamble for fear of CPU with the erroneous judgement of hdlc valid data, if occur 0 * 4142 in the hdlc valid data, so just inserting 0 * 0 thereafter.
FPGA notifies CPU to read data in the buffer unit 406 in the mode of interrupting.Be provided with two and interrupt the generation condition: (a) the data number of storing in the buffer unit 406 is greater than the thresholding of setting in advance; (b) in the buffer unit 406 data are arranged, the data number does not reach the thresholding of prior setting, but surpasses the timing thresholding of prior setting apart from the time that interrupted last time.Interrupt location 407 can produce the CPU interruption when arbitrary condition satisfies, and can reduce interruption times under the prerequisite that satisfies the HDLC real-time property like this, the expense when reducing CPU response interruption.The reading of data in the deposit receipt unit 406 of postponing of having no progeny in the CPU response, and carry out the location of HDLC frame according to frame head and postamble.Delete 0 * 0 of 0 * 4142 back during occurrence sequence in detecting the HDLC frame data " 0 * 4,142 0 * 0 ", to recover original HDLC valid data.
For non-HDLC data at the corresponding levels, level time delay unit 408, back postpones to obtain signal hdlc_data_delay according to total processing delay of decoding unit 402 and address detected unit 403 to the hdlc_data signal.Sequence generator 409 generates the flag sequence of HDLC frame " 01111110 ".When index signal local_hdlc_flag was ' 0 ', MUX 410 was sent to back level RRU with the hdlc_data_delay signal, otherwise sent the flag sequence of HDLC frame " 01111110 ".
According to the course of work and the principle of the method for HDLC data uplink in the RRU network, the present invention also provides the communication device of HDLC data uplink in a kind of RRU network, and this device adopts FPGA to design, and as shown in Figure 5, this communication device comprises:
Data uplink at the corresponding levels unit is used to produce written allowance signal, deposits CPU in and inquires about the effectively Frame of back transmission of this signal, carries out CRC check, parallel/serial conversion, coding, and buffer memory;
Back level data upstream cell, the Frame that level RRU takes place after being used to receive carries out payload and extracts, and buffer memory;
Sequence generator 507 is used to generate the flag sequence of Frame;
Up MUX is used for sending the data at the corresponding levels of described second buffer unit, the back level data of the 3rd buffer unit or the flag sequence of sequence generator by up link.
In more excellent embodiment, described data uplink at the corresponding levels unit comprises first buffer unit 502 and second buffer unit 504, the capacity of described first buffer unit 502 and second buffer unit 504 is according to the maximum length design of Frame, CPU is disposable to write first buffer unit 502 with Frame, and the data of being undertaken behind CRC check, parallel/serial conversion, the coding by encapsulation unit 503 deposit in second buffer unit 504.
In more excellent embodiment, described up MUX sends after the back level data of described the 3rd buffer unit 506, send the data at the corresponding levels of second buffer unit, when second buffer unit 504 and the 3rd buffer unit 506 free of data, send the flag sequence of sequence generator 507.
In a preferred embodiment, its concrete course of work is, for up HDLC link, flow controlling unit 501 produces CPU written allowance signal cpu_write_grant, at first inquired about the cpu_write_grant signal before CPU sends the HDLC data, if this signal is effective, CPU writes a complete HDLC frame continuously to first buffer unit 502 of FPGA, otherwise continue inquiry behind the wait certain hour, till signal effectively.The generation principle of written allowance signal cpu_write_grant is: when in first buffer unit 502 and second buffer unit 504 all during free of data, cpu_write_grant is changed to effective status, otherwise is changed to disarmed state.After CPU has write frame data, encapsulation unit 503 reading of data and carry out CRC check, parallel/serial conversion and the HDLC coding from first buffer unit 502, the HDLC data after will encoding then write second buffer unit 504.
For the up HDLC signal ul_hdlc_link that back level RRU produces, payload extraction unit 505 extracts the HDLC payload from ul_hdlc_link, and deposits it in the 3rd buffer unit 506.Sequence generator 507 generates the flag sequence of HDLC frame " 01111110 ".
Up MUX 508 is chosen the suitable data source and is read signal from second buffer unit 502, the 3rd buffer unit 506 and sequence generator 507 threes, and it is sent to BBU by up HDLC link, finishes the multiple connection of HDLC frame.The data decimation principle of up MUX 508 is: preferentially choose the data in the 3rd buffer unit 506, next selects the data in second buffer unit 502, when in these two buffer units all during free of data, selects the data of sequence generator 507.Because the generation of data uplink at the corresponding levels can be controlled, then the data that send over of one-level can not be controlled, and the back level is often many, the therefore preferential data that send the back level.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (14)
1. the method for HDLC data downstream in the RRU network is characterized in that, comprising:
The FPGA receiving data frames, judge that described Frame contains valid data after, detecting this Frame according to the address information of described Frame is data at the corresponding levels or back level data;
If data at the corresponding levels, then decipher and CRC check, and deposit buffer unit in, when the data number of storing in the described buffer unit greater than the threshold value of setting or when time of interrupting during greater than the threshold value set apart from last time, send interrupt signal and notify CPU to read data at the corresponding levels in the buffer unit;
If back level data then are sent to back level RRU.
2. the method for HDLC data downstream is characterized in that in the RRU network according to claim 1, and described testing process is specially:
Frame to described reception is deciphered, and extract the address information of this Frame and compare with the address of RRU at the corresponding levels, if address unanimity then this Frame is data at the corresponding levels, otherwise be back level data.
3. the method for HDLC data downstream is characterized in that in the RRU network according to claim 2, and described detection is after the data at the corresponding levels, specifically comprises:
Data at the corresponding levels are carried out the delay compensation of address detected process;
Data behind the delay compensation are carried out serial/parallel conversion, CRC check, inserted frame head and the postamble set, deposit buffer unit in;
Send the data that interrupt signal notice CPU reads described buffer unit.
4. the method for HDLC data downstream in the RRU network according to claim 3 is characterized in that:
In the process of described insertion frame head and postamble,, then after the sequence of these data, insert recognition sequence if the sequence that contains in the frame head of the sequence in the described data and insertion or the postamble is identical;
When CPU response interrupts reading above-mentioned data, with the recognition sequence deletion of inserting.
5. the method for HDLC data downstream is characterized in that in the RRU network according to claim 2, and described detection is back level data, and the detailed process that is sent to back level RRU comprises:
Level data in back are deciphered delay compensation with the address detected process, when detecting, be sent to back level RRU, otherwise send flag sequence that sequencer generates to back level RRU to back level data.
6. the method for HDLC data uplink in the RRU network is characterized in that, comprising:
FPGA produces written allowance signal, CPU inquires about this signal and effectively writes Frame to first buffer unit of described FPGA in the back, FPGA reading of data and carry out CRC check, parallel/serial conversion, coding from described first buffer unit deposits the data behind the coding in second buffer unit;
The Frame that receives back level RRU generation carries out payload and extracts, and deposits the 3rd buffer unit in;
Sequence generator generates the flag sequence of Frame;
Send the data at the corresponding levels of described second buffer unit, the back level data of the 3rd buffer unit or the flag sequence of sequence generator by up link.
7. the method for HDLC data uplink is characterized in that in the RRU network according to claim 6, and the detailed process of said write Frame is:
The capacity of described first buffer unit and second buffer unit is according to the maximum length design of Frame, and CPU is disposable to write first buffer unit with Frame.
8. the method for HDLC data uplink is characterized in that in the RRU network according to claim 6, and the detailed process of described transmission is:
Send after the back level data of described the 3rd buffer unit, send the data at the corresponding levels of second buffer unit, when second buffer unit and the 3rd buffer unit free of data, send the flag sequence of sequence generator.
9. the communication device of HDLC data downstream in the RRU network is characterized in that, this device adopts FPGA to design, and comprising:
The address detected unit, the address information that is used for the Frame that will receive compares with the address of RRU at the corresponding levels, and detecting this Frame is data at the corresponding levels or back grade data;
Data downstream at the corresponding levels unit, be used for data at the corresponding levels are deciphered and CRC check, and deposit buffer unit in, when the data number of storing in the described buffer unit greater than the threshold value of setting or when time of interrupting during greater than the threshold value set apart from last time, send interrupt signal and notify CPU to read data at the corresponding levels in the buffer unit;
Back level data downstream units is used for back level data are sent to back level RRU.
10. the communication device of HDLC data downstream is characterized in that in the RRU network according to claim 9, and described data downstream at the corresponding levels unit comprises:
Decoding unit is used for data at the corresponding levels are deciphered;
Time delay at the corresponding levels unit is used for the data at the corresponding levels after the decoding are carried out the delay compensation of address detected process;
Packaged unit is used for the data behind the delay compensation being carried out serial/parallel conversion, CRC check, inserting frame head and the postamble set;
Buffer unit is used to store the data that described packaged unit sends;
Interrupt location is used for sending interrupt signal to CPU, and notice CPU reads the data of described buffer unit.
11. the communication device of HDLC data downstream is characterized in that in the RRU network according to claim 9, described back level data downstream units comprises:
Back level time delay unit is used for back level data are deciphered delay compensation with the address detected process, and sends to MUX;
Sequencer is used to generate flag sequence;
MUX is used for when described address detected unit detects current data for back level data, and the back level data that will carry out behind the delay compensation send to the RRU of subordinate, otherwise send the flag sequence that described sequencer generates.
12. the communication device of HDLC data uplink is characterized in that in the RRU network, this device adopts FPGA to design, and comprising:
Data uplink at the corresponding levels unit, comprise first buffer unit and second buffer unit, be used to produce written allowance signal, first buffer unit to described FPGA deposits the Frame that CPU inquires about the effective back transmission of this signal in, and from described first buffer unit reading of data and carry out CRC check, parallel/serial conversion, coding, with storage second buffer unit behind the coding;
Back level data upstream cell, the Frame that level RRU takes place after being used to receive carries out payload and extracts, and buffer memory;
Sequence generator is used to generate the flag sequence of Frame;
Up MUX is used for sending the data at the corresponding levels of described second buffer unit, the back level data of the 3rd buffer unit or the flag sequence of sequence generator by up link.
13. the communication device of HDLC data uplink in the RRU network according to claim 12 is characterized in that:
The capacity of described first buffer unit and second buffer unit is according to the design of the maximum length of Frame, and CPU is disposable to write first buffer unit with Frame, carries out CRC check, parallel/serial conversion, the data after encoding deposit in second buffer unit.
14. the communication device of HDLC data uplink in the RRU network according to claim 13 is characterized in that:
Described up MUX sends after the back level data of described the 3rd buffer unit, sends the data at the corresponding levels of second buffer unit, when second buffer unit and the 3rd buffer unit free of data, sends the flag sequence of sequence generator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101239382A CN101146102B (en) | 2007-10-16 | 2007-10-16 | HDLC data uplink and downlink method and communication device in RRU network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101239382A CN101146102B (en) | 2007-10-16 | 2007-10-16 | HDLC data uplink and downlink method and communication device in RRU network |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101146102A CN101146102A (en) | 2008-03-19 |
| CN101146102B true CN101146102B (en) | 2010-09-15 |
Family
ID=39208390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101239382A Active CN101146102B (en) | 2007-10-16 | 2007-10-16 | HDLC data uplink and downlink method and communication device in RRU network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101146102B (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101651603B (en) * | 2008-08-15 | 2011-12-07 | 中兴通讯股份有限公司 | Method and device for controlling signaling traffic |
| CN101415027B (en) * | 2008-11-25 | 2012-05-30 | 哈尔滨工业大学 | Communication module based on HDLC protocol, and control method for data real time forwarding and storage |
| CN101932142B (en) * | 2009-06-19 | 2015-04-01 | 中兴通讯股份有限公司 | User interface data uplink/downlink transmission methods of time division BTS (Base Transceiver Station) for IP access |
| CN101938285B (en) * | 2010-08-30 | 2012-11-28 | 武汉邮电科学研究院 | Method and device for realizing RRU data interface by using ping-pong operation |
| CN102065008A (en) * | 2010-12-16 | 2011-05-18 | 华为技术有限公司 | Data transmission method, radio remote unit, station and communication system |
| CN103179036B (en) * | 2011-12-21 | 2016-08-24 | 上海博达数据通信有限公司 | The method realizing the Linktrace of MPLS-TP OAM based on FPGA |
| CN103186608B (en) * | 2011-12-30 | 2017-08-08 | 北京谊安医疗系统股份有限公司 | The method and apparatus that a kind of queue serializes formula processing data |
| CN104199783B (en) * | 2014-09-15 | 2017-06-20 | 烽火通信科技股份有限公司 | The caching of ethernet data frame and the method and device for forwarding in FPGA |
| CN104320864B (en) * | 2014-10-15 | 2018-05-08 | 新华三技术有限公司 | A kind of data transmission method and wireless access point AP |
| CN104410583B (en) * | 2014-11-26 | 2017-09-22 | 北京邮电大学 | Up channel data processing method in base band resource pool |
| CN104486241B (en) * | 2014-11-27 | 2017-12-05 | 北京邮电大学 | Down channel data processing method in base band resource pool |
| CN106656410B (en) * | 2015-11-04 | 2020-12-22 | 中兴通讯股份有限公司 | Method and device for sending data frame and baseband board |
| CN105843759B (en) * | 2016-03-17 | 2018-11-20 | 广州海格通信集团股份有限公司 | A kind of multi-serial communication method based on HDLC |
| CN109800195A (en) * | 2019-01-25 | 2019-05-24 | 山东超越数控电子股份有限公司 | A kind of fibre channel adapter and data transmission method based on FPGA |
| CN111181690B (en) * | 2019-12-26 | 2022-10-25 | 山西银河电子设备厂 | Multi-channel communication and interface dynamic switching method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1464666A (en) * | 2002-06-11 | 2003-12-31 | 华为技术有限公司 | Soft base station system based on fiber optic stretch and synchronous method thereof |
| CN1921455A (en) * | 2006-09-12 | 2007-02-28 | 华为技术有限公司 | Serial tandem connection bus up flow control method and node equipment |
| CN1976486A (en) * | 2005-11-28 | 2007-06-06 | 中兴通讯股份有限公司 | Signalling retransmitting system and method thereof |
| CN1988501A (en) * | 2005-12-23 | 2007-06-27 | 中兴通讯股份有限公司 | Realizing device for embedded control path communication using FPGA completing optic transmission device |
-
2007
- 2007-10-16 CN CN2007101239382A patent/CN101146102B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1464666A (en) * | 2002-06-11 | 2003-12-31 | 华为技术有限公司 | Soft base station system based on fiber optic stretch and synchronous method thereof |
| CN1976486A (en) * | 2005-11-28 | 2007-06-06 | 中兴通讯股份有限公司 | Signalling retransmitting system and method thereof |
| CN1988501A (en) * | 2005-12-23 | 2007-06-27 | 中兴通讯股份有限公司 | Realizing device for embedded control path communication using FPGA completing optic transmission device |
| CN1921455A (en) * | 2006-09-12 | 2007-02-28 | 华为技术有限公司 | Serial tandem connection bus up flow control method and node equipment |
Non-Patent Citations (2)
| Title |
|---|
| 李晓娟等.基于FPGA的HDLC设计实现.现代电子技术 6.2007,(6),35-37. |
| 李晓娟等.基于FPGA的HDLC设计实现.现代电子技术 6.2007,(6),35-37. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101146102A (en) | 2008-03-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101146102B (en) | HDLC data uplink and downlink method and communication device in RRU network | |
| CN103141066B (en) | Transmission circuit, reception circuit, transmission method, reception method, communication system and communication method therefor | |
| US10396921B2 (en) | Multi-lane synchronization method, synchronization apparatus and system, and computer storage medium | |
| CN104335534B (en) | Data transmission method for uplink, method of reseptance and equipment | |
| CN101702639B (en) | Check value calculation method and device of cyclic redundancy check | |
| CN101800757A (en) | No-feedback one-way data transmission method based on single fiber structure | |
| CN111106904B (en) | Frame sending processing method and system for DigRF transmission end | |
| CN203151539U (en) | AFDX terminal system virtual link layer IP core | |
| CN111211863B (en) | MAC transmitting terminal, MAC receiving terminal and circuit, FPGA chip and data transmission system | |
| CN102158282B (en) | Optical fiber longitudinal difference protection device and synchronous communication method thereof | |
| CN110838892B (en) | High-reliability merging and forwarding method for multi-path full-duplex serial port | |
| CN102158400B (en) | Communication interface of space-based route switching system and space-based route switching system | |
| US8792348B1 (en) | Serial link interface power control method and apparatus with selective idle data discard | |
| CN102420734A (en) | System for realizing topological structure of controller area network (CAN) bus | |
| CN103209041A (en) | Data collection method for GSM-R (Global System for Mobile for Railways) network interface | |
| CN102916910B (en) | Synchronous multiplexing method on basis of asynchronous system | |
| CN103077152B (en) | A kind of communication acceleration method for terminal equipment of intelligent substation chip chamber | |
| CN102185786A (en) | Soft IP core of HDLC (high-level data link control) protocol controller | |
| CN105718401A (en) | Multiplexing method and system for converting multi-path SMII signal to one-path MII signal | |
| CN110365687B (en) | SWP protocol processor | |
| CN105376149B (en) | Communication gate for rail traffic | |
| CN204244255U (en) | A kind of multichannel E1 deframer system | |
| CN112685350B (en) | 1394link layer chip internal data routing scheduling circuit and scheduling method thereof | |
| CN108833000B (en) | PON system protection switching information transmission method and system | |
| CN116112067A (en) | Multi-carrier demodulation method based on MF-TDMA communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 1118158 Country of ref document: HK |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: WD Ref document number: 1118158 Country of ref document: HK |
|
| ASS | Succession or assignment of patent right |
Owner name: SHENZHEN GUOREN COMMUNICATION CO., LTD. Free format text: FORMER OWNER: GUOREN COMMUNICATION CO LTD., SHENZHEN Effective date: 20150730 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150730 Address after: 518057 Guangdong city of Shenzhen province Nanshan District high tech park of science and technology in three Chinese central road building A building room 13F1303 Patentee after: Shenzhen compatriots limited company that communicates by letter Address before: 518057 building of three people's road, middle science and technology, Nanshan District science and Technology Park, Shenzhen, Guangdong Patentee before: Guoren Communication Co., Ltd., Shenzhen |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191012 Address after: Room 1403, building a, Guoren building, No. 5, Keji Zhongsan Road, gaoxinyuan Middle District, Maling community, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Guoren Wireless Communication Co., Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high tech park of science and technology in three Chinese central road building A building room 13F1303 Patentee before: Shenzhen compatriots limited company that communicates by letter |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20200408 Address after: 518000 5th floor, building 1, Guoren science and Technology Park, the intersection of Jinxiu middle road and Cuijing Road, Longtian street, Pingshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Guoren Technology Co., Ltd Address before: Room 1403, building a, Guoren building, No. 5, Keji Zhongsan Road, gaoxinyuan Middle District, Maling community, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Guoren Wireless Communication Co., Ltd. |
|
| TR01 | Transfer of patent right |