CN1988501A - Realizing device for embedded control path communication using FPGA completing optic transmission device - Google Patents
Realizing device for embedded control path communication using FPGA completing optic transmission device Download PDFInfo
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- CN1988501A CN1988501A CNA2005101324422A CN200510132442A CN1988501A CN 1988501 A CN1988501 A CN 1988501A CN A2005101324422 A CNA2005101324422 A CN A2005101324422A CN 200510132442 A CN200510132442 A CN 200510132442A CN 1988501 A CN1988501 A CN 1988501A
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Abstract
The invention discloses an ECC communication device between the two equipments for using field programmable logic device (FPGA) to realize optical transmission (SDH / SONET). The invention proposes the ECC communication device for using FPGA hardware to process SDH / SONET automatically, through the effective FPGA logic design, the veneer CPU only need to complete some initialization operation of FPGA, the rest tasks of the agreement processing are completed by the FPGA hardware automatically. The invention solves those technical problems, such as CPU overloading in the traditional way, no real-time to complete the conversion from DCC protocol to ECC protocol and easy ECC communication blocking, and raises ECC communications stability of the fiber transmission network.
Description
Technical field
The present invention relates to the Synchronous Optical Network communication technical field, relates in particular to a kind of ECC (Embedded Control Channel) communicating devices of utilizing between field programmable logic device (FPGA) realization optical transmission (SDH/SONET) equipment.
Background technology
In the wiring board of one or more line interfaces of traditional optical transmission device, the DCC processing unit that is formed by the FPGA device is finished with the expense transmitting-receiving of framer and is docked, in the processing expenditure 1 the road or the D1～D12 byte of multichannel all or part of, the synthetic packet that meets the HDLC agreement sends on the DCC universal serial bus, and then finish of the protocol conversion of DCC data packet format to the ECC data packet format by the next stage device, the conversion mode mainly contain two kinds, implementation method as shown in Figure 1:
Mode 1 is utilized the ready-made serial ports of CPU, and serial ports is operated in the HDLC protocol mode, and this serial ports DCC universal serial bus direct and the DCC processing unit docks, and is interrupted by the CPU response, and then finishes the transmitting-receiving of DCC data and the parsing of agreement by CPU.
When the HDLC of CPU channel resource is not enough, will enable mode 2.
At last, dual mode all is to finish the conversion of DCC data format to the ECC data format by CPU by software algorithm, sends to NCP network element control plate by the HDLC serial ports on the CPU by the HDLC bus then.
Above-mentioned two kinds of traditional approachs of realizing ECC communication have all taken a large amount of cpu resources, along with the integrated level of optical transmission device line interface base improves constantly, the line interface quantity of every wiring board constantly increases, the also corresponding increase of DCC number of channels, this just causes the interrupt response of CPU frequent, the load of CPU constantly increases the weight of, thereby can not finish DCC in real time to the ECC protocol conversion process, is easy to cause ECC communication blocking even communication disruption.
Summary of the invention
Given this, overweight in order to solve the traditional approach cpu load, can not finish DCC in real time to the ECC protocol conversion process, cause these technical problems of ECC communication blocking easily, the present invention proposes a kind of FPGA of utilization devices at full hardware and handles ECC communicating devices between the optical transmission device automatically, make that by FPGA being carried out effective logical design veneer CPU only needs to finish some to the initialized operation of FPGA when the initialization, for example register is provided with, remaining protocol processes work is finished automatically by FPGA hardware, below is technical scheme of the present invention:
A kind of FPGA of utilization finishes optical transmission device embedded control channel communicating devices, comprises,
At least one block of network element control plate is used for the processing of NE management and embedded control channel agreement;
At least one Data Communications Channel processing unit is used for the transmitting-receiving of overhead data; And
CPU element;
It is characterized in that this device also comprises:
Field programmable logic device, finish by of protocol conversion and the transmission of Data Communications Channel processing unit, and finish by of the protocol conversion and the transmission of network element control plate to the embedded control channel data to data communication path data of Data Communications Channel processing unit to the Data Communications Channel data of network element control plate to the embedded control channel data;
Buffering area is used for by the Data Communications Channel data to the embedded control channel data and by the protocol conversion of embedded control channel data to data communication path data and the buffer memory of transport process data;
Be connected by the HDLC bus between described network element control plate and the described field programmable logic device;
Be connected by the HDLC bus between described Data Communications Channel processing unit and the described field programmable logic device;
Circuit links to each other between described CPU element and the described field programmable logic device, and CPU element is finished the initialization of described field programmable logic device and configuration.
By above technical scheme, liberated the resource of CPU, solved the problem of ECC communication blocking, improved the stability of the ECC communication of optical transport network.
Description of drawings
Fig. 1 is that traditional DCC-ECC transmits the implementation schematic diagram;
The FPGA implementation logic diagram that Fig. 2 transmits for DCC-ECC;
Fig. 3 is the data flow schematic diagram of ECC-DCC;
Fig. 4 is the frame format schematic diagram of ECC channel data bag;
Fig. 5 is the frame format schematic diagram of the DCC channel data bag of standard.
Embodiment
The present invention utilizes FPGA to realize the exchanges data of ECC master control borad to optical channel plate overhead processing place, finishes the HDLC protocol processes, realizes the transmission of both sides ECC and DCC data, and whole transport process does not need CPU to control in real time.Replace in the traditional scheme, by HDLC communication serial port or the HDLC expander transmitting-receiving serial data (hardware components) of CPU, handle the process of transmitting (software section) between ECC data and the DCC data in real time by software algorithm then, implementation as shown in Figure 2.
The realization of whole proposal is divided into following funtion part and realizes:
ECC_HDLC receives: receive the HDLC frame of sending from the ECC master control borad, resolve ECC control information (some byte ECC information headers) wherein, will meet local data content then and be kept in the buffer memory.
DCC_HDLC sends: the access data of postponing comes out, and sends out by corresponding D CC port according to the DCC content of ECC control information decision from buffer memory that the ECC_HDLC receiving unit is resolved;
DCC_HDLC receives (many groups): multichannel receives the HDLC frame of sending from SDH/SONET overhead processing (DCC extraction) simultaneously, removes frame head and CRC check byte, and the DCC information content is write in the buffer memory.
ECC_HDLC sends: control extracts from buffer memory according to priority with the multichannel DCC information content, then DCC information is added CRC check word and the frame head of ECC control information (some byte ECC information headers), HDLC, sends to the ECC master control borad;
Buffering area: comprise the buffer area read-write controller, and data buffer area, corresponding several up (DCC receives ECC and sends) and descending (ECC accepts DCC and sends) direction respectively.Buffering area is used for the data that buffer memory receives, and the buffer area read-write controller is used for managing the read-write pointer and the empty full state of buffer area.Finish simultaneously ECC_HDLC reception, DCC_HDLC transmission, DCC_HDLC reception and four modules of ECC_HDLC transmission are controlled the timesharing of the read-write permission of RAM;
Cpu i/f: finish collection management to initial configuration He each module service behaviour of some byte control informations.
The enforcement that flows to technical scheme below in conjunction with accompanying drawing and data processing is described in further detail:
In present case, the buffering area controller mainly is made up of several BD (buffer description) table and RAM read-write control timing, and metadata cache adopts RAM to realize.In RAM, divide several FIFO (firstin first out), be used for the data that buffer memory receives; The BD table is used for managing the read-write pointer and the empty full state in FIFO district.
Data flow as shown in Figure 3.
Downstream data flow comprises step:
The data that A, NCP network element control plate issue by the HDLC bus;
B, ECC_HDLC_RX receive (correct with this address coupling and data) data in RAM;
C, take out data from RAM, one of them port from DCC_HDLC_TX sends then.
Upstream comprises step:
D, DCC_HDLC_RX receive data (multichannel simultaneously), then data (so long as correct) are deposited in the RAM;
E, take out data from RAM, ECC_HDLC_TX sends by the HDLC bus
F, NCP network element control plate receive data.
The A:NCP plate is sent out data
NCP network element control plate mails to the HDLC bus with the ECC packet, and data format comprises 10 byte information heads and the ECC protocol package by the DCC channel transfer as shown in Figure 4.10 byte information heads mainly comprise the reserve bytes of destination address, source address, destination slogan, frame length, controlling links byte and 3 bytes.
B:ECC_HDLC receives
After finding effective frame head, real-time analysis is from all data on the bus, as long as the destination address of packet and local address coupling, then the storage except that frame head in RAM, up to find finishing frame head, check the state of packet then, (whether packet is complete, whether crc error is arranged), whether FIFO overflows, and whether the BD table overflows.If packet is correct, FIFO and BD table does not overflow, and then upgrades the BD table, comprises writing present frame length, and will point to the pointer that BD shows and add a unit.The BD table is an enclosure space, if arrived the table tail, then gets back to the gauge outfit of this BD table and restarts.If find any mistake, then abandon this packet, once made a mistake to the report of the statistic register of cpu i/f, and all pointers were all got back to the state that does not receive before this packet.
C:DCC_HDLC sends
The read-write pointer that compares the BD table, if find the pointer value difference, then representative has new ECC packet to receive, obtain the frame length of packet from the BD table, and add the initial fifo address of 1 unit as this frame according to the FIFO pointer that previous frame finishes, begin FIFO district readback data in the RAM according to packet length and initial pointer, and string is changed, and, determine that the corresponding port from a plurality of ports sends according to the port information that ECC_HDLC_RX receives.After sending data, produce and send new CRC byte, send the HDLC frame head of end mark then.The pointer that will point to the BD table then adds a unit.
The data packet format that DCC_HDLC_TX sends as shown in Figure 5.
D:DCC_HDLC receives
A plurality of receive paths work alone simultaneously, find to begin to receive packet behind effective frame head, and the correctness of real-time inspection packet, simultaneously data are write among the FIFO.After receiving the end frame head, check the state of packet, comprise whether packet is complete, and whether crc error etc. is arranged, and whether buffering area overflows.If there is not mistake, read the BD table status again, check whether the BD table overflows or write fullly, can not write if overflow maybe, then writes present frame length to the BD table, and will point to the pointer that BD shows and add 1 unit.If in inspection, find any mistake, (packet error, perhaps buffering area mistake, or BD mistake), then the statistic register report to cpu i/f once made a mistake, and all pointers are all got back to and do not received this packet state before.
E:ECC_HDLC sends
Adopt polling mode, relatively the transmission BD pointer of each passage and DCC_HDLC receive the BD pointer, if find different, then representative has new packet to produce, then ECC_HDLC sends to control and comes into operation, the BD information of reading back in the RAM earlier, therefrom obtain length of data package, the FIFO pointer that finishes according to previous frame adds a unit as initial FIFO pointer then, begin the FIFO district readback data in the RAM, and the string conversion, be ready for sending data, from 10 byte ECC information header registers of cpu i/f configuration, obtain the information of preceding ten bytes earlier, sending to bus as the part of data gets on, send the data of reading among the FIFO then, data length is the frame length of BD table expression, produces new CRC byte at last and finishes frame head.New data packet format as shown in Figure 4.After transmission is really finished, upgrade the BD table, the pointer that promptly points to the BD table adds a unit.
In process of transmitting, if conflict, packet resends, and pointer is got back to the state when sending previous frame.
F:NCP network element control plate is received data
This part is finished at NCP network element control plate, the NCP plate receives the ECC packet from the HDLC bus, resolve 10 byte information heads, thereby judgement source address and port numbers are done respective handling, and resolve the ECC protocol package that the DCC passage passes of passing through of having peeled off 10 byte information heads, finish the connection of DCC-ECC.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those skilled in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (7)
1. one kind is utilized FPGA to finish optical transmission device embedded control channel communicating devices, comprise,
At least one block of network element control plate is used for the processing of NE management and embedded control channel agreement;
At least one Data Communications Channel processing unit is used for the transmitting-receiving of overhead data; And CPU element;
It is characterized in that this device also comprises:
Field programmable logic device, finish by of protocol conversion and the transmission of Data Communications Channel processing unit, and finish by of the protocol conversion and the transmission of network element control plate to the embedded control channel data to data communication path data of Data Communications Channel processing unit to the Data Communications Channel data of network element control plate to the embedded control channel data;
Buffering area is used for by the Data Communications Channel data to the embedded control channel data and by the protocol conversion of embedded control channel data to data communication path data and the buffer memory of transport process data;
Be connected by the HDLC bus between described network element control plate and the described field programmable logic device;
Be connected by the HDLC bus between described Data Communications Channel processing unit and the described field programmable logic device;
Circuit links to each other between described CPU element and the described field programmable logic device, and CPU element is finished the initialization of described field programmable logic device and configuration.
2. the FPGA of utilization as claimed in claim 1 finishes optical transmission device embedded control channel realization of Communication device, it is characterized in that, described buffering area is made of the RAM resource of described field programmable logic device inside.
3. the FPGA of utilization as claimed in claim 1 finishes optical transmission device embedded control channel realization of Communication device, it is characterized in that, described buffering area is a plug-in buffering area, and links to each other by data/address bus with described field programmable logic device.
4. the FPGA of utilization as claimed in claim 3 finishes optical transmission device embedded control channel realization of Communication device, it is characterized in that, described plug-in buffering area uses RAM to realize.
5. the FPGA of utilization as claimed in claim 1 finishes optical transmission device embedded control channel realization of Communication device, it is characterized in that described CPU element can also receive and the service behaviour data of handling inner each module of relevant described field programmable logic device when described device is in running order.
6. finish optical transmission device embedded control channel realization of Communication device as the described FPGA of utilization of arbitrary claim in the claim 1 to 3, it is characterized in that, described field programmable logic device comprises as lower module:
Data Communications Channel receives control module, is used for multichannel and receives the Data Communications Channel data of being sent by the Data Communications Channel processing unit simultaneously, through resolving, depositing buffering area in after the checking, carries out corresponding error when full or data verification makes mistakes when buffering area and handles;
Embedded control channel sends control module, is used for the multichannel data communication path information content is read out from buffering area according to priority, adds the embedded control channel control information then and sends to NCP network element control plate;
Embedded control channel receives control module, be used to receive the embedded control channel data of sending from the network element control plate, resolve wherein embedded control channel control information, to meet local embedded control channel data content then and be saved in the buffering area, and carry out corresponding error when full or data verification makes mistakes when buffering area and handle;
Data Communications Channel sends control module, is used for reading the embedded control channel data from buffering area, and sends to the Data Communications Channel processing unit according to embedded control channel control information decision from that port;
The cpu i/f module is used to finish the collection and the management of control information initial configuration and each module service behaviour data;
The buffer area read-write manager, the buffer area read-write manager is used for managing the read-write pointer and the full state of sky of buffering area, finishes Data Communications Channel simultaneously and receives the time-division control that control module, embedded control channel transmission control module, embedded control channel reception control module and Data Communications Channel transmission control module allow buffer area read-write;
Described Data Communications Channel reception control module, embedded control channel transmission control module, embedded control channel reception control module, Data Communications Channel transmission control module, cpu i/f module, buffer area read-write manager link to each other by internal data bus.
7. the FPGA of utilization as claimed in claim 6 finishes optical transmission device embedded control channel realization of Communication device, it is characterized in that, described buffering area controller is made up of some buffer description tables and RAM read-write control timing.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101146102B (en) * | 2007-10-16 | 2010-09-15 | 深圳国人通信有限公司 | HDLC data uplink and downlink method and communication device in RRU network |
| CN102571577A (en) * | 2011-12-29 | 2012-07-11 | 北京中创信测科技股份有限公司 | Method and device for realizing according-to-configuration distribution of scalable bandwidth interconnect (SBI) interface timeslot by utilizing field programmable gate array (FPGA) |
| CN102665151A (en) * | 2012-04-24 | 2012-09-12 | 烽火通信科技股份有限公司 | Processing method and processing device for DCC (Data Communication Channel) overhead of SDH (Synchronous Digital Hierarchy) service in packet transport network |
| CN103731225A (en) * | 2013-12-24 | 2014-04-16 | 北京格林伟迪科技有限公司 | Data transmission method and device |
| CN104391461A (en) * | 2014-10-23 | 2015-03-04 | 四川九洲电器集团有限责任公司 | High-integration KNX (Konnex) transmission control device |
| WO2024124729A1 (en) * | 2022-12-16 | 2024-06-20 | 无锡中微亿芯有限公司 | Fpga for realizing data transmission by means of built-in edge module |
Family Cites Families (2)
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| CN100433607C (en) * | 2002-08-02 | 2008-11-12 | 中兴通讯股份有限公司 | Transmission for embedded control channel data |
| CN1269320C (en) * | 2003-07-24 | 2006-08-09 | 烽火通信科技股份有限公司 | Organizing method for automaitic switching optical network node communication structure based on embedded communication channel technique |
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- 2005-12-23 CN CN2005101324422A patent/CN1988501B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101146102B (en) * | 2007-10-16 | 2010-09-15 | 深圳国人通信有限公司 | HDLC data uplink and downlink method and communication device in RRU network |
| CN102571577A (en) * | 2011-12-29 | 2012-07-11 | 北京中创信测科技股份有限公司 | Method and device for realizing according-to-configuration distribution of scalable bandwidth interconnect (SBI) interface timeslot by utilizing field programmable gate array (FPGA) |
| CN102571577B (en) * | 2011-12-29 | 2015-02-18 | 北京中创信测科技股份有限公司 | Method and device for realizing according-to-configuration distribution of scalable bandwidth interconnect (SBI) interface timeslot by utilizing field programmable gate array (FPGA) |
| CN102665151A (en) * | 2012-04-24 | 2012-09-12 | 烽火通信科技股份有限公司 | Processing method and processing device for DCC (Data Communication Channel) overhead of SDH (Synchronous Digital Hierarchy) service in packet transport network |
| CN102665151B (en) * | 2012-04-24 | 2014-12-03 | 烽火通信科技股份有限公司 | Processing method and processing device for DCC (Data Communication Channel) overhead of SDH (Synchronous Digital Hierarchy) service in packet transport network |
| CN103731225A (en) * | 2013-12-24 | 2014-04-16 | 北京格林伟迪科技有限公司 | Data transmission method and device |
| CN103731225B (en) * | 2013-12-24 | 2016-08-17 | 北京格林伟迪科技股份有限公司 | A kind of data transmission method and device |
| CN104391461A (en) * | 2014-10-23 | 2015-03-04 | 四川九洲电器集团有限责任公司 | High-integration KNX (Konnex) transmission control device |
| CN104391461B (en) * | 2014-10-23 | 2017-02-15 | 四川九洲电器集团有限责任公司 | KNX (Konnex) transmission control device |
| WO2024124729A1 (en) * | 2022-12-16 | 2024-06-20 | 无锡中微亿芯有限公司 | Fpga for realizing data transmission by means of built-in edge module |
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