CN101459815A - Data transmission method for video frequency light end machine and decoding method for video receiving machine - Google Patents
Data transmission method for video frequency light end machine and decoding method for video receiving machine Download PDFInfo
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Abstract
The invention provides a data transmitting method of a video transmitting machine, which comprises the following steps: dividing the least significant bit of eight bit video data into 4n time slots, each of the time slots comprises eight clock cycles, transmitting frame synchronous codes to the first seven clock cycles of the kn time slots, transmitting asynchronous codes to the eighth clock cycle, transmitting a lowest bit of sampling cycle video data to the first seven clock cycles of the kn+1 time slots, transmitting network management data to the eighth clock cycle, transmitting the lowest bit of sampling cycle video data to the first seven clock cycles of the kn+2 time slots, and transmitting asynchronous data to the eighth clock cycle, and transmitting the lowest bit of sampling cycle video data to the first seven clock cycles of the kn+3 time slots, and transmitting the network management data to the eighth clock cycle, improving the video data by seven bits and combing a one bit serial data into eight bit parallel data and coding into ten bit parallel data after framing. The data transmitting method of a video transmitting machine and the decoding method of the video transmitting machine are used for improving the resolution factor of the videos and improving the quality of video signals.
Description
Technical field
The present invention relates to a kind of video optical multiplexer, particularly a kind of video transmitter data transmission method and video receiver coding/decoding method.
Background technology
Continuous expansion along with the video optical multiplexer scope of application, user's technological know-how aspect uneven, the factor complicated and changeable of environment for use, function to video optical multiplexer, especially operability, multiple services flexible combination, applicabilities etc. are had higher requirement, only can transmit video signal preferably, can not satisfy current security protection market video optical multiplexer user's demand far away.
Video optical multiplexer comprises video transmitter and video receiver.Video transmitter is vision signal and other auxiliary signal to be combined be transferred to video receiver by optical-fibre channel.Video receiver receives the signal from video transmitter, and the signal that receives is reverted to vision signal and other auxiliary signal.
Video transmitter is in the control point of far-end usually, and video receiver is usually located at Surveillance center.Surveillance center need control the monitoring camera of far-end, but also need the watch-dog of far-end be managed.This is with regard to requiring video optical multiplexer video not only can being provided but also need provide data channel to be used for the monitoring camera of far-end is controlled, and need provide network management path to be used for watch-dog is managed.
Because the distance between video transmitter and the video receiver is distant, generally all transmits by optical fiber.In order to make correctly recovered clock and extract data of video receiver, require the data flow of Optical Fiber Transmission must DC (direct current) balance, and can not have in the data flow and longly connect 0 and longly connect 1.The optical fiber transport channel video receiver needs the front-end circuit of AC (interchange) coupling, and the data flow that therefore requires to be transmitted must the DC balance.The DC balance of data flow can be simplified video transmitter level control circuit, video receiver gain, equalizing circuit design simultaneously.Long connect 0 and longly connect 1 the clock information in the data flow is reduced, be unfavorable for SERDES (serializer deserializer) recovered clock from data flow, connect 0 and longly connect 1 and can cause that mistake appears in the level decision circuit of receiver, causes video receiver error code to occur with duration.
To be transmitted the characteristic that data have the DC balance in order making, to avoid simultaneously in the data occurring longly connecting 0 and longly connect 1, method commonly used comprises carries out scrambler and data is carried out line coding data.
First kind of traditional scheme is that 1 road asynchronous serial data and 1 tunnel serial network management data are that example describes with 1 road video data and auxiliary data.
First kind of traditional scheme is combined into 10 parallel-by-bit data with 1 road video data, 1 road asynchronous serial data and 1 tunnel serial network management data, then to giving SERDES (serializer deserializer) behind its scrambler, SERDES carries out 10 parallel-by-bit data and go here and there converting 1 Bits Serial data to, sends through optical module.
First kind of traditional scheme is when use is carried out the scrambler scheme to data, because scrambler can not solve the DC equilibrium problem of data flow, the DC imbalance can cause that mistake appears in the level decision circuit of receiver, causes receiver error code to occur.And error code can cause the SERDES step-out.Step-out is because mistake appears in the SERDES synchronous code that error code causes, and then causes the phenomenon of synchronization loss.Step-out can make SERDES reenter synchronizing process.Cause the restore data mistake during SERDES step-out, and then cause the problem that vision signal is fuzzy even interrupt.
Second kind of traditional scheme adopts the scheme of the data that are transmitted being carried out line coding.
Because 8B/10B encoding and decoding mechanism has the feature of DC (direct current) balance and multiple 0/1 conversion, be fit to very much Optical Fiber Transmission, so the 8B/10B encoding and decoding mechanism of line coding choice criteria.
Second kind of traditional scheme formed high 7 in 1 Bits Serial frame and the 8 digital video data with 1 road asynchronous serial data, 1 tunnel serial network management data, forms 8 bit data, gives 8B/10B coding module.The 8B/10B coding module is encoded into 10 bit data with 8 bit data and gives SERDES, and SERDES carries out 10 parallel-by-bit data and goes here and there conversion, obtains 1 Bits Serial data, sends through optical module again.
The frame structure of second kind of traditional scheme, every frame be totally 24 clock cycle, divides 3 time slots, and each time slot is 8 clock cycle.Frame swynchronization code, asynchronous data and network management data take 1 time slot respectively, form 1 Bits Serial code stream jointly.
Though second kind of traditional scheme adopts and data are carried out line coding can solve first kind of traditional scheme and data are carried out scrambler handle caused SERDES step-out problem, but, cause the actual samples precision of vision signal to have only 7 bits because 1 road asynchronous serial data and 1 tunnel serial network management data have taken the bandwidth of video data lowest bit fully.Thereby reduced the resolution of video sampling, caused that video signal quality descends.
Summary of the invention
The purpose of this invention is to provide a kind of video transmitter data transmission method and video receiver coding/decoding method, be used for solving employing first traditional scheme of above-mentioned background technology and the technical problem that second traditional scheme brings.
For addressing the above problem, the present invention discloses a kind of video transmitter data transmission method, said method comprising the steps of:
Lowest order in the 8 digital video data is divided into 4n time slot, and each time slot comprises 8 clock cycle, and n is the positive integer more than or equal to 1;
With preceding 7 clock cycle transmit frame synchronous codes of kn time slot, the 8th clock cycle sends asynchronous data, and k is the positive integer more than or equal to 1;
Preceding 7 clock cycle of kn+1 time slot are sent the lowest bit of the video data in a sampling period, and the 8th clock cycle sends network management data;
Preceding 7 clock cycle of kn+2 time slot are sent the video data in described sampling period, and the 8th clock cycle sends asynchronous data;
Preceding 7 clock cycle of kn+3 time slot are sent the lowest bit of the video data in described sampling period, and the 8th clock cycle sends network management data;
High 7 and give the 8B/10B coding module through the synthetic 8 parallel-by-bit data of 1 Bits Serial data set behind the framing and be encoded into 10 parallel-by-bit data with described 8 digital video data;
10 parallel-by-bit data are carried out and go here and there conversion, obtain serial data, more described serial data is carried out electric light conversion back and send.
Preferably, described n is specially 8.
Preferably, by the serializer deserializer 10 parallel-by-bit data are carried out and go here and there conversion.
The present invention also provides a kind of video receiver coding/decoding method, said method comprising the steps of:
With the data that receive, carry out obtaining serial data after the opto-electronic conversion;
From described serial data, extract clock and data, and go here and there and be converted to parallel data;
Parallel data decoded obtain 8 bit data;
The lowest order of 8 bit data is separated frame, and every frame is divided into 4n time slot, and each time slot comprises 8 clock cycle, and n is the positive integer more than or equal to 1;
Preceding 7 clock cycle of kn time slot are frame swynchronization code, and the 8th clock cycle is asynchronous data, and k is the positive integer more than or equal to 1;
The lowest bit that preceding 7 clock cycle of kn+1 time slot are the video data in a sampling period, the 8th clock cycle is network management data;
The video data that preceding 7 clock cycle of kn+2 time slot are the described sampling period, the 8th clock cycle is asynchronous data;
The lowest bit that preceding 7 clock cycle of kn+3 time slot are the video data in described sampling period, the 8th clock cycle is network management data;
Separate frame and obtain 1 road video data, 1 tunnel asynchronous data and 1 road network pipe data.
Preferably, the described step that parallel data is decoded comprises later on: the step of obtaining frame synchronization.
Preferably, the described step of obtaining frame synchronization is specially:
Search frame synchronous code in the lowest order of 8 bit data when searching correct frame swynchronization code continuously, is defined as frame synchronization state;
When searching wrong frame swynchronization code, be defined as the OOF state.
Preferably, after searching correct frame swynchronization code 2 times at least, be defined as frame synchronization state.
Preferably, after searching wrong frame swynchronization code 2 times at least continuously, be defined as thinking the OOF state that enters.
Preferably, obtain frame synchronization by the frame synchronization state machine;
The frame synchronization state machine comprises OOF state, presynchronization state and 3 states of synchronous regime;
When current state was the OOF state, after searching correct frame swynchronization code for the first time, the frame synchronization state machine entered presynchronization state, otherwise is in the OOF state;
When current state is presynchronization state, after the frame synchronization state machine enters this state by the OOF state, search correct frame swynchronization code at least 1 time or continuous 2 times, the frame synchronization state machine enters synchronous regime; When searching the frame swynchronization code of 1 mistake, the frame synchronization state machine comes back to the OOF state;
When current state was frame synchronization state, after the frame synchronization state machine entered this state by presynchronization state, at least 1 time or search wrong frame swynchronization code for 2 times continuously, the frame synchronization state machine entered the OOF state, otherwise is in frame synchronization state.
Preferably, the video data lowest order that is taken by asynchronous data or network management data in described 1 road video data replaces with fixed value 1 or 0;
Perhaps, replace with asynchronous data or network management data;
Perhaps, using the video data lowest order in a sampling period replaces.
The described video transmitter data transmission method of the embodiment of the invention is divided into 4n time slot with the lowest order in the 8 digital video data, and each time slot comprises 8 clock cycle, and n is the positive integer more than or equal to 1; With preceding 7 clock cycle transmit frame synchronous codes of kn time slot, the 8th clock cycle sends asynchronous data; The video data in a sampling period be will all send except that preceding 7 clock cycle of all time slots kn the time slot, network management data or asynchronous data sent the 8th clock cycle; Not continuous being taken like this in the lowest order in 8 digital video data by network management data or asynchronous data, but 8 clock cycle of every interval, its lowest bit data are to be taken by asynchronous data and network management data the 8th clock cycle of each time slot.Every interval 4n time slot has 7 clock cycle to be taken by frame swynchronization code.
The described video transmitter data transmission method of the embodiment of the invention has not only solved first kind of traditional scheme to carry out scrambler to data and handles caused SERDES step-out problem, and 1 the road asynchronous serial data and 1 tunnel serial network management data only taken the bandwidth of few part of video data lowest bit, improve the resolution of video sampling, improved the quality of vision signal.
Description of drawings
Fig. 1 is the video transmitter data transmission method first embodiment flow chart of the present invention;
Fig. 2 is a frame structure schematic diagram of the present invention;
Fig. 3 is the video receiver coding/decoding method first embodiment flow chart of the present invention;
Fig. 4 is a synchronous state machine state transition graph of the present invention.
Embodiment
The embodiment of the invention provides a kind of video transmitter data transmission method, is used to improve the resolution of video sampling, improves the quality of vision signal.
In order to make those skilled in the art understand the present invention program better, the present invention is described in further detail below in conjunction with the drawings and specific embodiments.
Referring to Fig. 1, this figure is the video transmitter data transmission method first embodiment flow chart of the present invention.
The described video transmitter data transmission method of first embodiment of the invention may further comprise the steps:
S10, the lowest order in the 8 digital video data is divided into 4n time slot, each time slot comprises 8 clock cycle, and n is the positive integer more than or equal to 1.
According to ADC (analog to digital converter) quantization principles, when the ADC sampling precision was 8, the value of lowest bit position representative was 1/256 of an ADC measuring range, and therefore the proportion minimum that accounts in 8 sampled datas adopts the lowest bit position.Adopt transmission that the lowest bit position makes auxiliary data that the influence of video is reduced to minimum.
S20, with the preceding 7 bit transmit frame synchronous codes of kn time slot, the 8th bit sends asynchronous data, k is the positive integer more than or equal to 1.
S30, preceding 7 bits of kn+1 time slot are sent the lowest bit of the video data in a sampling period, the 8th bit sends network management data.
S40, preceding 7 bits of kn+2 time slot are sent the video data in described sampling period, the 8th bit sends asynchronous data.
S50, preceding 7 bits of kn+3 time slot are sent the lowest bit of the video data in described sampling period, the 8th bit sends network management data.
S60, high 7 and give the 8B/10B coding module through the synthetic 8 parallel-by-bit data of 1 Bits Serial data set behind the framing and be encoded into 10 parallel-by-bit data with described 8 digital video data;
The 8B/10B coding module can become 10 parallel-by-bit data with described 8 parallel-by-bit digital coding.
S70,10 parallel-by-bit data are carried out and go here and there conversion, obtain serial data, more described serial data is carried out electric light conversion back and send.
The operation principle of existing video transmitter is, become the lowest bit of frame module with the video sampling data, high 7 bits that frame swynchronization code, asynchronous data and network management data are formed 1 bit serial data code stream and video sampling data are formed 8 bit data together and are given 8B/10B coding module, the 8B/10B coding module is encoded into 10 bit data with 8 bit data and gives outside SERDES, SERDES carries out 10 parallel-by-bit data and goes here and there converting serial data to and giving optical module, and optical module carries out the electric light conversion data are sent.
The described video transmitter data transmission method of first embodiment of the invention is divided into 4n time slot with the lowest order in the 8 digital video data, and each time slot comprises 8 clock cycle, and n is the positive integer more than or equal to 1; With preceding 7 clock cycle transmit frame synchronous codes of kn time slot, the 8th clock cycle sends asynchronous data; The video data in a sampling period be will all send except that preceding 7 clock cycle of all time slots kn the time slot, network management data or asynchronous data sent the 8th clock cycle; Not continuous being taken like this in the lowest order in 8 digital video data by network management data or asynchronous data, but 8 clock cycle of every interval, its lowest bit data are to be taken by asynchronous data and network management data the 8th clock cycle of each time slot.Every interval 4n time slot has 7 clock cycle to be taken by frame swynchronization code.
The described video transmitter data transmission method of the embodiment of the invention has not only solved first kind of traditional scheme to carry out scrambler to data and handles caused SERDES step-out problem, and 1 the road asynchronous serial data and 1 tunnel serial network management data only taken the bandwidth of few part of video data lowest bit, improve the resolution of video sampling, improved the quality of vision signal.
The lowest order with in the 8 digital video data among the step S10 is divided into 4n time slot, and each time slot comprises 8 clock cycle, and wherein n can adopt 8.
The described method of the embodiment of the invention can be carried out 10 parallel-by-bit data and goes here and there conversion by the serializer deserializer.
The present invention is directed to the improvement of second kind of traditional scheme in the background technology, making auxiliary data is asynchronous data and network management data and not exclusively to take video data lowest bit bit strip wide.
Below just so that the lowest order in the 8 digital video data is divided into 256 time cycles, 32 time slots are that the structure that example specifies the lowest order in the 8 digital video data is a frame structure altogether.
Referring to Fig. 2, this figure frame structure schematic diagram of the present invention.
The present invention is with the lowest order in the 8 digital video data, and every frame is divided into 256 clock cycle, is divided into 32 time slots, 8 clock cycle of each time slot.
First time slot is preceding 7 bits (clock cycle) the transmit frame synchronous code of TSO, and last 1 bit of TSO sends asynchronous data.
Second time slot is the lowest bit that preceding 7 bits of TS1 send video data, and last 1 bit of TS1 sends network management data.
The 3rd time slot is that preceding 7 bits of TS2 send video data, and last 1 bit of TS2 sends asynchronous data.
The 4th time slot is the lowest bit that preceding 7 bits of TS3 send video data, and last 1 bit of TS3 sends network management data.
And the like, the 31 time slot is that preceding 7 bits of TS30 send video data, last 1 bit of TS30 sends asynchronous data.
The 32 time slot is the lowest bit that preceding 7 bits of TS31 send video data, and last 1 bit of TS31 sends network management data.
8 clock cycle of the every interval of video data, its lowest bit data just can be taken by asynchronous data and network management data.
According to sampling thheorem, the sampling clock frequency must be greater than 2 times signal frequency.Suppose that video bandwidth is 6MHz, the video sampling clock is got 16MHz.According to above-mentioned frame format, approximate 1/8th of the video lowest bit bandwidth that takies of frame swynchronization code, asynchronous data and network management data, i.e. 2Mbps, then the bandwidth of asynchronous data and network management data is respectively 1Mbps.
The embodiment of the invention provides a kind of video receiver coding/decoding method, is used to improve the resolution of video sampling, improves the quality of vision signal.
Referring to Fig. 3, this figure is the video receiver coding/decoding method first embodiment flow chart of the present invention.
The described video receiver coding/decoding method of first embodiment of the invention comprises the steps:
S100, with the data that receive, carry out obtaining serial data after the opto-electronic conversion.
The data that reception utilizes the described video transmitter data transmission method of the embodiment of the invention to send, optical module carries out giving SERDES serial data after the opto-electronic conversion.
S200, from described serial data, extract clock and data, and go here and there and be converted to parallel data.
SERDES finishes from from extracting clock and data the serial signal of optical module, and goes here and there and change, and gives 8B/10B decoder module parallel data.
S300, parallel data decoded obtains the data that exist with the frame form.
The 8B/10B decoder module is finished decoding, decoded data is given separate frame module.
S400, the described data that exist with the frame form are separated frame, every frame is divided into 4n time slot, and each time slot comprises 8 clock cycle, and n is the positive integer more than or equal to 1.
Want to realize separating frame, must obtain frame swynchronization code, the serviceable condition machine that obtains of frame swynchronization code is finished.
Preceding 7 bits of S500, a kn time slot are frame swynchronization code, and the 8th bit is an asynchronous data, and k is the positive integer more than or equal to 1.
The lowest bit that preceding 7 bits of S600, a kn+1 time slot are the video data in a sampling period, the 8th bit are network management data.
The video data that preceding 7 bits of S700, a kn+2 time slot are the described sampling period, the 8th bit are asynchronous data.
The lowest bit that preceding 7 bits of S800, a kn+3 time slot are the video data in described sampling period, the 8th bit are network management data.
The frame synchronization state machine is from from the frame swynchronization code that defines in the search transmitter frame structure the lowest bit of 8 bit data of 8B/10B.
The described step of obtaining frame synchronization can realize in the following way.
Search frame synchronous code in the lowest bit position of the data that exist with the frame form when searching correct frame swynchronization code, is defined as frame synchronization state;
When searching wrong frame swynchronization code, be defined as the OOF state.
S900, separate frame and obtain 1 road video data, 1 tunnel asynchronous data and 1 road network pipe data.
The frame synchronization state machine is separated frame module and solve 1 road video data, 1 tunnel asynchronous data and 1 road network pipe data from 8 bit data that the 8B/10B decoder module is sent here after obtaining frame synchronization.Because the lowest bit of video transmitter video data in framing is taken by asynchronous data and network management data every 8 its values of clock cycle, therefore how to recover the key that occupied video data lowest bit position is design.Occupied video data lowest bit position replaces with fixed value 1 or 0 in described 1 road video data;
Perhaps, replace with asynchronous data or network management data;
Perhaps, using the video data lowest bit position in a sampling period replaces.
Existing four kinds of methods can recover occupied video data lowest bit position.
First method replaces every 8 clock cycle occupied video lowest bit positions with fixed value 1.
Second method replaces every 8 clock cycle occupied video lowest bit positions with fixed value 0.
The third method will promptly replace position, occupied video data lowest bit position with asynchronous data or network management data from the lowest bit data of 8B/10B decoder module directly as the lowest bit position of video data.
First three methods, be used for replacing the value of occupied video lowest bit position and video data without any correlation, replace occupied video lowest bit position to produce certain influence with them, do not compared about decline 4dB with the video lowest bit by the situation of any data occupancy through measuring the first three methods video signal-to-noise ratio to video signal quality.
The 4th kind of method utilizes the adjacent double sampling data of vision signal to have the principle of correlation, replaces occupied video lowest bit position with the video data lowest bit position in last sampling period of occupied video data lowest bit position.
Because the 4th kind of method utilized the adjacent double sampling data of vision signal to have the principle of correlation, adopts the 4th kind of method video signal-to-noise ratio not compared about decline 2dB by the situation of any data occupancy with the video lowest bit through measuring.
To sum up, by utilizing the adjacent double sampling data of vision signal to have the principle of correlation, by at regular intervals at interval, (the present invention is that example is described in detail to adopt every 8 clock cycle) takies the lowest bit position of video sampling data and transmits auxiliary data.Being the transmission that can make auxiliary data of video reception pusher side at receiving terminal drops within the acceptable scope the influence of video signal quality.
Synchronous for fear of vacation, the user can set and search continuously 1 time or continuous frame swynchronization code correct more than 2 times and 2 times is just thought and entered frame synchronization state.Equally, for fear of false step-out, the user also can set 1 time or search wrong frame swynchronization code more than 2 times and 2 times and just think the OOF state that enters continuously.
The frame synchronization state machine comprises three states, OOF state, presynchronization state and synchronous regime.Conversion between three states of frame synchronization state machine as shown in Figure 4.
Referring to Fig. 4, this figure is a synchronous state machine state transition graph of the present invention.
The frame synchronization state machine comprises OOF state, presynchronization state and 3 states of synchronous regime.
When frame synchronization state machine current state was the OOF state, after searching correct frame swynchronization code for the first time, the frame synchronization state machine entered presynchronization state.When not searching frame synchronization, then the frame synchronization state machine is in the OOF state always.When searching the frame swynchronization code of 1 mistake, the frame synchronization state machine enters presynchronization state.
When frame synchronization state machine current state is presynchronization state, after the frame synchronization state machine enters this state by the OOF state, search correct frame swynchronization code at least 1 time or continuous 2 times, the frame synchronization state machine enters frame synchronization state.When searching at least 1 time or during the frame swynchronization code of continuous 2 mistakes, the frame synchronization state machine comes back to the OOF state.
When current state was frame synchronization state, after the frame synchronization state machine entered this state by presynchronization state, at least 1 time or search wrong frame swynchronization code for 2 times continuously, the frame synchronization state machine entered the OOF state, otherwise is in frame synchronization state.
The frame synchronization state machine also can according to search continuously correct frame swynchronization code more than 2 times or 2 times after, be defined as frame synchronization state.
The frame synchronization state machine also can according to search continuously wrong frame swynchronization code more than 2 times or 2 times after, be defined as thinking the OOF state that enters.
More than video transmitter data transmission method provided by the present invention and video receiver coding/decoding method are described in detail.Used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof.Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1, a kind of video transmitter data transmission method is characterized in that, said method comprising the steps of:
Lowest order in the 8 digital video data is divided into 4n time slot, and each time slot comprises 8 clock cycle, and n is the positive integer more than or equal to 1;
With preceding 7 clock cycle transmit frame synchronous codes of kn time slot, the 8th clock cycle sends asynchronous data, and k is the positive integer more than or equal to 1;
Preceding 7 clock cycle of kn+1 time slot are sent the lowest bit of the video data in a sampling period, and the 8th clock cycle sends network management data;
Preceding 7 clock cycle of kn+2 time slot are sent the video data in described sampling period, and the 8th clock cycle sends asynchronous data;
Preceding 7 clock cycle of kn+3 time slot are sent the lowest bit of the video data in described sampling period, and the 8th clock cycle sends network management data;
High 7 and give the 8B/10B coding module through the synthetic 8 parallel-by-bit data of 1 Bits Serial data set behind the framing and be encoded into 10 parallel-by-bit data with described 8 digital video data;
10 parallel-by-bit data are carried out and go here and there conversion, obtain serial data, more described serial data is carried out electric light conversion back and send.
2, data transmission method according to claim 1 is characterized in that, described n is specially 8.
3, data transmission method according to claim 1 is characterized in that, 10 parallel-by-bit data are carried out and goes here and there conversion by the serializer deserializer.
4, a kind of video receiver coding/decoding method is characterized in that, said method comprising the steps of:
With the data that receive, carry out obtaining serial data after the opto-electronic conversion;
From described serial data, extract clock and data, and go here and there and be converted to parallel data;
Parallel data decoded obtain 8 bit data;
The lowest order of 8 bit data is separated frame, and every frame is divided into 4n time slot, and each time slot comprises 8 clock cycle, and n is the positive integer more than or equal to 1;
Preceding 7 clock cycle of kn time slot are frame swynchronization code, and the 8th clock cycle is asynchronous data, and k is the positive integer more than or equal to 1;
The lowest bit that preceding 7 clock cycle of kn+1 time slot are the video data in a sampling period, the 8th clock cycle is network management data;
The video data that preceding 7 clock cycle of kn+2 time slot are the described sampling period, the 8th clock cycle is asynchronous data;
The lowest bit that preceding 7 clock cycle of kn+3 time slot are the video data in described sampling period, the 8th clock cycle is network management data;
Separate frame and obtain 1 road video data, 1 tunnel asynchronous data and 1 road network pipe data.
5, video receiver coding/decoding method according to claim 4 is characterized in that, the described step that parallel data is decoded comprises later on: the step of obtaining frame synchronization.
6, video receiver coding/decoding method according to claim 5 is characterized in that, the described step of obtaining frame synchronization is specially:
Search frame synchronous code in the lowest order of 8 bit data when searching correct frame swynchronization code continuously, is defined as frame synchronization state;
When searching wrong frame swynchronization code, be defined as the OOF state.
7, video receiver coding/decoding method according to claim 6 is characterized in that, after searching correct frame swynchronization code 2 times at least, is defined as frame synchronization state.
8, video receiver coding/decoding method according to claim 5 is characterized in that, after searching wrong frame swynchronization code 2 times at least continuously, is defined as thinking the OOF state that enters.
9, video receiver coding/decoding method according to claim 5 is characterized in that, obtains frame synchronization by the frame synchronization state machine;
The frame synchronization state machine comprises OOF state, presynchronization state and 3 states of synchronous regime;
When current state was the OOF state, after searching correct frame swynchronization code for the first time, the frame synchronization state machine entered presynchronization state, otherwise is in the OOF state;
When current state is presynchronization state, after the frame synchronization state machine enters this state by the OOF state, search correct frame swynchronization code at least 1 time or continuous 2 times, the frame synchronization state machine enters synchronous regime; When searching the frame swynchronization code of 1 mistake, the frame synchronization state machine comes back to the OOF state;
When current state was frame synchronization state, after the frame synchronization state machine entered this state by presynchronization state, at least 1 time or search wrong frame swynchronization code for 2 times continuously, the frame synchronization state machine entered the OOF state, otherwise is in frame synchronization state.
10, video receiver coding/decoding method according to claim 4 is characterized in that,
The video data lowest order that is taken by asynchronous data or network management data in described 1 road video data replaces with fixed value 1 or 0;
Perhaps, replace with asynchronous data or network management data;
Perhaps, using the video data lowest order in a sampling period replaces.
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| CN103684736A (en) * | 2013-11-21 | 2014-03-26 | 国网上海市电力公司 | Clock synchronization method for high-speed communication |
| CN105706174A (en) * | 2013-11-04 | 2016-06-22 | 赛灵思公司 | SERDES receiver oversampling rate |
| CN103856763B (en) * | 2012-11-29 | 2017-09-29 | 常州华龙通信科技有限公司 | HDMI multiple business optical transmitter-receivers |
| CN110365991A (en) * | 2019-06-21 | 2019-10-22 | 武汉玉航科技有限公司 | A kind of synchronization mechanism applied in coding and decoding video |
| CN114416626A (en) * | 2021-11-22 | 2022-04-29 | 中国科学院西安光学精密机械研究所 | Asynchronous serial data recovery method based on 8B/10B coding |
-
2008
- 2008-12-31 CN CN2008102470364A patent/CN101459815B/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103856763B (en) * | 2012-11-29 | 2017-09-29 | 常州华龙通信科技有限公司 | HDMI multiple business optical transmitter-receivers |
| CN105706174A (en) * | 2013-11-04 | 2016-06-22 | 赛灵思公司 | SERDES receiver oversampling rate |
| CN105706174B (en) * | 2013-11-04 | 2019-08-27 | 赛灵思公司 | Serializer-deserializer system and oversampler method for serializer-deserializer system |
| CN103684736A (en) * | 2013-11-21 | 2014-03-26 | 国网上海市电力公司 | Clock synchronization method for high-speed communication |
| CN110365991A (en) * | 2019-06-21 | 2019-10-22 | 武汉玉航科技有限公司 | A kind of synchronization mechanism applied in coding and decoding video |
| CN114416626A (en) * | 2021-11-22 | 2022-04-29 | 中国科学院西安光学精密机械研究所 | Asynchronous serial data recovery method based on 8B/10B coding |
| CN114416626B (en) * | 2021-11-22 | 2024-04-12 | 中国科学院西安光学精密机械研究所 | Asynchronous serial data recovery method based on 8B/10B coding |
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