CN113722257B - B code analysis system based on domestic ARM - Google Patents
B code analysis system based on domestic ARM Download PDFInfo
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- CN113722257B CN113722257B CN202111034345.5A CN202111034345A CN113722257B CN 113722257 B CN113722257 B CN 113722257B CN 202111034345 A CN202111034345 A CN 202111034345A CN 113722257 B CN113722257 B CN 113722257B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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Abstract
The invention relates to a B code analysis system based on a domestic ARM, and belongs to the technical field of domestic communication time synchronization. Compared with the prior art, the invention adopts an autonomous and controllable nationwide production design and is not influenced by the forbidden foreign devices. The home-made ARM processor GD32F450 is used as an analysis chip, and the network switch is used for time distribution, so that the autonomous and controllable target is realized, the complexity of the system is reduced, the design is simplified, and the stability of the system is improved. The domestic network switch is adopted to distribute time information, which is different from the traditional distribution through serial ports, can effectively improve the distribution efficiency and reduce the delay on a transmission line. The analyzed time information is distributed to three interface devices through a network switch, so that multi-path redundancy backup is realized, and the time setting precision can reach microsecond level.
Description
Technical Field
The invention belongs to the technical field of domestic communication time synchronization, and particularly relates to a B code analysis system based on a domestic ARM.
Background
Currently, time synchronization, namely time synchronization, plays a significant role in many industrial fields, such as aerospace, power electronics and other systems, and the synchronous cooperative operation of the whole large system can be ensured only when time synchronization precision is required to reach microsecond level. The B code is used as an international universal time code and has the characteristics of universality and standardization. However, the existing B-code analysis system has the problems of complex design, low precision and poor working stability, and more importantly, cannot realize autonomous and controllable nationwide production design.
In order to meet the requirements of localization, realize high-precision decoding of B codes, reduce design complexity and improve system stability, a B code analysis system based on a domestic ARM needs to be designed.
Disclosure of Invention
First, the technical problem to be solved
The invention aims to solve the technical problems that: how to solve the problems of complex B code analysis system, poor stability and low time setting precision.
(II) technical scheme
In order to solve the technical problems, the invention provides a B code analysis system based on a domestic ARM, which comprises an ARM chip GD32F450 and a CPU chip 2K1000,GBE SWITCH chip SF2507EBI; the ARM chip GD32F450 receives external B code input through a DB9 serial port, then analyzes the B code, and distributes analyzed time information of year, month, day, time and second through the SF2507EBI of the GBE SWITCH chip, and the CPU chip 2K1000 receives the time information from the SF2507EBI of the GBE SWITCH chip through a network.
Preferably, the logic for implementing the B-code resolution for GD32F450 is as follows: the first timer inside the GD32F450 is used to detect the start bit of the B-code symbol, so as to detect a complete B-code symbol information; the second timer inside the GD32F450 is used to time the process of resolving the B code by the GD32F450 for later calibration of the B code; the network transceiver inside the GD32F450 is used to send the parsed time of year, month, day, and second information to the SF2507EBI of the GBE SWITCH chip for broadcasting.
Preferably, the ARM chip GD32F450 adopts an ARM Cortex-M4 32 bit processor core, and FLASH memory 3072KB and SRAM memory 512KB are integrated on a chip.
Preferably, the CPU chip 2K1000 adopts a 40nm technology, 2 GS264 processor cores are integrated in a chip, the main frequency is 1GHz, the shared 1MB secondary Cache, 2 x4 PCIE2.0 interfaces and 2 RGMII gigabit network interfaces of the DDR3 controller of 64 bit 533MHz are integrated in the chip.
Preferably, SF2507EBI of the GBE SWITCH chip is packaged by LQFP128-EPAD, supports 5+2 ports 10/100/1000M high performance Ethernet switching, and integrates 5 GigaPHY and 2 GMAC ports.
Preferably, the CPU chip 2K1000 is further configured to monitor the time information in real time by upper layer software.
Preferably, the external device may receive the time information from the SF2507EBI of the GBE SWITCH chip through an RJ45 portal or VPX bus.
The invention also provides a method for realizing B code analysis by using the system, which comprises the following steps:
step 1. The B code is sent to the ARM chip GD32F450 through a DB9 serial port;
Step 2, a first timer in the GD32F450 receives the B code information, and carries out timing inquiry, continuously detects whether a start mark of a B code symbol exists, if not, the timing inquiry is carried out all the time, and once the start mark of the B code symbol is inquired, the starting of a second timer is triggered;
step 3, when the second timer is started, analyzing the B code element by the GD32F450, analyzing the information of time, month, day and time seconds, simultaneously continuously detecting whether all the B code effective code elements in one second are analyzed by the GD32F450, if not, continuing analyzing, and once a completion mark is detected, triggering the second timer to stop timing;
Step 4, after the second timer stops counting, the GD32F450 calibrates the analyzed B code time information according to the counting time of the second timer;
And 5, for the time information after the calibration is completed, the GD32F450 calls the network transceiver to broadcast the analyzed time of year, month, day, minute and second to the network switch.
Preferably, the method further comprises step 6, wherein the external equipment obtains time information through the serial port and the internet port.
Preferably, the method further comprises the step 7 that the CPU 2K1000 monitors the time information through upper layer software in real time.
(III) beneficial effects
Compared with the prior art, the invention adopts an autonomous and controllable nationwide production design and is not influenced by the forbidden foreign devices. The home-made ARM processor GD32F450 is used as an analysis chip, and the network switch is used for time distribution, so that the autonomous and controllable target is realized, the complexity of the system is reduced, the design is simplified, and the stability of the system is improved. The domestic network switch is adopted to distribute time information, which is different from the traditional distribution through serial ports, can effectively improve the distribution efficiency and reduce the delay on a transmission line. The analyzed time information is distributed to three interface devices through a network switch, so that multi-path redundancy backup is realized, and the time setting precision can reach microsecond level.
Drawings
FIG. 1 is a schematic block diagram of a B-code resolution system on which a method embodying an embodiment of the present invention is based;
Fig. 2 is a B-code parsing schematic logic diagram based on which a method embodying an embodiment of the present invention is implemented.
Detailed Description
For the purposes of clarity, content, and advantages of the present invention, a detailed description of the embodiments of the present invention will be described in detail below with reference to the drawings and examples.
The method of the present invention is further described below in conjunction with the schematic block diagram of the B-code parsing system shown in fig. 1 and the schematic block diagram of the B-code parsing system shown in fig. 2.
In order to solve the defects of the existing B-code analysis technology, in particular to solve the problems of complex B-code analysis system, poor stability and low time setting precision, the invention realizes the nationwide design of the B-code analysis system on the basis of ensuring that the B-code time setting precision reaches microseconds, reduces the complexity of the design and improves the stability and the reliability of the system.
Specifically, the B code analysis system provided by the invention selects ARM chip GD32F450 of megainnovations, CPU chip 2K1000 of Beijing Loongson company, SF2507EBI of GBE SWITCH chip of Nanfei microelectronic company, and other peripheral serial ports, networks, buses and other all chips realize domestic design;
as shown in fig. 1, the B-code analysis system uses an ARM chip GD32F450 as a core, the ARM chip GD32F450 receives external B-code input through a DB9 serial port, then analyzes the B-code, and distributes analyzed time information of year, month, day, time, and second through an SF2507EBI of the GBE SWITCH chip, the CPU chip 2K1000 receives time information from the SF2507EBI of the GBE SWITCH chip through a network, and other external devices can receive time information from the SF2507EBI of the GBE SWITCH chip through an RJ45 network port or a VPX bus.
Furthermore, ARM chip GD32F450 of the megaly easy innovation company adopts ARM Cortex-M4 32 bit processor cores, FLASH storage 3072KB and SRAM storage 512KB are integrated on a chip, IO resources and peripheral interfaces are rich, and conventional standards and advanced communication requirements can be met.
Further, the CPU chip 2K1000 of Loongson company adopts a 40nm technology, 2 GS264 processor cores are integrated in a chip, the main frequency is 1GHz, the shared 1MB secondary Cache, 2 x4 PCIE2.0 interfaces of the 64-bit 533MHz DDR3 controller, 2 RGMII gigabit network interfaces and the like are integrated in a chip.
Further, SF2507EBI of the Phoaphis microelectronic company GBE SWITCH chip adopts LQFP128-EPAD package, supports 5+2 port 10/100/1000M high-performance Ethernet exchange, and integrates 5 low-power consumption characteristics GigaPHY and 2 GMAC ports.
Referring to fig. 2, the logic of the B-code parsing implemented by the gd32f450 is as follows: timer 1 inside GD32F450 detects the B-code symbol start bit to detect a complete B-code symbol information; the main purpose of the timer 2 is to time the process of analyzing the B code by the GD32F450 so as to calibrate the B code later; the network transceiver inside the GD32F450 is configured to send the parsed time information of year, month, day, time and second to the network SWITCH SF2507EBI of the GBE SWITCH chip for broadcasting, and the external device may acquire the time information through the serial port or the internet access, and in addition, the CPU chip 2K1000 may also monitor the time information through the upper layer software in real time.
As shown in fig. 2, the steps for implementing B-code analysis by using the above system are as follows:
step 1. The B code is sent to the ARM chip GD32F450 through a DB9 serial port;
Step 2, timer 1 in GD32F450 receives B code information, and carries on timing inquiry, whether there is a beginning sign of B code symbol or not is detected continuously, if not, inquiry is timed always, once the beginning sign of B code symbol is inquired, the start of timer 2 is triggered;
Step 3, when the timer 2 is started, analyzing the B code element by the GD32F450 to obtain the information of time, month, day, time and second, and meanwhile, continuously detecting whether all the B code effective code elements in one second are analyzed by the GD32F450, if not, continuing to analyze, and once a completion mark is detected, triggering the timer 2 to stop timing;
step 4, after the timer 2 stops counting, the GD32F450 calibrates the analyzed B code time information according to the counting time of the timer 2;
Step 5, for the time information after calibration is completed, the GD32F450 broadcasts the analyzed time, month, day, minute and second to a network switch by calling a network transceiver;
step 6, the external equipment obtains time information through the serial port and the network port;
and 7, the CPU 2K1000 operating system monitors time information in real time through upper software.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (9)
1. A B code analysis system based on domestic ARM is characterized by comprising an ARM chip GD32F450, a CPU chip 2K1000 and an SF2507EBI of a GBE SWITCH chip; the ARM chip GD32F450 receives external B code input through a DB9 serial port, then analyzes the B code, distributes analyzed time information of year, month, day, time and second through SF2507EBI of the GBE SWITCH chip, and the CPU chip 2K1000 receives the time information from the SF2507EBI of the GBE SWITCH chip through a network;
The logic for implementing the B-code parsing for GD32F450 is as follows: the first timer inside the GD32F450 is used to detect the start bit of the B-code symbol, so as to detect a complete B-code symbol information; the second timer inside the GD32F450 is used to time the process of resolving the B code by the GD32F450 for later calibration of the B code; the network transceiver inside the GD32F450 is used to send the parsed time of year, month, day, and second information to the SF2507EBI of the GBE SWITCH chip for broadcasting.
2. The system of claim 1, wherein the ARM chip GD32F450 employs an ARM Cortex-M4 32 bit processor core, integrated on-chip FLASH memory 3072KB and SRAM memory 512KB.
3. The system of claim 1, wherein the CPU chip 2K1000 employs a 40nm technology, integrates 2 GS264 processor cores on-chip, a main frequency of 1GHz, integrates a shared 1MB secondary Cache on-chip, a DDR3 controller of 64 bits 533MHz, 2 x4 PCIE2.0 interfaces, and 2 RGMII gigabit network interfaces.
4. The system of claim 1, wherein SF2507EBI of the GBE SWITCH chip employs LQFP128-EPAD packaging supporting 5+2 port 10/100/1000M high performance ethernet switching integrating 5 GigaPHY and 2 GMAC ports.
5. The system of claim 1, wherein the CPU chip 2K1000 is further configured to monitor the time information in real time by upper layer software.
6. The system of claim 1, wherein the external device receives the time information from SF2507EBI of the GBE SWITCH chip through an RJ45 portal or VPX bus.
7. A method for implementing B-code resolution using the system of any one of claims 1 to 6, comprising the steps of:
step 1, B codes are sent to an ARM chip GD32F450 through a DB9 serial port;
Step 2, a first timer in the GD32F450 receives the B code information, and carries out timing inquiry, continuously detects whether a start mark of a B code symbol exists, if not, the inquiry is always timed, and once the start mark of the B code symbol is inquired, the starting of a second timer is triggered;
Step 3, when the second timer is started, analyzing the B code element by the GD32F450, analyzing the information of time, month, day and time seconds, simultaneously continuously detecting whether all the B code effective code elements in one second are analyzed by the GD32F450, if not, continuing analyzing, and once a completion mark is detected, triggering the second timer to stop timing;
Step 4, after the second timer stops counting, the GD32F450 calibrates the analyzed B code time information according to the counting time of the second timer;
and 5, for the time information after the calibration is completed, the GD32F450 calls the network transceiver to broadcast the analyzed time of year, month, day, minute and second to the network switch.
8. The method of claim 7, further comprising step 6. The external device obtains time information via a serial port, a network port.
9. The method of claim 8, further comprising step 7. The CPU chip 2K1000 monitors the time information in real time by upper layer software.
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| CN204270025U (en) * | 2014-12-16 | 2015-04-15 | 天津天保电力有限公司 | There is the clock system of IRIG-B time adjustment function |
| CN205123755U (en) * | 2015-10-20 | 2016-03-30 | 天津七六四通信导航技术有限公司 | Be applied to B sign indicating number decoder module in electric power time service |
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- 2021-09-03 CN CN202111034345.5A patent/CN113722257B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078401A (en) * | 2012-12-17 | 2013-05-01 | 广东电网公司电力科学研究院 | Time synchronization and sampling synchronization system and method for transformer substation |
| CN204270025U (en) * | 2014-12-16 | 2015-04-15 | 天津天保电力有限公司 | There is the clock system of IRIG-B time adjustment function |
| CN205123755U (en) * | 2015-10-20 | 2016-03-30 | 天津七六四通信导航技术有限公司 | Be applied to B sign indicating number decoder module in electric power time service |
Non-Patent Citations (1)
| Title |
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| 一种IRIG-B码对时系统方案软硬件设计的研究;许仁安 等;《陕西电力》;20140720;91-93 * |
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