CN204906347U - Asymmetric radio frequency transceiving switch circuit - Google Patents
Asymmetric radio frequency transceiving switch circuit Download PDFInfo
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- CN204906347U CN204906347U CN201520509899.XU CN201520509899U CN204906347U CN 204906347 U CN204906347 U CN 204906347U CN 201520509899 U CN201520509899 U CN 201520509899U CN 204906347 U CN204906347 U CN 204906347U
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Abstract
The utility model provides a less size and lower cost have, good insertion loss has simultaneously, the asymmetric radio frequency transceiving switch circuit of the linearity and isolation, it includes antenna OUT, it still includes a MOS field effect transistor M1, the 2nd MOS field effect transistor M2, the 3rd MOS field effect transistor M3, fourth MOS field effect transistor M4, the 5th MOS field effect transistor M5, the 6th MOS field effect transistor M6, the 7th MOS field effect transistor M7, the 8th MOS field effect transistor M8, the 9th MOS field effect transistor M9, a MOS field effect transistor M1's D end, the 5th MOS field effect transistor M5's D end all are connected with antenna OUT, each MOS field effect transistor all is equipped with the double diode of P trap / dark N trap and dark N trap P substrate, and wherein dark N trap and P trap float in vain.
Description
Technical field
The utility model relates to radio-frequency receiving-transmitting switching circuit technical field, is specifically a kind of asymmetric radio-frequency receiving-transmitting switching circuit.
Background technology
In the burgeoning epoch of mobile phone in early days, most IC handheld device adopts GaAs (GaAs) technique.But, to low cost and and the demand of digital integration make research from GaAs technical change to complementary metal oxide semiconductors (CMOS) (CMOS) technology.Meanwhile, the performance requirement of required duplexer has become stricter, comprises lower insertion loss (IL), higher isolation, and higher power handling capability, the higher linearity, less size and lower cost.
Utility model content
Technical problem to be solved in the utility model is, overcomes the defect of prior art, provides a kind of and has less size and lower cost, has the asymmetric radio-frequency receiving-transmitting switching circuit of excellent insertion loss, the linearity and isolation simultaneously.
For solving the problems of the technologies described above, the utility model proposes a kind of asymmetric radio-frequency receiving-transmitting switching circuit, it comprises antenna OUT, and it also comprises the first metal-oxide-semiconductor field effect transistor M1, the second metal-oxide-semiconductor field effect transistor M2, the 3rd metal-oxide-semiconductor field effect transistor M3, the 4th metal-oxide-semiconductor field effect transistor M4, the 5th metal-oxide-semiconductor field effect transistor M5, the 6th metal-oxide-semiconductor field effect transistor M6, the 7th metal-oxide-semiconductor field effect transistor M7, the 8th metal-oxide-semiconductor field effect transistor M8, the 9th metal-oxide-semiconductor field effect transistor M9, after the G end series resistance R2 of the first metal-oxide-semiconductor field effect transistor M1, after the G end series resistance R3 of the second metal-oxide-semiconductor field effect transistor M2, after the G end series resistance R4 of the 3rd metal-oxide-semiconductor field effect transistor M3, all be connected with one end of resistance R1 after the G end series resistance R5 of the 4th metal-oxide-semiconductor field effect transistor M4, the other end of resistance R1 is connected with the first control signal end gate1, parallel resistance R6 between the D end of the first metal-oxide-semiconductor field effect transistor M1 and S end, parallel resistance R7 between the D end of the second metal-oxide-semiconductor field effect transistor M2 and S end, parallel resistance R8 between the D end of the 3rd metal-oxide-semiconductor field effect transistor M3 and S end, parallel resistance R9 between the D end of the 4th metal-oxide-semiconductor field effect transistor M4 and S end, resistance R6, resistance R7, resistance R8, resistance R9 sequentially connects, the S end of the 4th metal-oxide-semiconductor field effect transistor M4 is connected with transmitting terminal IN1, after the G end series resistance R11 of the 5th metal-oxide-semiconductor field effect transistor M5, after the G end series resistance R12 of the 6th metal-oxide-semiconductor field effect transistor M6, after the G end series resistance R13 of the 7th metal-oxide-semiconductor field effect transistor M7, after the G end series resistance R14 of the 8th metal-oxide-semiconductor field effect transistor M8, all be connected with one end of resistance R10 after the G end series resistance R15 of the 9th metal-oxide-semiconductor field effect transistor M9, the other end of resistance R10 is connected with the second control signal end gate2, parallel resistance R16 between the D end of the 5th metal-oxide-semiconductor field effect transistor M5 and S end, parallel resistance R17 between the D end of the 6th metal-oxide-semiconductor field effect transistor M6 and S end, parallel resistance R18 between the D end of the 7th metal-oxide-semiconductor field effect transistor M7 and S end, parallel resistance R19 between the D end of the 8th metal-oxide-semiconductor field effect transistor M8 and S end, parallel resistance R20 between the D end of the 9th metal-oxide-semiconductor field effect transistor M9 and S end, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20 sequentially connects, the S end of the 9th metal-oxide-semiconductor field effect transistor M9 is connected with receiving terminal IN2, the D end of the first metal-oxide-semiconductor field effect transistor M1, the D end of the 5th metal-oxide-semiconductor field effect transistor M5 are all connected with antenna OUT, each metal-oxide-semiconductor field effect transistor is equipped with the double diode of P trap/dark N trap and dark N trap/substrate P, wherein dark N trap and P trap floating.
After adopting said structure, compared with prior art, the utility model has the following advantages: the utility model proposes a kind of novel circuit structure design, by the asymmetry of design transmitting-receiving, can be received and be launched the radio-frequency (RF) index such as the isolation of the radio-frequency switch circuit required separately, insertion loss and the linearity respectively, not only there is less size and lower cost, there is excellent insertion loss, the linearity and isolation simultaneously.
As improvement, each metal-oxide-semiconductor field effect transistor is the MOS transistor of triple well structure, and the MOS transistor reparation technology due to triple well structure is stable ripe, so when producing in batches, quality is comparatively reliable and stable, thus is more conducive to the raising of the utility model stability and reliability.
As improvement, floating after the P trap series resistance R of each metal-oxide-semiconductor field effect transistor, like this, floating better effects if.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of the asymmetric radio-frequency receiving-transmitting switching circuit of the utility model.
Fig. 2 is the structural representation of the metal-oxide-semiconductor field effect transistor of the asymmetric radio-frequency receiving-transmitting switching circuit of the utility model.
Embodiment
Below the utility model is described in further detail:
The asymmetric radio-frequency receiving-transmitting switching circuit of the utility model, it comprises antenna OUT, and it also comprises the first metal-oxide-semiconductor field effect transistor M1, the second metal-oxide-semiconductor field effect transistor M2, the 3rd metal-oxide-semiconductor field effect transistor M3, the 4th metal-oxide-semiconductor field effect transistor M4, the 5th metal-oxide-semiconductor field effect transistor M5, the 6th metal-oxide-semiconductor field effect transistor M6, the 7th metal-oxide-semiconductor field effect transistor M7, the 8th metal-oxide-semiconductor field effect transistor M8, the 9th metal-oxide-semiconductor field effect transistor M9, after the G end series resistance R2 of the first metal-oxide-semiconductor field effect transistor M1, after the G end series resistance R3 of the second metal-oxide-semiconductor field effect transistor M2, after the G end series resistance R4 of the 3rd metal-oxide-semiconductor field effect transistor M3, all be connected with one end of resistance R1 after the G end series resistance R5 of the 4th metal-oxide-semiconductor field effect transistor M4, the other end of resistance R1 is connected with the first control signal end gate1, parallel resistance R6 between the D end of the first metal-oxide-semiconductor field effect transistor M1 and S end, parallel resistance R7 between the D end of the second metal-oxide-semiconductor field effect transistor M2 and S end, parallel resistance R8 between the D end of the 3rd metal-oxide-semiconductor field effect transistor M3 and S end, parallel resistance R9 between the D end of the 4th metal-oxide-semiconductor field effect transistor M4 and S end, resistance R6, resistance R7, resistance R8, resistance R9 sequentially connects, the S end of the 4th metal-oxide-semiconductor field effect transistor M4 is connected with transmitting terminal IN1, after the G end series resistance R11 of the 5th metal-oxide-semiconductor field effect transistor M5, after the G end series resistance R12 of the 6th metal-oxide-semiconductor field effect transistor M6, after the G end series resistance R13 of the 7th metal-oxide-semiconductor field effect transistor M7, after the G end series resistance R14 of the 8th metal-oxide-semiconductor field effect transistor M8, all be connected with one end of resistance R10 after the G end series resistance R15 of the 9th metal-oxide-semiconductor field effect transistor M9, the other end of resistance R10 is connected with the second control signal end gate2, parallel resistance R16 between the D end of the 5th metal-oxide-semiconductor field effect transistor M5 and S end, parallel resistance R17 between the D end of the 6th metal-oxide-semiconductor field effect transistor M6 and S end, parallel resistance R18 between the D end of the 7th metal-oxide-semiconductor field effect transistor M7 and S end, parallel resistance R19 between the D end of the 8th metal-oxide-semiconductor field effect transistor M8 and S end, parallel resistance R20 between the D end of the 9th metal-oxide-semiconductor field effect transistor M9 and S end, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20 sequentially connects, the S end of the 9th metal-oxide-semiconductor field effect transistor M9 is connected with receiving terminal IN2, the D end of the first metal-oxide-semiconductor field effect transistor M1, the D end of the 5th metal-oxide-semiconductor field effect transistor M5 are all connected with antenna OUT, each metal-oxide-semiconductor field effect transistor is equipped with the double diode of P trap/dark N trap and dark N trap/substrate P, wherein dark N trap and P trap floating.
Each metal-oxide-semiconductor field effect transistor is the MOS transistor of triple well structure.
Floating after the P trap series resistance R of each metal-oxide-semiconductor field effect transistor.
The linearity of switch, the i.e. power handling capability of switch, represent with P1dB usually, and two factors affecting the cmos switch linearity are: the metal-oxide-semiconductor generation conducting of cut-off and metal-oxide-semiconductor gate-dielectric performance stable not.
The application is by the circuit in Fig. 1, at traditional string and Structure Receive end and transmitting terminal increase different metal-oxide-semiconductor field effect transistors, transmitting terminal is 4, receiving terminal is 5, be used for fully meeting the different demands of signal at reiving/transmitting state, can meet in the satisfactory situation of insertion loss simultaneously, improve the isolation of switch.Wherein OUT, IN1 and IN2 are respectively the antenna of radio-frequency (RF) switch, and transmitting and receiving port, it is complementary voltage that gate1 and gate2 is respectively the control signal controlling radio-frequency (RF) switch, and DNW is dark N trap.The radiofrequency signal of long arc may cause the grid G-source S of single-transistor or grid G-to leak D junction breakdown.By increasing a large resistance in the grid G of each FET, as shown in Figure 1, grid G current potential by unsettled and with source S and drain D ground.Be combined in the negative voltage bias voltage of off state, this grid G current potential can by bootstrapping to the current potential of source/drain, and this not only prevents radio frequency signal leakage to AC earth, also add each FET from VT-Vgs to the voltage handling ability of 2 (VT-Vgs).In addition, each metal-oxide-semiconductor has a large resistance to stride across source/drain two ends, and to prevent any direct voltage from flowing through from superposition metal-oxide-semiconductor, this contributes to guaranteeing that voltage drop is uniformly distributed each being in the metal-oxide-semiconductor of off state.
In FIG, adopt at present comparatively conventional for noise decrease and improve isolation performance the mixed signal technique with triple-well to design novel radio-frequency switch circuit, 2 that utilize it to produce extra parasitic diodes: P trap and dark N trap diode, dark N trap and substrate P diode, depict the circuit of the double diode of P trap/dark N trap and dark N trap/substrate P, in the utility model, adopt the method for designing of dark N trap and P trap dual suspension to realize large linearity index specially to improve the linearity, simultaneously owing to being floating state, when metal-oxide-semiconductor conducting, the parasitic capacitance of source body and leakage body can not have an impact to insertion loss.
The above is only better embodiment of the present utility model, therefore all equivalences done according to structure, feature and the principle described in the utility model patent claim change or modify, and are included in the utility model patent claim.
Claims (3)
1. an asymmetric radio-frequency receiving-transmitting switching circuit, it comprises antenna OUT, it is characterized in that, it also comprises the first metal-oxide-semiconductor field effect transistor M1, the second metal-oxide-semiconductor field effect transistor M2, the 3rd metal-oxide-semiconductor field effect transistor M3, the 4th metal-oxide-semiconductor field effect transistor M4, the 5th metal-oxide-semiconductor field effect transistor M5, the 6th metal-oxide-semiconductor field effect transistor M6, the 7th metal-oxide-semiconductor field effect transistor M7, the 8th metal-oxide-semiconductor field effect transistor M8, the 9th metal-oxide-semiconductor field effect transistor M9, after the G end series resistance R2 of the first metal-oxide-semiconductor field effect transistor M1, after the G end series resistance R3 of the second metal-oxide-semiconductor field effect transistor M2, after the G end series resistance R4 of the 3rd metal-oxide-semiconductor field effect transistor M3, all be connected with one end of resistance R1 after the G end series resistance R5 of the 4th metal-oxide-semiconductor field effect transistor M4, the other end of resistance R1 is connected with the first control signal end gate1, parallel resistance R6 between the D end of the first metal-oxide-semiconductor field effect transistor M1 and S end, parallel resistance R7 between the D end of the second metal-oxide-semiconductor field effect transistor M2 and S end, parallel resistance R8 between the D end of the 3rd metal-oxide-semiconductor field effect transistor M3 and S end, parallel resistance R9 between the D end of the 4th metal-oxide-semiconductor field effect transistor M4 and S end, resistance R6, resistance R7, resistance R8, resistance R9 sequentially connects, the S end of the 4th metal-oxide-semiconductor field effect transistor M4 is connected with transmitting terminal IN1, after the G end series resistance R11 of the 5th metal-oxide-semiconductor field effect transistor M5, after the G end series resistance R12 of the 6th metal-oxide-semiconductor field effect transistor M6, after the G end series resistance R13 of the 7th metal-oxide-semiconductor field effect transistor M7, after the G end series resistance R14 of the 8th metal-oxide-semiconductor field effect transistor M8, all be connected with one end of resistance R10 after the G end series resistance R15 of the 9th metal-oxide-semiconductor field effect transistor M9, the other end of resistance R10 is connected with the second control signal end gate2, parallel resistance R16 between the D end of the 5th metal-oxide-semiconductor field effect transistor M5 and S end, parallel resistance R17 between the D end of the 6th metal-oxide-semiconductor field effect transistor M6 and S end, parallel resistance R18 between the D end of the 7th metal-oxide-semiconductor field effect transistor M7 and S end, parallel resistance R19 between the D end of the 8th metal-oxide-semiconductor field effect transistor M8 and S end, parallel resistance R20 between the D end of the 9th metal-oxide-semiconductor field effect transistor M9 and S end, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20 sequentially connects, the S end of the 9th metal-oxide-semiconductor field effect transistor M9 is connected with receiving terminal IN2, the D end of the first metal-oxide-semiconductor field effect transistor M1, the D end of the 5th metal-oxide-semiconductor field effect transistor M5 are all connected with antenna OUT, each metal-oxide-semiconductor field effect transistor is equipped with the double diode of P trap/dark N trap and dark N trap/substrate P, wherein dark N trap and P trap floating.
2. asymmetric radio-frequency receiving-transmitting switching circuit according to claim 1, it is characterized in that, each metal-oxide-semiconductor field effect transistor is the MOS transistor of triple well structure.
3. asymmetric radio-frequency receiving-transmitting switching circuit according to claim 1, is characterized in that, floating after the P trap series resistance R of each metal-oxide-semiconductor field effect transistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520509899.XU CN204906347U (en) | 2015-07-14 | 2015-07-14 | Asymmetric radio frequency transceiving switch circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520509899.XU CN204906347U (en) | 2015-07-14 | 2015-07-14 | Asymmetric radio frequency transceiving switch circuit |
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| CN204906347U true CN204906347U (en) | 2015-12-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105187038A (en) * | 2015-07-14 | 2015-12-23 | 海宁海微电子科技有限公司 | Asymmetric RF transceiver switch circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105187038A (en) * | 2015-07-14 | 2015-12-23 | 海宁海微电子科技有限公司 | Asymmetric RF transceiver switch circuit |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151223 Termination date: 20190714 |