CN204859381U - Based on FPGA video processing multiresolution conversion module and video processing system - Google Patents
Based on FPGA video processing multiresolution conversion module and video processing system Download PDFInfo
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- CN204859381U CN204859381U CN201520660652.8U CN201520660652U CN204859381U CN 204859381 U CN204859381 U CN 204859381U CN 201520660652 U CN201520660652 U CN 201520660652U CN 204859381 U CN204859381 U CN 204859381U
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Abstract
The utility model is suitable for a video image processing technology field. The utility model discloses based on FPGA video processing multiresolution conversion module, including FPGA module and VIP video processing module, wherein video processing module including the video of real -time configuration input effective go with the controller module of row, change into the BT1120 video flowing of standard the video input module of avalon -ST video flowing, cut into the sanction shear die piece of output equal proportion size output with the video of input, the module of handling of zooming is zoomed to video after will cuting, carries out the frame cache module of buffer memory to the video after zooming, changes the avalon -ST circulation output module of the BT1120 video flowing of standard into, video memory after the storage is zoomed. Because multiresolution conversion module can export different standards and differentiate, therefore can adapt to different playback devices broadcast demand, avoid video data input and the playback devices circumstances of mismatching under video smoothness nature compatible with the definition, improve video result of broadcast and quality.
Description
Technical field
The utility model relates to technical field of video image processing, particularly relates to a kind of based on FPGA Video processing multiresolution modular converter and processing system for video.
Background technology
In actual applications, the needs of back-end client often can not be met from movement video formats out, for example at pc client, during with USB2.0 interface, the input of video source maximum support 1280*72025hz, and when network environment difference, in order to the fluency of transmission of video, often substitute with the resolution of sacrificing video, the video size of such as 640*480 or lower CIF size.When from movement out be all the video source of high definition time, just need video HD video being converted to VGA size resolution.Again for example, when live one side recorded broadcast on one side, often live scene needs to use HD video and shows, recorded broadcast transmission needs SD video, this just needs to carry out the conversion of high definition to SD to the HD video source of movement, thus reaching the object not only exporting high definition but also export SD, the output therefore realizing multiresolution in meeting camera is necessary.
Summary of the invention
The technical problem that the utility model mainly solves is to provide a kind of based on FPGA Video processing multiresolution modular converter and processing system for video, video data should can be avoided to input and video fluency under playback equipment not match condition and definition compatibility based on FPGA Video processing multiresolution modular converter, improve video display effect and quality.
In order to solve the problems of the technologies described above, the utility model provides a kind of based on FPGA Video processing multiresolution modular converter, should comprise based on FPGA Video processing multiresolution modular converter: for exporting the FPGA module of multiresolution and multiplex roles video frequency output, the video processing module of multiresolution configuration, wherein said VIP video processing module comprises
Soft nuclear control device, the video of configuration input in real time is effectively gone and effectively row realize multi input configuration;
Video input module, changes into Avalon-ST video flowing by the BT1120 video flowing of standard;
Cutting module, becomes to export the output of equal proportion size by the vide clip of input;
Zoom module, carries out convergent-divergent process by the video after shearing;
Frame buffer module, carries out buffer memory to the video after convergent-divergent;
Video Output Modules, changes the BT1120 video flowing of standard into by Avalon-ST circulation;
Memory, is connected the video after storing convergent-divergent with frame buffer module.
Say further, the interface type of described Video Output Modules, frame buffer module, Zoom module, cutting module, controller module and video input module is all Avalon-ST.
The utility model also provides a kind of processing system for video, this processing system for video comprises: imageing sensor and the dsp processor be connected with this imageing sensor, this dsp processor is connected with FPGA process chip and is connected with ARM controller by UART respectively, and described FPGA process chip sends chip with SDI respectively by data/address bus, USB3.0 transmits chip, HDMI sends chip, YPBPR coding chip and the CVBS coding chip that digital signal converted to analog signal are connected.
Say further, described SDI sends chip and adopts model to be GV7600.
Say further, described USB3.0 transmits chip and adopts the chip that model is CY3014.
The utility model is based on FPGA Video processing multiresolution modular converter, comprise FPGA module and VIP video processing module, wherein said VIP video processing module comprises, soft nuclear control device, the effective row and column of video of real-time configuration input realizes multi input configuration, and this soft-core processor adopts NiosII processor; Video input module, changes into Avalon-ST video flowing by the BT1120 video flowing of standard; Cutting module, becomes to export the output of equal proportion size by the vide clip of input; Zoom module, carries out convergent-divergent process by the video after shearing; Frame buffer module, carries out buffer memory to the video after convergent-divergent; Output module, changes the BT1120 video flowing of standard into by Avalon-ST circulation; Memory, is connected the video after storing convergent-divergent with frame buffer module.Differentiate because multiresolution modular converter can export different systems, thus can adapt to different playback equipment and play demand, avoid video data to input and video fluency under playback equipment not match condition and definition compatibility, improve video display effect and quality.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, and the accompanying drawing in describing is embodiments more of the present utility model, to those skilled in the art, under the prerequisite not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is based on FPGA Video processing multiresolution modular converter embodiment principle schematic.
Fig. 2 is processing system for video embodiment schematic diagram.
Below in conjunction with embodiment, and with reference to accompanying drawing, the realization of the utility model object, functional characteristics and advantage are described further.
Embodiment
In order to make the object of utility model, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the utility model embodiment, technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belongs to the scope of the utility model protection.
As shown in Figure 1, the utility model provides a kind of embodiment based on FPGA Video processing multiresolution modular converter embodiment.
Should comprise based on FPGA Video processing multiresolution modular converter: FPGA module and video processing module, wherein said video processing module comprises, soft-core processor 1, and the video of configuration input in real time is effectively gone and effectively row realize multi input configuration; Video input module 2, changes into Avalon-ST video flowing by the BT1120 video flowing of standard; Cutting module 3, becomes to export the output of equal proportion size by the vide clip of input; Zoom module 4, carries out convergent-divergent process by the video after shearing; Frame buffer module 5, carries out buffer memory to the video after convergent-divergent; Video Output Modules 6, changes the BT1120 video flowing of standard into by Avalon-ST circulation; Memory 7, stores the video after convergent-divergent.
Specifically, HD video enters FPGA module with the form of bt1120, because in Video processing bag, the interface type of modules is all Avalon-ST, namely the interface type of described soft-core processor 1, video input module 2, cutting module 3, Zoom module 4, frame buffer module 5 and Video Output Modules 6 is all Avalon-ST, therefore HD video is first through video input module 2, and the BT1120 video flowing of standard is changed into Avalon-ST video flowing; Soft-core processor 1 configures video effectively row and effective row of input in real time by Avalon-MM interface, completes multi input configuration; The vide clip of input is become to export the output of equal proportion size by cutting module 3 according to the output demand of designer, such as input source is 1280*720(16:9), require to export as 640*480(4:3), then need 1280*720(16:9) resolution cut into 960*720(4:3) just can be unlikely to be out of shape on the display of 4:3; The function of Zoom module 4 is that the video after shearing is carried out convergent-divergent process, reach and export expection, altera provides Nearestneighbor, Bilinear, PolyphaseandBicubic, Edge-Adaptivescaling tetra-kinds of convergent-divergent algorithms for designer, selects according to different application field and resource service condition; Frame buffer module 5, carries out buffer memory to the video after convergent-divergent, video is left in the conversion completing frame per second in ddr2 external memory storage; Video Output Modules 6 is BT1120 video flowing Avalon-ST circulation being changed into standard, and after this module, the video of output is the resolution of client requirements.
Differentiate because multiresolution modular converter can export different systems, thus can adapt to different playback equipment and play demand, avoid video data to input and video fluency under playback equipment not match condition and definition compatibility, improve video display effect and quality.
As described in Figure 2, the utility model also provides a kind of processing system for video embodiment.
This processing system for video comprises: imageing sensor 100 and the dsp processor 101 be connected with this imageing sensor 100, this dsp processor 101 is connected with FPGA process chip 103 respectively and passes through UART(UniversalAsynchronousReceiver/Transmitter, universal asynchronous receiving-transmitting transmitter) be connected with ARM controller 102, described FPGA process chip 103 sends chip 104 with SDI respectively by data/address bus, USB3.0 transmits chip 105, HDMI sends chip 106, YPBPR coding chip 107 is connected with the CVBS coding chip 108 digital signal being converted to analog signal.
Specifically, described FPGA process chip 103 adopts NiosII processor; Described USB3.0 transmits chip 105 and adopts the model of cypress company to be the chip of CY3014, and the input interface bit wide of CY3014 chip can be configured to 8bit, 16bit, 24bit and 32bit, and speed can reach 100Mhz.Because the video bit wide transmitting 108060Hz is 16bit, speed 148.5Mhz, therefore must at the inner video video of 16bit148.5Mhz being become 32bit74.25Mhz of FPGA module.
This function can be completed with a FIFO in FPGA process chip 103 inside, the input bit wide of FIFO is set to 16bit, input clock frequency is set to 148.5Mhz, the output bit wide of FIFO is set to 32bit, output clock set of frequency is 74.25Mhz, the written request signal that the degree of depth of FIFO is set to 128, FIFO shows effect, using 8 clock cycle of written request signal time delay as reading request signal for the effective & of row.
Described FPGA process chip 103 sends chip 104 with SDI respectively by data/address bus, USB3.0 transmits chip 105, HDMI sends chip 106, YPBPR coding chip 107 and CVBS coding chip 108 are connected.Described SDI sends the GV7600 that chip 104 adopts Gennum company; this SDI sends the BT1120 data that chip 104 receives 16bit, only needs configuration pin E3 and E4 can realize the reception of vision signal, when the video pixel clock received is 74.25Mhz(1080P30hz; 1080P25hz; 1080I60hz, 1080I50hz, 720P60hz; 720P50hz; 720P30hz, 720P25hz) time, pin E3 and pin E4 is configured to low level; When the video pixel clock received is 148.5Mhz(1080P60hz, 1080P50hz) time, pin E4 is configured to high level, pin E3 is configured to low level.
The input of YPBPR coding chip 107 that described HDMI sends chip 106 and digital signal converted to analog signal is all the BT1120 data of standard, is configured by I2C bus.In NiosII, adopt two PIO mouths to carry out analogue I2C bus, when machine powers on and video format switches, first chip is resetted, and then carry out the configuration of corresponding format according to address of devices.
The input video source that described CVBS coding chip 108 receives is the 8bit data of standard BT656 form, is also configured by I2C bus.BT656 data can have multiresolution modular converter to obtain.
Above embodiment only in order to the technical solution of the utility model to be described, is not intended to limit; Although be described in detail the utility model with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or equivalent replacement is carried out to wherein portion of techniques feature, and these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (5)
1., based on FPGA Video processing multiresolution modular converter, comprise the video processing module of the FPGA module for exporting multiresolution and multiplex roles video frequency output, multiresolution configuration, wherein said video processing module comprises,
Soft nuclear control device, the video of configuration input in real time is effectively gone and effectively row realize multi input configuration;
Video input module, changes into Avalon-ST video flowing by the BT1120 video flowing of standard;
Cutting module, becomes to export the output of equal proportion size by the vide clip of input;
Zoom module, carries out convergent-divergent process by the video after shearing;
Frame buffer module, carries out buffer memory to the video after convergent-divergent;
Video Output Modules, changes the BT1120 video flowing of standard into by Avalon-ST circulation;
Memory, frame buffer module connects the video after storing convergent-divergent.
2. according to claim 1 based on FPGA Video processing multiresolution modular converter, it is characterized in that, the interface type of described Video Output Modules, frame buffer module, Zoom module, cutting module, controller module and video input module is all Avalon-ST.
3. processing system for video, the dsp processor comprising imageing sensor and be connected with this imageing sensor, this dsp processor is connected with FPGA process chip and is connected with ARM controller by UART respectively, and described FPGA process chip sends chip with SDI respectively by data/address bus, USB3.0 transmits chip, HDMI sends chip, YPBPR coding chip and the CVBS coding chip that digital signal converted to analog signal are connected.
4. according to the processing system for video shown in claim 3, it is characterized in that: described SDI sends chip and adopts model to be GV7600.
5. the processing system for video according to claim 3 or 4, is characterized in that: described USB3.0 transmits chip and adopts the chip that model is CY3014.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107147890A (en) * | 2017-05-11 | 2017-09-08 | 西安交通大学 | The many video scaling modules and concurrent working method of a kind of compatible different resolution and breadth length ratio |
| CN109743520A (en) * | 2019-01-14 | 2019-05-10 | 苏州长风航空电子有限公司 | A kind of multipath resolution dynamic self-adapting Airborne Video Recording System |
| CN110475142A (en) * | 2019-08-16 | 2019-11-19 | 福州大学 | A kind of 3G-SDI data-flow conversion method based on FPGA |
| CN112383732A (en) * | 2020-12-09 | 2021-02-19 | 上海移远通信技术股份有限公司 | Signal transmission system and method with adaptive resolution |
| CN113596373A (en) * | 2021-07-28 | 2021-11-02 | 成都卓元科技有限公司 | 8K video processing architecture for converting 12G-SDI into HDMI2.1 |
| CN116456144A (en) * | 2023-06-14 | 2023-07-18 | 合肥六角形半导体有限公司 | Frame-free cache video stream processing output device and method |
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2015
- 2015-08-30 CN CN201520660652.8U patent/CN204859381U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107147890A (en) * | 2017-05-11 | 2017-09-08 | 西安交通大学 | The many video scaling modules and concurrent working method of a kind of compatible different resolution and breadth length ratio |
| CN109743520A (en) * | 2019-01-14 | 2019-05-10 | 苏州长风航空电子有限公司 | A kind of multipath resolution dynamic self-adapting Airborne Video Recording System |
| CN110475142A (en) * | 2019-08-16 | 2019-11-19 | 福州大学 | A kind of 3G-SDI data-flow conversion method based on FPGA |
| CN112383732A (en) * | 2020-12-09 | 2021-02-19 | 上海移远通信技术股份有限公司 | Signal transmission system and method with adaptive resolution |
| CN112383732B (en) * | 2020-12-09 | 2023-08-04 | 上海移远通信技术股份有限公司 | Resolution adaptive signal transmission system and method |
| CN113596373A (en) * | 2021-07-28 | 2021-11-02 | 成都卓元科技有限公司 | 8K video processing architecture for converting 12G-SDI into HDMI2.1 |
| CN116456144A (en) * | 2023-06-14 | 2023-07-18 | 合肥六角形半导体有限公司 | Frame-free cache video stream processing output device and method |
| CN116456144B (en) * | 2023-06-14 | 2023-09-26 | 合肥六角形半导体有限公司 | Frame-free cache video stream processing output device and method |
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