CN201974795U - Image mosaic processing device based on field programmable gate array (FPGA) - Google Patents
Image mosaic processing device based on field programmable gate array (FPGA) Download PDFInfo
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- CN201974795U CN201974795U CN2010206973581U CN201020697358U CN201974795U CN 201974795 U CN201974795 U CN 201974795U CN 2010206973581 U CN2010206973581 U CN 2010206973581U CN 201020697358 U CN201020697358 U CN 201020697358U CN 201974795 U CN201974795 U CN 201974795U
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Abstract
The utility model relates to an image mosaic processing device based on a field programmable gate array (FPGA), which is characterized in that the image mosaic processing device comprises a group of digital visual interface (DVI) digital decoding circuits, a group of FPGA digital video processing circuits and a group of output interface circuits, external digital signals are connected with the DVI digital decoding circuits, decoding processing is conducted to digital video signals in a form of minimum transformation differential signals to obtain a video pixel information stream which is directly fed into the FPGA digital video processing circuits, after an image processing algorithm is conducted, encoding processing is conducted to the signals to obtain digital video signals in a form of minimum differential signals, and finally the digital video signals are output to splicing wall displays through the output interface circuits. The image mosaic processing device based on the FPGA has the advantages that the limitation to a splicing scale is broken through and the splicing quantity is theoretically limitless; the splitting of real-time digital videos and the interpolation amplification of video images are realized, and the processing speed and the response speed can be effectively improved; and the application demand of continuous expansion in the field of stream media video signals, especially high-definition video signals, is met.
Description
Technical field
The utility model relates to a kind of image mosaic treating apparatus based on FPGA.
Background technology
At present, because the progress of computing machine display technique and digital visual interface standard is universal day by day, extract with the requirement of digitized processing more and more higher to the DVI digital video signal.Particularly at present more and more obvious to the dependence of streaming media video signal aspect, especially in the high definition field.Traditional pci bus pattern obviously can't satisfy the demands, and its space that at first is subjected to bandwidth bottleneck and development is very little.Though embedded pattern has certain progress, also relatively be short of in the processing power aspect splicing processing, signal source management and the network especially Streaming Media.
Meanwhile, programmable logic device (PLD) FPGA constantly updates, and its internal logic resource and speed class improve constantly, and can satisfy hardware realization fast and parallel processing, to solve the problem that video processing speed restriction and various criterion merge.Thereby for processing video real-time, that walk abreast has brought new solution route.
The utility model content
The purpose of this utility model provides a kind of image mosaic treating apparatus based on FPGA, makes its restriction that promptly is not subjected to the pci bus bandwidth do not gathered restriction with the processing power aspect again.
In order to achieve the above object, a technical scheme of the present utility model has provided a kind of image mosaic treating apparatus based on FPGA, it is characterized in that, comprise one group of DVI digital decoding circuit, one group of FPGA Digital Video Processing circuit and one group of output interface circuit, wherein external digital signal links to each other with DVI digital decoding circuit, digital video signal to minimum translation difference sub-signal form carries out decoding processing, the video pixel information flow that obtains is directly sent into FPGA Digital Video Processing circuit, through behind the image processing algorithm, again signal is carried out encoding process, obtain the digital video signal of minimum differential signal, output to the combination display through output interface circuit.
The utility model has the advantages that: break through the restriction of splicing scale, make splicing quantity reach unlimited in theory; Realize that the interpolation of the cutting apart of real-time digital video, video image amplifies, a kind of collection and treating apparatus of video stream media is provided.Simultaneously the DVI digital signal is extracted, the video data and the signal source of algorithm process are consistent, and avoid the loss of signal in the signal D/A conversion; Utilize parallel processing technique in the FPGA indoor design, can effectively improve and handle and response speed, and unified the external interface of screen splicing application system hardware to DVI digital video display interface; Satisfy the especially application demand of the continuous expansion in high definition field of streaming media video signal simultaneously.
Description of drawings
Fig. 1 is based on the image mosaic treating apparatus theory diagram of FPGA;
Fig. 2 is FPGA internal logic structure figure.
Embodiment
Specify the utility model below in conjunction with embodiment.
Embodiment
As shown in Figures 1 and 2, the utility model provides a kind of image mosaic treating apparatus based on FPGA, comprise one group of DVI digital decoding circuit, one group of FPGA Digital Video Processing circuit and one group of output interface circuit, wherein external digital signal links to each other with DVI digital decoding circuit, digital video signal to minimum translation difference sub-signal form carries out decoding processing, the video pixel information flow that obtains is directly sent into FPGA Digital Video Processing circuit, through behind the image processing algorithm, again signal is carried out encoding process, obtain the digital video signal of minimum differential signal, output to the combination display through output interface circuit.
Described output interface circuit comprises one group of DVI numerical coding circuit and one group of DVI interface, outputs to described combination display by the DVI interface behind the digital video signal process DVI numerical coding circuit code of described FPGA Digital Video Processing circuit output.
Described FPGA Digital Video Processing circuit comprises video input module, the Video Segmentation module, video interpolating module and video output module, video input module receives the video pixel information flow of sending from described DVI digital decoding circuit and changes pretreated video pixel stream format into, the Video Segmentation module is cut apart cutting with the video pixel information flow that obtains, obtain the complete sub-video pixel stream of multichannel, and control the mutual sequential relationship that each way video shows, the video interpolating module carries out M * N interpolation processing and amplifying doubly to each way video pixel stream, and each the way video pixel stream after the video output module then will amplify is sent to described output interface circuit.
Claims (3)
1. image mosaic treating apparatus based on FPGA, it is characterized in that, comprise one group of DVI digital decoding circuit, one group of FPGA Digital Video Processing circuit and one group of output interface circuit, wherein external digital signal links to each other with DVI digital decoding circuit, digital video signal to minimum translation difference sub-signal form carries out decoding processing, the video pixel information flow that obtains is directly sent into FPGA Digital Video Processing circuit, through behind the image processing algorithm, again signal is carried out encoding process, obtain the digital video signal of minimum differential signal, output to the combination display through output interface circuit.
2. a kind of image mosaic treating apparatus as claimed in claim 1 based on FPGA, it is characterized in that, described output interface circuit comprises one group of DVI numerical coding circuit and one group of DVI interface, outputs to described combination display by the DVI interface behind the digital video signal process DVI numerical coding circuit code of described FPGA Digital Video Processing circuit output.
3. a kind of image mosaic treating apparatus based on FPGA as claimed in claim 1 is characterized in that described FPGA Digital Video Processing circuit comprises video input module, Video Segmentation module, video interpolating module and video output module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206973581U CN201974795U (en) | 2010-12-31 | 2010-12-31 | Image mosaic processing device based on field programmable gate array (FPGA) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206973581U CN201974795U (en) | 2010-12-31 | 2010-12-31 | Image mosaic processing device based on field programmable gate array (FPGA) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201974795U true CN201974795U (en) | 2011-09-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206973581U Expired - Lifetime CN201974795U (en) | 2010-12-31 | 2010-12-31 | Image mosaic processing device based on field programmable gate array (FPGA) |
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| CN (1) | CN201974795U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102724477A (en) * | 2012-05-25 | 2012-10-10 | 黑龙江大学 | Device and method for carrying out real-time splicing on surveillance videos based on FPGA (field programmable gata array) |
| CN105979164A (en) * | 2016-05-31 | 2016-09-28 | 罗杰 | System for seamless real-time zooming multi-screen picture |
| CN111913676A (en) * | 2020-07-31 | 2020-11-10 | 宁波Gqy视讯股份有限公司 | Control system and method of LED spliced screen and splicing processor |
-
2010
- 2010-12-31 CN CN2010206973581U patent/CN201974795U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102724477A (en) * | 2012-05-25 | 2012-10-10 | 黑龙江大学 | Device and method for carrying out real-time splicing on surveillance videos based on FPGA (field programmable gata array) |
| CN105979164A (en) * | 2016-05-31 | 2016-09-28 | 罗杰 | System for seamless real-time zooming multi-screen picture |
| CN111913676A (en) * | 2020-07-31 | 2020-11-10 | 宁波Gqy视讯股份有限公司 | Control system and method of LED spliced screen and splicing processor |
| CN111913676B (en) * | 2020-07-31 | 2023-01-31 | 宁波Gqy视讯股份有限公司 | Control system and method of LED spliced screen and splicing processor |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110914 |
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| CX01 | Expiry of patent term | ||
| DD01 | Delivery of document by public notice |
Addressee: Liu Hong Document name: Notice of expiration of patent right |
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| DD01 | Delivery of document by public notice |