CN204836400U - Embedded multi -functional video interface module - Google Patents
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- CN204836400U CN204836400U CN201520531362.3U CN201520531362U CN204836400U CN 204836400 U CN204836400 U CN 204836400U CN 201520531362 U CN201520531362 U CN 201520531362U CN 204836400 U CN204836400 U CN 204836400U
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Abstract
The utility model relates to an embedded multi -functional video interface module, including power module, global clock module, video AD conversion module, video DA conversion module, FPGA, SDI coding module, cameraLink interface circuit, output data drive module and serial ports drive circuit, power module supplies power to FPGA, the global clock module provides global clock the signal to FPGA, video AD conversion module and FPGA are connected, video data, line signal, a signal, clock signal that video DA conversion module will come from FPGA convert simulation PAL -system CVBS signal output into, the SDI coding module is connected with FPGA, and TTL signal that serial ports drive circuit received converts the received signal into 8 data according to the desired communication protocol of RS485 and supplies FPGA chip image processing to use. The utility model discloses small, the light in weight of video interface module, about 150 grams.
Description
Technical field
The utility model relates to a kind of video interface module of embedded type multifunctional.
Background technology
This video interface module mainly for: the decoding data of (1) industry high speed CameraLink digital camera becomes 80 bit data, and issues by kerve the real-time tracking that polylith video tracking plate carries out High-speed video images.(2) this module to from industry high speed CameraLink digital camera decoding data, take out frame and high-speed figure image conversion Phase Alternation Line system and the display of SDI (single-definition) digital picture.(3) this module is with fpga chip, can complete the character adding of video image, the function such as maximum, average, minimum value of real-time statistics video image.(4) this module has a road CVBS decoding input, and a road video d/a exports, the functions such as a road SDI output.(5) this module is with video frequency output power drive function, and support pal video, transmission range reaches 10 meters.(6) this module supports RS485 communication function, can complete the RS485 serial communication of this plate and external system.
Summary of the invention
The utility model discloses a kind of video interface module based on embedded type multifunctional.
Technical solution of the present utility model:
A video interface module for embedded type multifunctional, its special character is: comprise power module, global clock module, video A/D conversion module, video D/A conversion module, FPGA, SDI coding module, CameraLink interface circuit, export data-driven module and serial port drive circuit;
Described power module is powered to FPGA;
Described global clock module provides global clock signal to FPGA, to video A/D conversion module clock input signal;
Described video A/D conversion module is used for pal mode vision signal to be decoded as 8 bit data signal DEC_P, clock signal DEC_CLK, field signal FIELD, frame synchronizing signal VS and line synchronizing signal HS, and this data-signal carries out image procossing through FPGA;
Described video D/A conversion module is converted to analog pal CVBS signal exports from the video data of FPGA, row signal, field signal, clock signal;
Described SDI coding module is used for carrying out stringization process from the video data of FPGA, video clock, output SDI video image;
View data LVDS differential signal, LVDS differential clock signal, for gathering the view data of industrial CameraLink camera, are changed that output is 80 LVTTL video data signals, XPCLK clock signal exports for FPGA process by described CameraLink interface circuit;
The signal received is that the data of 8 are for fpga chip image procossing according to the communication Protocol Conversion required by RS485 by the TTL signal that described serial port drive circuit receives;
Described output driver circuit is used for be that video data signal, PCLK output signal are simultaneously for polylith tracking disposable plates real-time tracking target from 80 LVTTL data-signals of FPGA, pixel clock signal PCLK driver output.
Above-mentioned power module comprises the first power subsystem, second source unit and the 3rd power subsystem, and described first power subsystem is connected with second source unit.
Above-mentioned global clock module comprises active crystal oscillator.
Above-mentioned video A/D conversion module comprises ADV7183 chip, described ADV7183 chip receives pal mode vision signal and carries out decoding process, and decoded 8 bit data signal DEC_P, clock signal DEC_CLK, field signal FIELD, frame synchronizing signal VS and line synchronizing signal HS are transferred to FPGA; FPGA is by I2C bus configuration ADV7183 decoded data.
Above-mentioned video D/A conversion module comprises ADV7179 chip and AD8051 driving chip, and described ADV7179 chip is converted to analog pal CVBS signal and amplifies through AD8051 driving chip export from video data ENC_P, the row signal ENC_HS of fpga chip, field signal ENC_VS, clock signal ENC_CLK.
Above-mentioned SDI coding module comprises CLC020 chip and SDI interface, and described CLC020 chip is used for video data DA, video clock DA_CLK stringization generate the SDI video image of SD and are exported by SDI interface.
Above-mentioned CameraLink interface circuit comprises DS90CR288A chip, described DS90CR288A chip is for gathering the view data of industrial CameraLink camera, and by the LVDS differential signal of view data, LVDS differential clock signal is converted to 80 LVTTL video data signals, XPCLK clock signal exports for FPGA process.
Above-mentioned serial port drive circuit comprises MAX3430 chip, is used for and external system communication by MAX3430 chip.
Above-mentioned output driver circuit comprises SN74LVTH16245A chip, and it is video data signal that described SN74LVTH16245A chip is used for 80 LVTTL vision signals and pixel clock signal PCLK driver output, PCLK output signal follows the tracks of disposable plates real-time tracking target for polylith simultaneously.
Above-mentioned FPGA comprises that video AD turns D/A module, configuration module, character adding module, CameraLink turn D/A module, CameraLink decoder module, max min average module, 80 bit data modules and transmitting-receiving modular converter,
Described video AD turns 8 bit data signal DEC_P, clock signal DEC_CLK that D/A module exports for receiver, video AD conversion module, field signal FIELD, frame synchronizing signal VS and line synchronizing signal HS, and produce DA video data and DA clock signal according to the requirement form of digital video DA coding chip, send to character adding module, for character adding module;
Described CameraLink turns D/A module for receiving 80 LVTTL video data signals and the XPCLK clock signal of the transmission of CameraLink interface circuit, and be translated into pal video data flow, and export according to the requirement of DA coding chip, send to character adding module, for character adding module;
Described character adding module: receive DA video data, DA clock signal carries out character adding to its video data stream, exports as with the DA video data of character and DA clock signal; This output signal divides two-way to export, and video D/A conversion module is exported on a road, and SDI coding module is exported on a road; Receive pal video stream, carry out character adding, export as with the DA video data of character and DA clock signal; This output signal divides two-way to export, and video D/A conversion module is exported on a road, and SDI coding module is exported on a road;
Described CameraLink decoder module receives 80 LVTTL video data signals and the XPCLK clock signal of the transmission of CameraLink interface circuit, after be converted to LVTTL video data signal, XPCLK clock signal, FVAL frame signal, the capable signal of LVAL of 80, export to 80 bit data modules;
Described 80 bit data modules receive 80 LVTTL video data signal, XPCLK clock signal, FVAL frame signal and the capable signal of LVAL, after be converted to 80 LVTTL video data signals, XPCLK clock signal, FVAL frame signal, the capable signal of LVAL, 14 output enable signals and 14 control direction signals, export to and export data-driven module;
Described max min average module receives 80 LVTTL video data signals and the XPCLK clock signal of the transmission of CameraLink interface circuit, calculate the maximum of entire image pixel, minimum value and mean value in real time, and export maximum, minimum value and mean value and receive and dispatch modular converter to RS485;
Described RS485 receives and dispatches modular converter and receives maximum, minimum value, average data, is converted to the TTL signal of serial according to RS485 requirement and exports to serial port drive circuit module;
Described configuration module is by the decoded data of I2C bus configuration ADV7183.
The advantage that the utility model has:
1, the utility model video interface module volume is little, lightweight, about 150 grams.
2, can the forwarding of video data of embedded video tracker of the present utility model, preliminary treatment and video image display.
3, the utility model video interface module also may be used for industry, the live video of military project and national defense industry monitors.
4, the utility model video interface module may be used for the data acquisition of industry high speed digital camera, forwarding and display.
5, the utility model video interface module may be used for the display of the data acquisition of Industrial Simulation camera, forwarding and pal video.
6, the utility model video interface module may be used for the preliminary treatment of video image, comprises character adding, image average, maximum, minimum value etc., for the polylith video tracking disposable plates of rear end video tracker provides preprocessed data.
7, the utility model video interface module can complete the video image acquisition display of the multiple frame frequency of industrial CameraLink digital camera and forward.
Accompanying drawing explanation
Fig. 1 is the structural representation of the video interface module of the utility model embedded type multifunctional;
Fig. 2 is power module theory diagram;
Fig. 3 is global clock module principle figure;
Fig. 4 is the schematic diagram of video A/D conversion module;
Fig. 5 is the schematic diagram of video D/A conversion module;
Fig. 6 is the circuit theory diagrams of fpga chip;
Fig. 7 is the schematic diagram of SDI coding module;
Fig. 8 is the schematic diagram of CameraLink interface circuit;
Fig. 9 is serial port drive circuit diagram;
Figure 10 is the schematic diagram exporting data-driven module.
Embodiment
As shown in Figure 1, a video interface module for embedded type multifunctional, comprises power module 1, global clock module 2, video A/D conversion module 3, video D/A conversion module 4, FPGA5, SDI coding module 6, CameraLink interface circuit 7, exports data-driven module 9 and serial port drive circuit 8;
Power module is powered to FPGA; Global clock module provides global clock signal to FPGA, to video A/D conversion module clock input signal; Video A/D conversion module is used for pal mode vision signal to be decoded as 8 bit data signal DEC_P, clock signal DEC_CLK, field signal FIELD, frame synchronizing signal VS and line synchronizing signal HS (CCIR601/CCIR656 standard), and this data-signal carries out image procossing through FPGA; Video D/A conversion module is converted to analog pal CVBS signal exports from the video data of FPGA, row signal, field signal, clock signal; SDI coding module is used for carrying out stringization process from the video data of FPGA, video clock, output SDI video image; View data LVDS differential signal, LVDS differential clock signal, for gathering the view data of industrial CameraLink camera, are changed that output is 80 LVTTL video data signals, XPCLK clock signal exports for FPGA process by CameraLink interface circuit; The signal received is that the data of 8 are for fpga chip image procossing according to the communication Protocol Conversion required by RS485 by the TTL signal that serial port drive circuit receives; Output driver circuit is used for be that video data signal, PCLK output signal are simultaneously for polylith tracking disposable plates real-time tracking target from 80 LVTTL data-signals of FPGA, pixel clock signal PCLK driver output.
Power module comprises the first power subsystem, second source unit and the 3rd power subsystem, and described first power subsystem is connected with second source unit.
Global clock module comprises active crystal oscillator.
Video A/D conversion module comprises ADV7183 chip, described ADV7183 chip receives pal mode vision signal and carries out decoding process, and decoded 8 bit data signal DEC_P, clock signal DEC_CLK, field signal FIELD, frame synchronizing signal VS and line synchronizing signal HS are transferred to FPGA; FPGA is by I2C bus configuration ADV7183 decoded data.
Video D/A conversion module comprises ADV7179 chip and AD8051 driving chip, and described ADV7179 chip is converted to analog pal CVBS signal and amplifies through AD8051 driving chip export from video data ENC_P, the row signal ENC_HS of fpga chip, field signal ENC_VS, clock signal ENC_CLK.
SDI coding module comprises CLC020 chip and SDI interface, and described CLC020 chip is used for video data DA, video clock DA_CLK stringization generate the SDI video image of SD and are exported by SDI interface.
CameraLink interface circuit comprises DS90CR288A chip, described DS90CR288A chip is for gathering the view data of industrial CameraLink camera, and by the LVDS differential signal of view data, LVDS differential clock signal is converted to 80 LVTTL video data signals, XPCLK clock signal exports for FPGA process.
Serial port drive circuit comprises MAX3430 chip, is used for and external system communication by MAX3430 chip.
Output driver circuit comprises SN74LVTH16245A chip, and it is video data signal that described SN74LVTH16245A chip is used for 80 LVTTL vision signals and pixel clock signal PCLK driver output, PCLK output signal follows the tracks of disposable plates real-time tracking target for polylith simultaneously.
FPGA comprises that video AD turns D/A module, character adding module, CameraLink turn D/A module, CameraLink decoder module, max min average module, 80 bit data modules and transmitting-receiving modular converter.
Video AD turns the input termination video A/D conversion module of D/A module, video AD turns the input of the output termination character adding module of D/A module, the input that CameraLink turns D/A module and CameraLink decoder module all connects CameraLink interface circuit, CameraLink turns the input of the output termination character adding module of D/A module, the output termination video D/A conversion module of character adding module and SDI coding module, the output termination of CameraLink decoder module exports the input of 80 bit data modules, the output exporting 80 bit data modules exports the input exporting data-driven module to, the output termination RS485 of max min average module receives and dispatches the input of modular converter, S485 receives and dispatches the input of the output termination serial port drive circuit module of modular converter.
Video AD turns D/A module: analog video CVBS signal is decoded into 8 digital video data and row, field, clock signal by AD decoding chip, and produces 8 digital video data, clock signal according to the requirement form of digital video DA coding chip.Character adding module: write generation character repertoire, by the character adding that generates on the video data of 8 (as by character adding in positions such as video image top, bottoms), and to export according to the video flowing of video DA form.CameraLink turns D/A module: the view data receiving CameraLink interface, the vedio data of LVDS difference is converted to 80 digital video view data of LVTTL signal, vedio data is converted to pal video data flow, according to video DA formatted output video data stream.CameraLink decoder module: the view data receiving CameraLink interface, the differential video view data of its LVDS is converted to the vedio data signal of 80, this signal is LVTTL signal, and this 80 digital video view data is exported.Max min average module: calculate the maximum of all pixels on whole frame video image, minimum value and mean value in real time, and export maximum, minimum value and mean value.Export 80 bit data modules: export 80 digital video diagram datas, clock, frame signal, row signal.Control the enable signal exporting data driving chip simultaneously, enable 80 digital video view data, clock, frame signal, row signal that real-time tracking disposable plates receiver module exports.RS485 receives and dispatches modular converter: receiving the TTL signal that serial ports RS485 chip receives, is that the data of 8 are for fpga chip image procossing according to the communication Protocol Conversion required by RS485 by the signal received; The maximum calculated by image procossing, minimum value, mean value etc. require the TTL signal of accurate transposition serial according to RS485 and export to RS485 chip.The effect of max min average module: in fpga chip, calculates the maximum of all pixels on whole frame video image, minimum value, mean value in real time, and these values is exported by RS485 serial ports.Be mainly real-time tracking disposable plates real-time tracking target to use (maximum, minimum value, these parameter extraction targets of mean value of image will be used when following the tracks of disposable plates tracking target, determine whether follow the tracks of target).
Power unit: power unit is input as 5V, power supply output error is ± 10%, exports as 3.3V, 1.2V and 1.8V.Power supply chip PTH05060WAH is input as 5V, exports as 3.3V; Power supply chip LT1764EQ is input as 3.3V, exports as 1.2V; Power supply chip LT1764EQ-1.8 is input as 5.0V, exports as 1.8V.Its schematic diagram is shown in accompanying drawing 2.
Global clock schematic diagram: global clock circuit is the active crystal oscillator of 27MHZ, for FPGA provides global clock and AD decoding chip ADV7183 to provide 27MHZ clock to input.Its theory diagram is shown in accompanying drawing 3.
Video A/D conversion module: the pal mode vision signal that J1 or J2 inputs is decoded as by chip ADV7183 the I/O pin that 8 bit data signal DEC_P are transferred to fpga chip; Clock signal DEC_CLK, field signal FIELD, frame synchronization VS are connected FPGA with the synchronous HS pin of row simultaneously; FPGA, by I2C bus configuration ADV7183 decoded data, carries out preliminary treatment for FPGA to image, shows and be transmitted to follow the tracks of processing module use as character adding.Its schematic diagram is shown in accompanying drawing 4.
Video D/A conversion module: video DA chip ADV7179 will export 8 digital video data ENC_P, row signal ENC_HS, field signal ENC_VS, clock signal ENC_CLK by ADV7179 chip from fpga chip, be converted to analog pal CVBS signal to export, and amplifying output through driving chip AD8051, its output interface is shown in J3.Its schematic diagram is shown in shown in accompanying drawing 5.
FPGA chip circuit: fpga chip selects EP2S60F672, this chip is realized (1) and is decoded by ADV7183 by analog video signal CVBS, turn D/A module by video AD, character adding module exports real time video image, this video image has two-way to export, and wherein a road exports the pal video image of tape character superposition through path 1 chip ADV7179; Another road exports the SDI video image of tape character superposition through path 2 chip CLC020; (2) industrial CameraLink Interface Video data are received, decoding outputs to FPGA, turn D/A module by Cameralink, character adding module exports real time video image, this video image has two-way to export, wherein a road video image and through path 1 chip ADV7179 export tape character superposition pal video image; Another road video image exports the SDI video image of tape character superposition through path 2 chip CLC020; (3) the Cameralink interface data of industrial camera is received, decoding outputs to FPGA, by Cameralink decoder module, export 80 bit data modules, real-time output image data to real-time tracking disposable plates, for real-time tracking disposable plates image data processing; (4) receive and dispatch modular converter by max min average module, RS485, export RS485 signal by chip MAX3430 and be used for the RS485 communication with external system.Its schematic diagram is shown in accompanying drawing 6.
SDI coding module: comprise chip CLC020,8 digital video data DA, video clock DA_CLK are inputed to chip CLC020 by this chip, exported as sdi signal, generate the SDI video image of SD by chip CLC020 stringization.Its principle is shown in accompanying drawing 7.
CameraLink interface circuit: the LVDS differential clock signal of 4 of video data X, Y, Z LVDS differential signals, XCLK, YCLK, ZCLK, for gathering the view data of industrial CameraLink camera, is changed by DS90CR288A chip that to export be the video data signal of 80 LVTTL, XPCLK clock signal exports for FPGA process by this circuit.One circuit-switched data is transmitted to output driver chip by FPGA and exports, for video tracking processing module deal with data; Another circuit-switched data is converted into the image display of pal mode and SDI standard for FPGA process.Its schematic diagram is shown in accompanying drawing 8.
Serial port drive circuit (serial ports RS485 communication): this module is chip used is MAX3430.The RS485 communication with external system is used for by MAX3430 chip.Its schematic diagram is shown in accompanying drawing 9.
Output driver circuit: this output driver chip is SN74LVTH16245A, by the LVTTL vision signal of 80, pixel clock signal PCLK, be that 80 digital video data-signals, PCLK output signal are simultaneously for polylith tracking disposable plates real-time tracking target through SN74LVTH16245 driver output.Its schematic diagram is shown in accompanying drawing 10.
Claims (10)
1. a video interface module for embedded type multifunctional, is characterized in that: comprise power module, global clock module, video A/D conversion module, video D/A conversion module, FPGA, SDI coding module, CameraLink interface circuit, export data-driven module and serial port drive circuit;
Described power module is powered to FPGA;
Described global clock module provides global clock signal to FPGA, to video A/D conversion module clock input signal;
Described video A/D conversion module is used for pal mode vision signal to be decoded as 8 bit data signal DEC_P, clock signal DEC_CLK, field signal FIELD, frame synchronizing signal VS and line synchronizing signal HS, and this data-signal carries out image procossing through FPGA;
Described video D/A conversion module is converted to analog pal CVBS signal exports from the video data of FPGA, row signal, field signal, clock signal;
Described SDI coding module is used for carrying out stringization process from the video data of FPGA, video clock, output SDI video image;
View data LVDS differential signal, LVDS differential clock signal, for gathering the view data of industrial CameraLink camera, are changed that output is 80 LVTTL video data signals, XPCLK clock signal exports for FPGA process by described CameraLink interface circuit;
The signal received is that the data of 8 are for fpga chip image procossing according to the communication Protocol Conversion required by RS485 by the TTL signal that described serial port drive circuit receives;
Described output driver circuit is used for be that video data signal, PCLK output signal are simultaneously for polylith tracking disposable plates real-time tracking target from 80 LVTTL data-signals of FPGA, pixel clock signal PCLK driver output.
2. the video interface module of embedded type multifunctional according to claim 1, is characterized in that: described power module comprises the first power subsystem, second source unit and the 3rd power subsystem, and described first power subsystem is connected with second source unit.
3. the video interface module of embedded type multifunctional according to claim 2, is characterized in that: described global clock module comprises active crystal oscillator.
4. the video interface module of embedded type multifunctional according to claim 3, it is characterized in that: described video A/D conversion module comprises ADV7183 chip, described ADV7183 chip receives pal mode vision signal and carries out decoding process, and decoded 8 bit data signal DEC_P, clock signal DEC_CLK, field signal FIELD, frame synchronizing signal VS and line synchronizing signal HS are transferred to FPGA; FPGA is by I2C bus configuration ADV7183 decoded data.
5. the video interface module of embedded type multifunctional according to claim 4, it is characterized in that: described video D/A conversion module comprises ADV7179 chip and AD8051 driving chip, described ADV7179 chip is converted to analog pal CVBS signal and amplifies through AD8051 driving chip export from video data ENC_P, the row signal ENC_HS of fpga chip, field signal ENC_VS, clock signal ENC_CLK.
6. the video interface module of embedded type multifunctional according to claim 5, it is characterized in that: described SDI coding module comprises CLC020 chip and SDI interface, described CLC020 chip is used for video data DA, video clock DA_CLK stringization generate the SDI video image of SD and are exported by SDI interface.
7. the video interface module of embedded type multifunctional according to claim 6, it is characterized in that: described CameraLink interface circuit comprises DS90CR288A chip, described DS90CR288A chip is for gathering the view data of industrial CameraLink camera, and by the LVDS differential signal of view data, LVDS differential clock signal is converted to 80 LVTTL video data signals, XPCLK clock signal exports for FPGA process.
8. the video interface module of embedded type multifunctional according to claim 7, is characterized in that: described serial port drive circuit comprises MAX3430 chip, is used for and external system communication by MAX3430 chip.
9. the video interface module of embedded type multifunctional according to claim 8, it is characterized in that: described output driver circuit comprises SN74LVTH16245A chip, described SN74LVTH16245A chip is used for 80 LVTTL vision signals and pixel clock signal PCLK driver output being that video data signal, PCLK output signal are simultaneously for polylith tracking disposable plates real-time tracking target.
10. according to the video interface module of arbitrary described embedded type multifunctional of claim 1 to 9, it is characterized in that: described FPGA comprises that video AD turns D/A module, configuration module, character adding module, CameraLink turn D/A module, CameraLink decoder module, max min average module, 80 bit data modules and transmitting-receiving modular converter
Described video AD turns 8 bit data signal DEC_P, clock signal DEC_CLK that D/A module exports for receiver, video AD conversion module, field signal FIELD, frame synchronizing signal VS and line synchronizing signal HS, and produce DA video data and DA clock signal according to the requirement form of digital video DA coding chip, send to character adding module, for character adding module;
Described CameraLink turns D/A module for receiving 80 LVTTL video data signals and the XPCLK clock signal of the transmission of CameraLink interface circuit, and be translated into pal video data flow, and export according to the requirement of DA coding chip, send to character adding module, for character adding module;
Described character adding module: receive DA video data, DA clock signal carries out character adding to its video data stream, exports as with the DA video data of character and DA clock signal; This output signal divides two-way to export, and video D/A conversion module is exported on a road, and SDI coding module is exported on a road; Receive pal video stream, carry out character adding, export as with the DA video data of character and DA clock signal; This output signal divides two-way to export, and video D/A conversion module is exported on a road, and SDI coding module is exported on a road;
Described CameraLink decoder module receives 80 LVTTL video data signals and the XPCLK clock signal of the transmission of CameraLink interface circuit, after be converted to LVTTL video data signal, XPCLK clock signal, FVAL frame signal, the capable signal of LVAL of 80, export to 80 bit data modules;
Described 80 bit data modules receive 80 LVTTL video data signal, XPCLK clock signal, FVAL frame signal and the capable signal of LVAL, after be converted to 80 LVTTL video data signals, XPCLK clock signal, FVAL frame signal, the capable signal of LVAL, 14 output enable signals and 14 control direction signals, export to and export data-driven module;
Described max min average module receives 80 LVTTL video data signals and the XPCLK clock signal of the transmission of CameraLink interface circuit, calculate the maximum of entire image pixel, minimum value and mean value in real time, and export maximum, minimum value and mean value and receive and dispatch modular converter to RS485;
Described RS485 receives and dispatches modular converter and receives maximum, minimum value, average data, is converted to the TTL signal of serial according to RS485 requirement and exports to serial port drive circuit module;
Described configuration module is by the decoded data of I2C bus configuration ADV7183.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108297791A (en) * | 2016-12-16 | 2018-07-20 | 梅克朗有限两合公司 | Camera system and visor alternative system |
| CN110971856A (en) * | 2019-10-30 | 2020-04-07 | 中国航空工业集团公司洛阳电光设备研究所 | Device and method for generating HD-SDI video and analog video based on low-speed SRAM |
| CN112702608A (en) * | 2020-12-21 | 2021-04-23 | 苏州长风航空电子有限公司 | 2Lane LVDS video coding method and system |
| CN114390237A (en) * | 2021-12-23 | 2022-04-22 | 南京熊猫电子制造有限公司 | 48Gbps ultra-high bandwidth video coding and decoding processing system and method |
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2015
- 2015-07-21 CN CN201520531362.3U patent/CN204836400U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108297791A (en) * | 2016-12-16 | 2018-07-20 | 梅克朗有限两合公司 | Camera system and visor alternative system |
| CN108297791B (en) * | 2016-12-16 | 2021-05-14 | 梅克朗有限两合公司 | Camera system and mirror replacement system |
| CN110971856A (en) * | 2019-10-30 | 2020-04-07 | 中国航空工业集团公司洛阳电光设备研究所 | Device and method for generating HD-SDI video and analog video based on low-speed SRAM |
| CN110971856B (en) * | 2019-10-30 | 2022-01-04 | 中国航空工业集团公司洛阳电光设备研究所 | Device and method for generating HD-SDI video and analog video based on low-speed SRAM |
| CN112702608A (en) * | 2020-12-21 | 2021-04-23 | 苏州长风航空电子有限公司 | 2Lane LVDS video coding method and system |
| CN114390237A (en) * | 2021-12-23 | 2022-04-22 | 南京熊猫电子制造有限公司 | 48Gbps ultra-high bandwidth video coding and decoding processing system and method |
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