CN116208722A - Synchronous analog camera based on CMOS image sensor - Google Patents
Synchronous analog camera based on CMOS image sensor Download PDFInfo
- Publication number
- CN116208722A CN116208722A CN202310226776.4A CN202310226776A CN116208722A CN 116208722 A CN116208722 A CN 116208722A CN 202310226776 A CN202310226776 A CN 202310226776A CN 116208722 A CN116208722 A CN 116208722A
- Authority
- CN
- China
- Prior art keywords
- image sensor
- odd
- image
- trigger signal
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Studio Devices (AREA)
Abstract
The invention belongs to the field of camera module design, and particularly relates to a synchronous analog camera based on a CMOS image sensor, which comprises an image sensor, an FPGA control chip, a communication interface, a digital-to-analog converter, an external trigger interface and a power chip; the FPGA control chip comprises: the detector configuration module is connected with the image sensor and used for initializing the configuration of the image sensor; the detector trigger processing module receives the external trigger signal and distinguishes odd triggers or even triggers from the counting; the data deserializing module is used for deserializing the multipath high-speed serial data output by the image sensor, converting the multipath high-speed serial data into parallel data and splicing the parallel data to generate a frame of complete image. The even trigger signal and the odd trigger signal are distinguished and allocated through the detector trigger processing module, and the odd-even field image obtained by splitting the same frame of image is sequentially output when the external trigger signal arrives, so that the synchronization with the external trigger signal is realized. All pixels are simultaneously exposed to start/stop, and no jaggy phenomenon exists when a dynamic target is shot.
Description
Technical Field
The invention belongs to the technical field of image communication, and particularly relates to a synchronous analog camera based on a CMOS image sensor.
Background
The analog camera carries out PAL type coding on the video model, realizes long-distance transmission of video images by adopting a single signal wire, has the characteristic of simple connection, and is widely applied to some military monitoring equipment. The traditional analog camera design adopts CCD as an image sensor, and realizes an imaging function by matching with a special driving chip and an analog video amplifier.
The traditional analog camera divides the image into odd-even fields for transmission, and because the odd-even field images are imaged in a time-sharing way, a sawtooth phenomenon can appear when a dynamic object is shot or the dynamic object is imaged, and the image appearance is affected.
Disclosure of Invention
The invention aims to provide a synchronous analog camera based on a CMOS image sensor, which overcomes the defects of the prior art, distinguishes and distributes even trigger signals and odd trigger signals through a detector trigger processing module, outputs odd-even field images obtained by splitting the same frame of images together, and enables all pixels to be exposed and started/stopped simultaneously, so that the synchronous analog camera has no saw-tooth phenomenon when shooting a dynamic target.
In order to solve the problems, the technical scheme adopted by the invention is as follows:
a synchronous analog camera based on a CMOS image sensor comprises an image sensor, an FPGA control chip, a communication interface, a digital-to-analog converter, an external trigger interface and a power chip;
the FPGA control chip comprises:
the detector configuration module is connected with the image sensor and used for initializing the configuration of the image sensor;
the detector trigger processing module receives the external trigger signal and distinguishes odd triggers or even triggers from the counting;
the data deserializing module is used for deserializing the multipath high-speed serial data output by the image sensor, converting the multipath high-speed serial data into parallel data and splicing the parallel data to generate a frame of complete image;
the odd-even field image splitting module is used for splitting a frame of complete image into an odd-numbered line image and an even-numbered line image, wherein the odd-numbered line image is used as an odd field image, and the even-numbered line image is used as an even field image;
and the PLA format data packaging module is used for generating PAL-type digital video by receiving the odd field image and the even field image, adding the frame head and the frame tail information to the odd field image and transmitting the digital video to the digital-to-analog converter.
Further, the power supply chip comprises a DCDC chip and an LDO chip.
Further, a DDR memory is arranged outside the FPGA control chip, and a DDR memory control module connected with the DDR memory is arranged in the FPGA chip and used for controlling reading and writing of the DDR memory.
Further, the odd-even field image splitting module is connected with a dimming control module, receives the exposure time and gain output by the serial port module in a manual exposure mode, counts the brightness information of the image in an automatic exposure mode, automatically calculates and generates the exposure time and gain, and sends the exposure time and gain to the detector configuration module.
Further, the dimming control module is connected with the serial port communication module and is used for receiving control information to control the working mode of the camera and feeding back the real working state of the camera.
Further, the workflow of the FPGA control chip includes the following steps:
step one, after a camera is electrified, initializing and configuring an image sensor through a detector configuration module;
waiting for an external trigger signal, and reasonably delaying the trigger signal and then sending the trigger signal to the image sensor after the external trigger signal is transmitted to the detector trigger processing module;
step three, the data deserializing module receives the image output by the image sensor and splits the image into odd-even field images through the odd-even field image splitting module;
step four, receiving an odd trigger signal, directly packaging the odd field images into PAL format for outputting, and caching the even field images;
and step five, receiving an even trigger signal, reading out buffered even field images, packaging the even field images into PAL format for output, and returning to the step two.
Further, in the fourth step, when the odd trigger signal is received, the image sensor trigger signal is not generated, but an internal trigger signal is generated in a delayed manner to the odd-even field image splitting module, so as to control the output of the buffered even field image, and ensure that the PAL analog video is started to be synchronous with the next even trigger signal.
In the fifth step, when an even trigger signal is received, the trigger signal of the image sensor is generated after the input trigger signal is precisely delayed, the delay considers the exposure time of the image sensor, the output delay of the image sensor, the processing delay of the data deserializing module and the processing delay of the odd-even field image splitting module are considered, so that the synchronization of the output PAL analog video start and the next odd trigger signal is ensured.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention distinguishes and distributes even trigger signals and odd trigger signals through the detector trigger processing module, outputs the odd-even field images obtained by splitting the same frame of images together, and simultaneously exposes all pixels to start/stop, so that the invention has no sawtooth phenomenon when shooting dynamic targets.
2. According to the invention, the FPGA is used as a control chip, so that the automatic dimming function is realized, the external trigger is supported, and the synchronous shooting of a plurality of cameras can be realized.
3. The invention adopts the DCDC chip and the LDO chip as the power chip, and has the advantage of low power consumption.
Drawings
Fig. 1 is a schematic structural diagram of a synchronous analog camera based on a CMOS image sensor.
Fig. 2 is a schematic diagram of an internal structure of an FPGA control chip in a CMOS image sensor-based synchronous analog camera.
Fig. 3 is a schematic workflow diagram of a synchronous analog camera based on a CMOS image sensor.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, a synchronous analog camera based on a CMOS image sensor according to the present invention includes:
the image sensor employs a Sony global shutter detector, model IMX287LLR-C. The global shutter detector is characterized in that all pixel exposure starts and ends simultaneously so as to ensure that the moving image is not inclined when shooting; the pixel size is 6.9 mu m multiplied by 6.9 mu m, and the large pixel size leads the sensitivity of the camera to be better than that of the traditional analog camera; resolution 728×554 is close to the PAL resolution, and the matching process is easy.
The camera is powered by 5-12V. The power supply design adopts a DCDC and LDO combined design. The digital power supply adopts a DCDC chip with the model SY8182BABC, and the power efficiency is up to 95 percent so as to realize low power consumption; the analog power supply is generated by using an LDO with the model SY6301DCS, and the ripple wave of the power supply is restrained so as to reduce image noise.
The controller adopts an FPGA with Xilinx model number of XC7A50T-324I and is provided with a DDR memory chip for data caching, the storage capacity is 1Gbit, and the model number is MT41J64M16JT_15E.
The communication interface adopts TPT3232E-SS3R of 3Peak company to realize RS232 communication, controls the working mode of the camera, comprises automatic/manual dimming, and sets parameters such as exposure time, gain and the like.
The analog video output adopts a digital-to-analog converter ADV7123KST140-RL, and the chip can output three paths of analog videos, and only 1 path of video output is used in the design of the camera.
The external trigger interface adopts LVTTL level standard and is directly connected with the FPGA programmable pin.
As shown in fig. 2, 8 functional modules are designed in the FPGA software.
The detector configuration module: the method realizes the initialization configuration of the image sensor, controls the detector to work in an external trigger mode, and realizes the dynamic adjustment of the exposure time and gain of the detector.
The detector trigger control module: after receiving the external trigger signal, the FPGA distinguishes odd trigger or even trigger from the counting. When even trigger is performed, the trigger signal of the image sensor is generated after the input trigger signal is precisely delayed, the delay considers the exposure time of the image sensor, the output delay of the image sensor, the processing delay of a decoding data decoding module, the processing delay of an even-odd field image splitting module and the like are considered, so that the output PAL analog video is ensured to be synchronous with the next odd trigger signal. When the PAL analog video is triggered in odd number, the trigger signal of the image sensor is not generated, but an internal trigger signal is generated in a delayed mode to the odd-even field image splitting module, and the buffered even field image is controlled to be output so as to ensure that the PAL analog video is started to be synchronous with the next even trigger signal. Each time the image sensor receives a trigger signal, it outputs a complete image including the parity field image.
And a data deserializing module: and de-serializing the multipath high-speed serial data output by the image sensor, converting the multipath high-speed serial data into parallel data, and splicing to generate a frame of complete image.
Parity field image splitting module: and splitting a frame of complete image into an odd line image and an even line image, wherein the odd line image is used as an odd field image, and the even line image is used as an even field image. The odd field image cache lines are arranged in the FPGA, and are directly output to a subsequent packaging module after receiving the odd field synchronous signals; and after the odd field images are sent, controlling the DDR memory control module to read out a plurality of lines of even field images to be cached in the FPGA, waiting for the arrival of even field synchronizing signals, outputting the cached even field images, sequentially reading out the even field images from the DDR memory, and continuously sending out the even field images. By the method, the fact that the odd-even field image is a frame of complete image at the source end is guaranteed, all pixel exposure start and stop are completed synchronously, the follow-up image receiving equipment is used for splicing the odd-even field into a frame of complete image for displaying, and the problem of sawtooth generated by shooting a dynamic target due to target image shift is solved.
DDR memory control module: is an IP core in the FPGA and mainly realizes the read-write control of the DDR memory chip.
The PAL format data packaging module adds the odd-even field image with the frame head and frame tail information to generate PAL format digital video, and sends the PAL format digital video to the digital-to-analog conversion chip.
And the serial communication module controls the working mode of the camera according to the received control information and feeds back the real working state of the camera.
The dimming control module realizes different functions according to the control information, receives the exposure time and gain output by the serial port module in the manual exposure mode, counts the image brightness information in the automatic exposure mode, automatically calculates and generates the exposure time and gain, and sends the exposure time and gain to the detector configuration module. The automatic exposure algorithm is designed individually according to different applications.
As shown in fig. 3, the workflow of the FPGA control chip includes the following steps:
step one, after a camera is electrified, initializing and configuring an image sensor through a detector configuration module;
waiting for an external trigger signal, and reasonably delaying the trigger signal to be sent to the image sensor after the external trigger signal is transmitted to the detector trigger processing module through the external trigger interface;
step three, the data deserializing module receives the image output by the image sensor and splits the image into odd-even field images through the odd-even field image splitting module;
step four, receiving odd trigger signals, not generating the trigger signals of the image sensor, delaying to generate an internal trigger signal to the odd-even field image splitting module, controlling to output buffered even field images so as to ensure that PAL analog video starts to be synchronous with the next even trigger signals, directly packaging odd field images into PAL format for outputting, and buffering even field images;
and fifthly, receiving even trigger signals, precisely delaying the input trigger signals to generate trigger signals of the image sensor, wherein the delay considers the exposure time of the image sensor, the output delay of the image sensor, the processing delay of the data deserializing module and the processing delay of the odd-even field image splitting module are considered, so that the output PAL analog video is ensured to be synchronous with the next odd trigger signals, the buffered even field images are read out and packaged into PAL format for output, and the step two is returned.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (8)
1. A synchronous analog camera based on a CMOS image sensor, characterized in that: the device comprises an image sensor, an FPGA control chip, a communication interface, a digital-to-analog converter, an external trigger interface and a power chip;
the FPGA control chip comprises:
the detector configuration module is connected with the image sensor and used for initializing the configuration of the image sensor;
the detector trigger processing module receives the external trigger signal and distinguishes odd triggers or even triggers from the counting;
the data deserializing module is used for deserializing the multipath high-speed serial data output by the image sensor, converting the multipath high-speed serial data into parallel data and splicing the parallel data to generate a frame of complete image;
the odd-even field image splitting module is used for splitting a frame of complete image into an odd-numbered line image and an even-numbered line image, wherein the odd-numbered line image is used as an odd field image, and the even-numbered line image is used as an even field image;
and the PLA format data packaging module is used for generating PAL-type digital video by receiving the odd field image and the even field image, adding the frame head and the frame tail information to the odd field image and transmitting the digital video to the digital-to-analog converter.
2. A synchronous analog camera based on CMOS image sensor according to claim 1, wherein: the power supply chip comprises a DCDC chip and an LDO chip.
3. A synchronous analog camera based on CMOS image sensor according to claim 1, wherein: the external part of the FPGA control chip is provided with a DDR memory, and the FPGA chip is internally provided with a DDR memory control module connected with the DDR memory and used for controlling the reading and writing of the DDR memory.
4. A synchronous analog camera based on CMOS image sensor according to claim 1, wherein: the odd-even field image splitting module is connected with a dimming control module, receives the exposure time and gain output by the serial port module in a manual exposure mode, counts the image brightness information in an automatic exposure mode, automatically calculates and generates the exposure time and gain, and sends the exposure time and gain to the detector configuration module.
5. The synchronous analog camera based on CMOS image sensor according to claim 4, wherein: the dimming control module is connected with the serial port communication module and is used for receiving control information to control the working mode of the camera and feeding back the real working state of the camera.
6. A synchronous analog camera based on CMOS image sensor according to any one of claims 1-5, wherein: the working flow of the FPGA control chip comprises the following steps:
step one, after a camera is electrified, initializing and configuring an image sensor through a detector configuration module;
waiting for an external trigger signal, and reasonably delaying the trigger signal to be sent to the image sensor after the external trigger signal is transmitted to the detector trigger processing module through the external trigger interface;
step three, the data deserializing module receives the image output by the image sensor and splits the image into odd-even field images through the odd-even field image splitting module;
step four, receiving an odd trigger signal, directly packaging the odd field images into PAL format for outputting, and caching the even field images;
and step five, receiving an even trigger signal, reading out buffered even field images, packaging the even field images into PAL format for output, and returning to the step two.
7. The CMOS image sensor-based synchronous analog camera of claim 6, wherein: and step four, when the odd trigger signal is received, the image sensor trigger signal is not generated, but an internal trigger signal is generated in a delayed mode to the odd-even field image splitting module, and the buffered even field image is controlled to be output so as to ensure that PAL analog video starts to be synchronous with the next even trigger signal.
8. A CMOS image sensor based synchronous analog camera according to claim 7, wherein: and fifthly, when an even trigger signal is received, accurately delaying the input trigger signal to generate a trigger signal of the image sensor, wherein the delay considers the exposure time of the image sensor, the output delay of the image sensor, the processing delay of the data deserializing module and the processing delay of the odd-even field image splitting module so as to ensure that the output PAL analog video is started to be synchronous with the next odd trigger signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310226776.4A CN116208722A (en) | 2023-03-09 | 2023-03-09 | Synchronous analog camera based on CMOS image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310226776.4A CN116208722A (en) | 2023-03-09 | 2023-03-09 | Synchronous analog camera based on CMOS image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116208722A true CN116208722A (en) | 2023-06-02 |
Family
ID=86517126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310226776.4A Pending CN116208722A (en) | 2023-03-09 | 2023-03-09 | Synchronous analog camera based on CMOS image sensor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116208722A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118075405A (en) * | 2024-04-22 | 2024-05-24 | 南京仁芯科技有限公司 | De-serializer, serial/de-serializer comprising same and automobile communication system using same |
-
2023
- 2023-03-09 CN CN202310226776.4A patent/CN116208722A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118075405A (en) * | 2024-04-22 | 2024-05-24 | 南京仁芯科技有限公司 | De-serializer, serial/de-serializer comprising same and automobile communication system using same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5925812B2 (en) | Real-time image acquisition and display | |
| CN102929572B (en) | A kind of realize the seamless spliced method of the many projections of giant-screen and splicing fusion device | |
| CN100426840C (en) | Multicamera system, image pickup apparatus, image pickup control method, controller and control method thereof | |
| CN103595924B (en) | A kind of image fusion system based on Cameralink and method thereof | |
| CN116208722A (en) | Synchronous analog camera based on CMOS image sensor | |
| CN104580945A (en) | Image sensor structure and method for achieving high-dynamic-range image | |
| US10997689B1 (en) | High dynamic range sensor system with row increment operation | |
| CN105657403B (en) | The synchronization system of structured light projection and Image Acquisition based on FPGA | |
| CN101909149A (en) | Camera head | |
| CN109587421B (en) | HD-SDI/3G-SDI transceiving and real-time picture-in-picture switching output processing method | |
| CN101729782B (en) | Imaging apparatus and imaging method | |
| CN101815170A (en) | Camera head | |
| CN102625086B (en) | DDR2 (Double Data Rate 2) storage method and system for high-definition digital matrix | |
| CN108134912B (en) | Video stream conversion method | |
| JP2020170923A (en) | Imaging element, control method of the same, and imaging apparatus | |
| US20130058618A1 (en) | Imaging device and imaging method | |
| JP3118032B2 (en) | Video camera | |
| CN102497514B (en) | Three-channel video forwarding equipment and forwarding method | |
| CN107948467B (en) | Large-area-array high-frame-frequency image acquisition device | |
| JP2015054211A (en) | Image pickup device and electronic endoscope apparatus | |
| JP2003283906A (en) | High resolution imaging device | |
| KR102104327B1 (en) | Low power LVDS video transmission system | |
| KR101939990B1 (en) | Low power LVDS video transmission device, system and method | |
| CN110971856B (en) | Device and method for generating HD-SDI video and analog video based on low-speed SRAM | |
| JP2020057844A (en) | Imaging apparatus, control method of the same, program, and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |