CN118075405A - De-serializer, serial/de-serializer comprising same and automobile communication system using same - Google Patents
De-serializer, serial/de-serializer comprising same and automobile communication system using same Download PDFInfo
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Abstract
The invention relates to a deserializer, a serial/deserializer comprising the same and an automobile communication system using the same. The deserializer comprises a data receiving module, wherein the data receiving module is used for converting original data into a format of the original data; the video processing module is connected with the data receiving module, and comprises a data splitter, a left splitter, a right splitter and a parity splitter which are sequentially connected, wherein the data splitter is used for receiving the original data passing through the data receiving module, the left splitter and the right splitter are used for splitting the original data passing through the data splitter into left data and right data, the parity splitter is used for splitting the left data into left odd data and left even data, and the right data is split into right odd data and right even data; and the driving signal output module is connected with the video processing module and used for outputting driving signals. The invention supports driving of the high-resolution display screen, and has high efficiency and low cost.
Description
Technical Field
The invention relates to the technical field of automobile communication; in particular, the present invention relates to a deserializer, a serial/deserializer including the same, and an automotive communication system to which the same is applied.
Background
In an automotive communication system, a liquid crystal driving chip (Source IC) is generally driven by a Low Voltage Differential Signal (LVDS) output from a serializer/deserializer (Serdes), and thus drives a display screen.
When the display screen needs higher resolution, the frequency of the LVDS signal output by the Serdes increases, and may exceed the threshold value preset by the Source IC, so in the conventional technology, the LVDS signal is usually split by a Bridge chip (Bridge IC), and the frequency of the LVDS signal is further reduced. However, the Bridge IC has a relatively high cost, and can only split the LVDS signal into two paths, so that when the display screen has a requirement of ultra-high resolution, the frequency of the LVDS signal is very high, and the Bridge IC cannot reduce the frequency of the LVDS signal to a suitable value, so that the low-cost and high-efficiency development requirement of the display screen driving system in the automobile communication system cannot be met.
Disclosure of Invention
In view of the above, the present invention provides a deserializer, a serializer/deserializer including the same, and an automotive communication system employing the same, thereby solving or at least alleviating one or more of the above-mentioned problems and other problems with the prior art.
To achieve the foregoing object, a first aspect of the present invention proposes a deserializer for connecting to a serializer, comprising:
the data receiving module is used for receiving the original data sent by the serializer and converting the format of the original data;
The video processing module is connected with the data receiving module, the video processing module comprises a data splitter, a left splitter, a right splitter and a parity splitter which are sequentially connected, the data splitter is used for receiving the original data passing through the data receiving module, the left splitter and the right splitter are used for splitting the original data passing through the data splitter into left data and right data, the parity splitter is used for splitting the left data into left odd data and left even data, and the right data is split into right odd data and right even data; and
The driving signal output module is connected with the video processing module and is used for outputting driving signals according to the left odd data, the left even data, the right odd data and the right even data.
In the deserializer as described above, optionally, the data splitter has a threshold for data transmission rate set therein,
When the transmission rate of the original data is greater than the threshold value, the data splitter splits the original data passing through the data receiving module into A data and B data, and the data splitter outputs the A data to the left splitter and the right splitter;
when the transmission rate of the original data is smaller than or equal to the threshold value, the data splitter outputs the original data passing through the data receiving module to the left splitter and the right splitter.
In the aforementioned deserializer, optionally, the deserializer further includes a data transmitting module, which is connected to the data splitter, and is configured to receive the B data and convert a format of the B data.
In the deserializer as described above, optionally, the transmission rate of the original data is N times the transmission rate of the B data passing through the data transmission module, where N is a positive integer greater than or equal to 2.
In the deserializer as described above, optionally, the data receiving module includes:
The first physical layer chip is used for carrying out A/D conversion on the original data; and
The first media access control chip is connected with the first physical layer chip and is used for carrying out deblocking processing on the original data passing through the first physical layer chip.
In the deserializer as described above, optionally, the driving signal output module is provided with a synchronization module and a plurality of parallel output channels, where the output channels are used for outputting the driving signal, and the synchronization module is used for outputting the synchronization signal.
In the deserializer as described above, optionally, the data transmitting module includes:
The second medium access control chip is used for packaging the B data; and
And the second physical layer chip is connected with the second media access control chip and is used for carrying out D/A conversion on the B data passing through the second media access control chip.
In the deserializer as described above, optionally, the video processing module further includes a buffer for temporarily storing the B data.
In order to achieve the foregoing object, a second aspect of the present invention provides a scalable serializer/deserializer for an automotive communication system, wherein the serializer/deserializer has a serializer and at least two deserializers according to any one of the foregoing first aspects connected by a daisy chain, and in adjacent two of the deserializers, a data transmitting module and a synchronizing module of a front deserializer are connected to a data receiving module and a synchronizing module of a rear deserializer, respectively.
In order to achieve the foregoing object, a third aspect of the present invention provides an automotive communication system having the deserializer as described in any of the foregoing first aspects.
According to the deserializer, the multiple splitters are arranged in the video processing module, so that the original data are split into multiple paths of data, and multiple paths of LVDS can be output without externally connecting Bridge ICs. In addition, the deserializers can be connected through the daisy chain to support higher display screen resolution, and synchronous output of each deserializer is realized through the SYNC signal, so that the development requirements of low cost and high efficiency of a display screen driving system in an automobile communication system are met.
Drawings
The present disclosure will become more apparent with reference to the accompanying drawings. It is to be understood that these drawings are solely for purposes of illustration and are not intended as a definition of the limits of the invention. In the figure:
FIG. 1 is a schematic diagram of one embodiment of a deserializer of the present invention;
fig. 2 and 3 are schematic diagrams of the working principle of the embodiment shown in fig. 1;
FIG. 4 is a schematic diagram of the embodiment shown in FIG. 1 outputting 24bit RGB data map;
Fig. 5 and 6 are schematic diagrams of a conventional deserializer driving display screen; and
Fig. 7 is a schematic diagram of an embodiment of a deserializer driven display screen of the present invention.
Detailed Description
The emergency stop switch device, the apparatus cable breakage prevention device for a heading machine, and the structure, composition, characteristics, and advantages of the heading machine of the present invention will be described below by way of example with reference to the accompanying drawings and specific embodiments, however, all descriptions should not be taken to limit the present invention in any way.
Furthermore, to the extent that any individual feature described or implied in the embodiments set forth herein, or any individual feature shown or implied in the figures, the invention still allows any combination or deletion of such features (or equivalents thereof) without any technical hurdle, and further embodiments according to the invention are considered to be within the scope of the disclosure herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
Fig. 1 is a schematic diagram of an embodiment of a deserializer according to the present invention, and as can be seen from fig. 1, the deserializer may include a data receiving module, a video processing module, a data transmitting module, and a driving signal output module, where the video processing module is respectively connected to the data receiving module, the driving signal output module, and the data transmitting module. The data receiving module receives the original data sent by the serializer, converts the format of the original data, then sends the original data to the video processing module, processes the original data by the video processing module, and finally sends the original data to the driving signal output module to finally output the driving signal. In addition, the data transmitting module may be used to receive the data output from the video processing module when the original data transmission rate is too high.
In this embodiment, the data receiving module may include a first physical layer chip and a first media access control chip, where the first physical layer chip is configured to receive the raw data sent by the serializer and is connected to the first media access control chip; the first media access control chip is connected with the video processing module and is used for carrying out deblocking processing on the original data passing through the first physical layer chip.
Specifically, after the data receiving module receives the original data, the first physical layer chip can perform a/D conversion on the original data, encode the original data according to the encoding rule (4B/5B encoding) of the physical layer, and then transmit the original data to the first media access control chip; after the first media access control chip receives the data, the data frame is unpacked.
The video processing module processes the original data passing through the data receiving module and finally transmits the processed data to the driving signal output module, and decides whether to transmit the data to the data transmitting module according to the transmission rate of the original data. The data sending module corresponds to the data receiving module and can comprise a second media access control chip and a second physical layer chip, wherein the second media access control chip is connected with the video processing module and is used for carrying out unpacking processing on data; the second physical layer chip is connected with the second medium access control chip and is used for carrying out D/A conversion on the data passing through the second medium access control chip. After the second media access control chip receives the data output by the second physical layer chip, the data is packaged into frames, and the method specifically comprises the steps of defining the frames, realizing frame synchronization, processing a destination address and a source address, processing the frames when transmission errors occur with the second physical layer chip, and the like.
Data communication is required to comply with a certain protocol, and data to be transmitted to each other is required to have a specific format. The protocol refers to the agreement of the data frame format of the communication between the equipment and the control end, and different functions correspond to different data frames. The data frame comprises a frame head, data and a frame tail. Wherein the frame header and the frame tail contain some necessary control information, such as synchronization information, address information, error control information, etc.; the data portion includes data, such as IP packets, that are transmitted by the network layer. The data transmitting module and the data receiving module can ensure the mutual safety communication of different devices, and the problems are solved.
Fig. 2 and 3 are schematic diagrams illustrating the operation of the embodiment shown in fig. 1, and the aforementioned data receiving module and data transmitting module are not shown in fig. 2 and 3, in which the deserializer video processing module may include a data splitter, a left-right splitter, and a parity splitter connected in sequence. It should be noted that, the threshold of the data transmission rate is set in the data splitter, the data splitter may determine whether to split the data according to the transmission rate of the original data passing through the data receiving module, and the data transmission rate refers to the number of bits of the data passing through serially per second.
Moreover, in order to make the principle of splitting the original data by the deserializer of the present invention clearer, the boxes corresponding to the two colors i and ii in fig. 2 represent the two components of the original data in fig. 2, and the boxes corresponding to the four colors i, ii, iii and iv in fig. 3 represent the four components of the original data in fig. 3, respectively.
Specifically, when the transmission rate of the original data passing through the data receiving module is less than the threshold, the operating principle of the deserializer of the present invention is as shown in fig. 2. As can be seen from fig. 2, the data splitter receives the original data passing through the data receiving module (not shown in the drawing) and directly transmits it to the left and right splitters, which split the data into left and right data, and transmit the left and right data to the two parity splitters, respectively, which split the left data into left and left even data, split the right data into right and left odd data, and finally input to the driving signal output module.
In this embodiment, four parallel output channels, namely, a channel one, a channel two, a channel three and a channel four, may be provided in the driving signal output module of the deserializer, and the output channels are respectively used for receiving left odd data, left even data, right odd data and right even data and outputting driving signals (LVDS) according to the four data, where the LVDS signals are low voltage differential signals.
When the transmission rate of the original data passing through the data receiving module is greater than the threshold value in the data receiving module, the operating principle of the deserializer of the present invention is shown in fig. 3. In this embodiment, two deserializers, a first and a second deserializer, respectively, are shown in fig. 3. Because the transmission rate of the original data passing through the data receiving module is too high, the frequency of the finally output low-voltage differential signal cannot meet the requirement, and the deserializer can split the high-rate original data in a specific expansion mode.
Splitting low voltage differential signals requires consideration of the topology. When the signal transmission rate is particularly high, the T-topology cannot meet the performance requirements. The reason is that the branch wiring length of the T-shaped topological structure is too long, the impedance matching is difficult to realize with the main road under the condition of not adding a terminal resistor, the terminal resistor is added for realizing the impedance matching of each branch, the workload and the cost of circuit design are increased, and the reflection interference of the branch signal of the T-shaped topological structure on the main signal is serious, so that the T-shaped topological structure is not adopted.
The branch wires of the daisy chain topology structure are short, so that the reflected signals of the branches can be effectively restrained, but clock, address and control signals of the daisy chain topology structure cannot reach different chips at the same time. In order to solve the problem of asynchronous signals of a daisy chain topology structure, the invention is provided with a synchronization module in a driving signal output module.
As can be seen from fig. 3, the data splitter of the first deserializer may be connected to the data splitter of the second deserializer, the driving signal output module has a synchronization module that may transmit a synchronization Signal (SYNC) to ensure the synchronization output of the first deserializer and the second deserializer, and the synchronization module of the first deserializer is connected to the synchronization module of the second deserializer.
Specifically, the data splitter of the first deserializer receives the original data passing through the data receiving module (not shown in the figure), and splits the original data passing through the data receiving module into a data and B data, and then outputs the a data to the left and right splitters, and outputs the B data to the Buffer for temporary storage. The data A is finally converted into four paths of low-voltage differential signals through the left and right splitters, the parity splitters and the driving signal output module, the data B is output from the Buffer to the data transmission module (not shown in the figure) to be converted into a data format, and then is transmitted to the data receiving module (not shown in the figure) of the second deserializer to be converted into a data format, and finally is transmitted to the left and right splitters of the second deserializer. The transmission process of the B data in the second deserializer is the same as that of the A data in the first deserializer, and finally the driving signal output module of the second deserializer converts the B data into four paths of low-voltage differential signals and outputs the four paths of low-voltage differential signals.
It should be noted that, the transmission rate of the original data is N times that of the B data passing through the data transmission module, and N is a positive integer greater than or equal to 2. As can be seen from fig. 2, the data splitter of this embodiment may be implemented by two buffers, buffer a and buffer B, and the left and right splitters may be implemented by two buffers, buffer a and buffer B, and in other alternative embodiments, the data splitter and the left and right splitters may be implemented by other devices in a specific manner.
Fig. 4 is a schematic diagram of an embodiment of outputting 24bit RGB data map shown in fig. 1, R, G, B represents red, green and blue, respectively, and in this embodiment, the data corresponding to the three colors are eight bits, and in fig. 4, schematic diagrams of RGB signals of four output channels in the pixel clock signal and driving signal output module are sequentially shown from top to bottom. As can be seen from fig. 4, DE, VS, HS signals are arranged in the RGB signal header of channel three, where DE signals refer to the valid data strobe signals, VS signals refer to the field sync signals, and HS signals refer to the row sync signals. The video data signal corresponding to the high level period of the DE signal is considered as an effective data signal, the line synchronizing signal is used for selecting an effective line signal section on the liquid crystal panel, the field synchronizing signal is used for selecting an effective field signal section on the liquid crystal panel, and the line field synchronizing signal can be used for selecting the effective video signal section on the liquid crystal panel under the combined action of the line field synchronizing signal.
The synchronization signal output by the synchronization module can effectively control the synchronization of the HS signal, so that the first deserializer and the second deserializer can only read RGB data when the HS signal is in a high/low level and the pixel clock signal is in a rising edge/falling edge, thereby ensuring the consistency of data display.
Fig. 5 and 6 are schematic diagrams of a conventional deserializer driving display screen, in which fig. 5 is a schematic diagram of a conventional deserializer driving display screen without using Bridge ICs, and fig. 6 is a schematic diagram of a conventional deserializer driving display screen with using Bridge ICs.
As can be seen from fig. 5, the deserializer can receive the signal output by the serializer, and then can output two low-voltage differential signals to the liquid crystal driving chip, and finally drive the display to work. In driving the display screen, for RGB888 video, the single set of low voltage differential signal clock frequencies is equal to the pixel clock frequency. A single set of low voltage differential signal lines should support a minimum of 893 ps, corresponding to a pixel clock of 160 MHz. When the display screen needs a higher resolution, for example 3840×2160, the pixel clock is equal to the video width×video height×the frame rate of the display (60 Hz by default), the pixel clock can be calculated to be 500MHz, and the signal frequency of the single set of low voltage differential signals output by the Serdes chip exceeds 160MHz, and the source IC cannot support the signal. At this time, it is necessary to split the single group LVDS signal into 4 groups using a Bridge chip (Bridge IC), and the single group LVDS signal frequency is reduced to 160MHz or less.
As can be seen from fig. 6, the deserializer can receive the signal output by the serializer, and then output the eDP signal to the bridge chip, and finally output four low-voltage differential signals to the liquid crystal driving chip to drive the display screen.
Thus, the frequency of a single set of low voltage differential signals output by the Serdes chip is reduced to 160MHz or less. However, the cost of the bridge chip is high, and when the display screen has the requirement of ultra-high resolution, the frequency of the low voltage differential signal is high, and even if the bridge chip splits the low voltage differential signal into 4 paths, the frequency of the low voltage differential signal cannot be reduced to a proper value.
The deserializer of the present invention can solve this problem. FIG. 7 is a schematic diagram of one embodiment of a deserializer drive display screen of the present invention, with the "R-linc" signal shown in FIG. 7, and described herein: when a video signal (i.e., an NTSC, PAL or SECAM format signal) is to be processed, the signal is first subjected to a protocol conversion by an R-linc protocol, converted into an R-linc signal, and after the R-linc signal enters the serializer, the signal is converted into a signal which is easy to process by a protocol conversion in a data receiving module in the serializer, and then converted into an R-linc signal by a protocol conversion in a data transmitting module in the serializer, and then is input into the deserializer of the present invention, and the protocol conversion process in the serializer is similar to that in fig. 1 of the present invention. The R-LINC protocol is a private communication protocol for automobiles, so that the R-LINC signal can be operated safely outside, and the normal operation of the deserializer of the invention is ensured.
As can be seen from fig. 7, after two adjacent deserializers are used for receiving signals and 16G R-linc signals are input into the front deserializers, the front deserializers split 8G R-linc signals and input into the rear deserializers, and the front deserializers output synchronous signals to the rear deserializers to finally realize synchronous output of eight paths of low-voltage differential signals. Obviously, when the deserializer is applied to driving a display screen in an automobile communication system, eight low-voltage differential signals can still be output under the condition of not externally connecting a bridge chip, and in other alternative embodiments, the number of the deserializers can be expanded according to actual needs, so that the low-cost and high-efficiency development requirements of the display screen driving system in the automobile communication system are met.
The invention also proposes a scalable serializer/deserializer for an automotive communication system, having a serializer and at least two of the aforementioned deserializers connected by a daisy chain, in adjacent two of which the data transmitting module and the synchronizing module of the front deserializer are respectively connected with the data receiving module and the synchronizing module of the rear deserializer.
The invention also provides an automobile communication system with the deserializer.
In summary, the deserializer of the present invention splits the original data into multiple paths of data by arranging multiple splitters in the video processing module, and can output multiple paths of low voltage differential signals without an external bridge chip. In addition, the deserializers can be connected through the daisy chain to support higher display screen resolution, and synchronous output of each deserializer is realized through the synchronous signals, so that the development requirements of low cost and high efficiency of a display screen driving system in an automobile communication system are met.
The technical scope of the present invention is not limited to the above description, and those skilled in the art may make various changes and modifications to the above-described embodiments without departing from the technical spirit of the present invention, and these changes and modifications should be included in the scope of the present invention.
Claims (10)
1. A deserializer for use in connection with a serializer, the deserializer comprising:
the data receiving module is used for receiving the original data sent by the serializer and converting the format of the original data;
The video processing module is connected with the data receiving module, the video processing module comprises a data splitter, a left splitter, a right splitter and a parity splitter which are sequentially connected, the data splitter is used for receiving the original data passing through the data receiving module, the left splitter and the right splitter are used for splitting the original data passing through the data splitter into left data and right data, the parity splitter is used for splitting the left data into left odd data and left even data, and the right data is split into right odd data and right even data; and
The driving signal output module is connected with the video processing module and is used for outputting driving signals according to the left odd data, the left even data, the right odd data and the right even data.
2. The deserializer of claim 1, wherein the data splitter has a threshold for data transfer rate set therein,
When the transmission rate of the original data is greater than the threshold value, the data splitter splits the original data passing through the data receiving module into A data and B data, and the data splitter outputs the A data to the left splitter and the right splitter;
when the transmission rate of the original data is smaller than or equal to the threshold value, the data splitter outputs the original data passing through the data receiving module to the left splitter and the right splitter.
3. The deserializer of claim 1 or 2, further comprising a data transmission module coupled to the data splitter, the data transmission module to receive the B data and convert a format of the B data.
4. The deserializer of claim 3, wherein the transmission rate of the raw data is N times the transmission rate of the B data through the data transmission module, N being a positive integer greater than or equal to 2.
5. The deserializer of claim 3, wherein the data receiving module comprises:
The first physical layer chip is used for carrying out A/D conversion on the original data; and
The first media access control chip is connected with the first physical layer chip and is used for carrying out deblocking processing on the original data passing through the first physical layer chip.
6. A deserializer according to claim 3 wherein the drive signal output module is provided with a synchronization module and a plurality of parallel output channels, the output channels being for outputting the drive signal, the synchronization module being for outputting a synchronization signal.
7. The deserializer of claim 3, wherein the data transmission module comprises:
The second medium access control chip is used for packaging the B data; and
And the second physical layer chip is connected with the second media access control chip and is used for carrying out D/A conversion on the B data passing through the second media access control chip.
8. The deserializer of claim 3, wherein the video processing module further comprises a buffer to temporarily store the B data.
9. A scalable serializer/deserializer for automotive communication systems, characterized in that it has a serializer and at least two deserializers according to any of the previous claims 1 to 8 connected by a daisy chain, in adjacent two of which the data transmitting module and the synchronizing module of the front deserializer are connected to the data receiving module and the synchronizing module of the rear deserializer, respectively.
10. An automotive communication system, characterized in that it has a deserializer according to any of the previous claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410479776.XA CN118075405B (en) | 2024-04-22 | De-serializer, serial/de-serializer comprising same and automobile communication system using same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410479776.XA CN118075405B (en) | 2024-04-22 | De-serializer, serial/de-serializer comprising same and automobile communication system using same |
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| CN118075405A true CN118075405A (en) | 2024-05-24 |
| CN118075405B CN118075405B (en) | 2024-07-05 |
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| US6696995B1 (en) * | 2002-12-30 | 2004-02-24 | Cypress Semiconductor Corp. | Low power deserializer circuit and method of using same |
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| CN116208722A (en) * | 2023-03-09 | 2023-06-02 | 吉林省智宸光电技术有限公司 | Synchronous analog camera based on CMOS image sensor |
| CN219372498U (en) * | 2022-12-14 | 2023-07-18 | 宁波舜宇车载光学技术有限公司 | Video transmission device, video projection system and vehicle |
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| US6696995B1 (en) * | 2002-12-30 | 2004-02-24 | Cypress Semiconductor Corp. | Low power deserializer circuit and method of using same |
| CN203691525U (en) * | 2013-09-25 | 2014-07-02 | 武汉精立电子技术有限公司 | Device for converting LVDS video signal to 8LANE odd-even split screen MIPI video signals |
| CN219372498U (en) * | 2022-12-14 | 2023-07-18 | 宁波舜宇车载光学技术有限公司 | Video transmission device, video projection system and vehicle |
| CN116208722A (en) * | 2023-03-09 | 2023-06-02 | 吉林省智宸光电技术有限公司 | Synchronous analog camera based on CMOS image sensor |
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