CN212381303U - Device for realizing double-link DVI (digital video interactive) based on FPGA (field programmable Gate array) - Google Patents

Abstract

The utility model discloses a device based on FPGA realizes dual-link DVI relates to chip technical field. The device comprises: the FPGA chip is used for converting the RGB data into DVI interface data; a dual-link DVI interface for receiving the DVI interface data and transmitting the DVI interface data to an external display device. The utility model discloses a FPGA chip converts the RGB data into DVI interface data, DVI interface data is received to double Link DVI interface, and with DVI interface data transmission to external display device, thereby utilized the single-chip to realize Dual-Link DVI, compare with the scheme that adopts a plurality of chip conversion and switch realization Dual-Link DVI among the prior art, very big saving the integrated circuit board area.

Description

Device for realizing double-link DVI (digital video interactive) based on FPGA (field programmable Gate array)

Technical Field

The utility model belongs to the technical field of the chip technique and specifically relates to a device based on FPGA realizes dual-link DVI.

Background

With the continuous development of computers, in some special fields, Dual-Link DVI (Dual-Link digital Visual Interface), which is called Dual-Link DVI Interface for short, is required to be used for display.

Most of the existing chips only have HDMI (High Definition Multimedia Interface) supporting High resolution, and the chips supporting the Dual-Link DVI display mode are fewer.

SUMMERY OF THE UTILITY MODEL

The utility model discloses aim at solving one of the technical problem that exists among the prior art at least. For this reason, the utility model provides a device based on FPGA realizes Dual-Link DVI can utilize the single-chip to realize Dual-Link DVI.

According to the utility model discloses device based on FPGA realizes dual-link DVI, include:

the FPGA chip is used for converting the RGB data into DVI interface data;

a dual-link DVI interface for receiving the DVI interface data and transmitting the DVI interface data to an external display device.

According to the utility model discloses device based on FPGA realizes dual-link DVI has following beneficial effect at least:

the embodiment of the utility model provides a convert RGB data into DVI interface data through the FPGA chip, DVI interface data is received to double-Link DVI interface, and with DVI interface data transmission to external display device, thereby utilize the single-chip to realize Dual-Link DVI, compare with the scheme that adopts a plurality of chips conversion and switching realization Dual-Link DVI among the prior art, very big saving the integrated circuit board area.

According to some embodiments of the present invention, the FPGA chip includes an I/O serial-to-parallel conversion interface, the device further includes a DVI driver chip;

the I/O serial-parallel conversion interface is connected with the DVI driving chip and used for converting the DVI interface data into low-voltage differential signals and transmitting the low-voltage differential signals to the DVI driving chip;

DVI driver chip, DVI driver chip with double-link DVI interface connection is used for with low-voltage differential signal converts transition modulation differential signal into, and will transition modulation differential signal transmits extremely double-link DVI interface, double-link DVI interface be used for with transition modulation differential signal transmits extremely outside display device.

According to some embodiments of the present invention, the FPGA chip further comprises:

and the DVI encoder is connected with the I/O serial-parallel conversion interface and used for converting the RGB data into the DVI interface data and transmitting the DVI interface data to the I/O serial-parallel conversion interface.

According to some embodiments of the present invention, the FPGA chip further comprises:

and the bit width matcher is respectively connected with the DVI encoder and the I/O serial-parallel conversion interface and is used for adjusting the bit width of the DVI interface data to be matched with the bit width supported by the I/O serial-parallel conversion interface.

According to some embodiments of the present invention, the FPGA chip further comprises:

an I2C bus interface, the I2C bus interface being connected with the DVI driver chip, the DVI driver chip being connected with the external display device;

and the processor is respectively connected with the I2C bus interface and the I/O serial-parallel conversion interface, and is used for acquiring the resolution of the external display equipment through the I2C bus interface and the DVI driving chip and adjusting the transmission rate of the I/O serial-parallel conversion interface according to the resolution of the external display equipment.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of an apparatus for implementing a dual-link DVI based on an FPGA according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an apparatus for implementing a dual-link DVI based on an FPGA according to another embodiment of the present invention.

Reference numerals:

FPGA chip 100, I/O serial-parallel conversion interface 110, DVI encoder 120, bit width matcher 130, I2C bus interface 140, processor 150, dual-link DVI interface 200, external display device 300, DVI driver chip 400.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated with respect to the orientation description, such as up, down, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, a plurality of means are one or more, a plurality of means are two or more, and the terms greater than, less than, exceeding, etc. are understood as not including the number, and the terms greater than, less than, within, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless there is an explicit limitation, the words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in combination with the specific contents of the technical solution.

As shown in fig. 1, an embodiment of the present invention provides a schematic structural diagram of an apparatus for implementing a dual-link DVI based on an FPGA. The device includes:

the FPGA chip 100 is used for converting the RGB data into DVI interface data;

the Dual-Link DVI interface 200 (i.e., Dual-Link DVI interface), the Dual-Link DVI interface 200 for receiving DVI interface data and transmitting the DVI interface data to the external display device 300.

In some embodiments, the apparatus of the present embodiment is implemented based on s720-fds boards. The s720-fds board is a display switch board and needs to support Dual-Link DVI display with a resolution of 2560X 1600. The device of the embodiment is arranged on an s720-fds board card, the board card receives Displayport (digital video interface standard) data from a host (or other equipment), converts the Displayport data into RGB data and transmits the RGB data to an FPGA chip, the RGB data is processed by the FPGA chip, and finally DVI interface data is output through a dual-link DVI interface and is sent to external display equipment (such as a display). It should be noted that the s720-fds board card can receive multiple Displayport signals at the same time, output multiple DVI interface data, and switch the multiple DVI interface data as required. Every way DVI interface data only needs a plurality of IO pins on the FPGA chip just can accomplish corresponding function, utilizes single-chip to realize Dual-Link DVI promptly, compares with the scheme that adopts a plurality of chip conversions and switch to realize Dual-Link DVI among the prior art, very big saving the integrated circuit board area.

In some embodiments, the FPGA chip selects KintexUltraScale series of Xilinx, the rate of I/O output differential signals is not less than 1600Mbps, and the Dual-Link DVI interface is supported to output DVI interface data to a display with the resolution of 2560X1600/60 Hz.

In some embodiments, as shown in fig. 2, FPGA chip 100 includes I/O serial-to-parallel conversion interface 110, the apparatus further includes DVI driver chip 400;

the I/O serial-parallel conversion interface 110 is connected to the DVI driver chip 400, and is configured to convert DVI interface data into a low-voltage differential signal and transmit the low-voltage differential signal to the DVI driver chip 400;

DVI driver chip 400, DVI driver chip 400 is connected with two-link DVI interface 200 for convert the low voltage differential signal into the transition modulation differential signal, and transmit the transition modulation differential signal to two-link DVI interface 200, two-link DVI interface 200 is used for transmitting the transition modulation differential signal to external display device 300.

In some embodiments, in order to enhance the transmission distance, a dedicated DVI driver chip 400 is selected, so as to better ensure the DVI transmission quality, and convert LVDS (Low-Voltage Differential Signaling) into TMDS (Transition Minimized Differential Signaling) used by a dual-link DVI interface.

In some embodiments, as shown in fig. 2, the FPGA chip 100 further includes:

and the DVI encoder 120 is connected with the I/O serial-parallel conversion interface 110, and is used for converting the RGB data into DVI interface data and transmitting the DVI interface data to the I/O serial-parallel conversion interface 110.

In some embodiments, the s720-fds board receives Displayport data from a host (or other device), converts the Displayport data into RGB data, and transmits the RGB data to the DVI encoder 120, the DVI encoder 120 encodes the RGB data according to the DVI encoding method, converts the RGB data into DVI interface data, and transmits the DVI interface data to the I/O serial-parallel conversion interface 110, and the I/O serial-parallel conversion interface 110 transmits the encoded DVI interface data to the DVI driver chip 400 in serial.

In some embodiments, as shown in fig. 2, the FPGA chip 100 further includes:

the bit width matcher 130 and the bit width matcher 130 are respectively connected to the DVI encoder 120 and the I/O serial-parallel conversion interface 110, and are configured to adjust a bit width of DVI interface data to match the bit width supported by the I/O serial-parallel conversion interface 110.

In some embodiments, bit width matcher 130 converts the bit width of the DVI interface data into a bit width required by the I/O parallel-to-serial conversion interface, thereby facilitating better transmission.

In some embodiments, the FPGA chip 100 further includes:

the I2C bus interface 140, the I2C bus interface 140 are connected with the DVI driver chip 400, and the DVI driver chip 400 is connected with an external display device;

and the processor 150, the processor 150 is respectively connected to the I2C bus interface 140 and the I/O serial-parallel conversion interface 110, and is configured to obtain the resolution of the external display device 300 through the I2C bus interface 140 and the DVI driver chip 400, and adjust the transmission rate of the I/O serial-parallel conversion interface 110 according to the resolution of the external display device 300.

In some embodiments, the processor 150 reads the resolution of the external display device 300 through the I2C bus interface 140 and the DVI driver chip 400, and dynamically adjusts the rate of the I/O serial-parallel conversion interface 110 at which DVI interface data is transmitted according to the resolution of the external display device 300. It should be noted that, by querying the communication standard protocol, the transmission rate of the I/O port corresponding to each resolution is queried, and as a result, the transmission rate does not exceed 1600Mbps, so in this embodiment, the transmission rate of the I/O serial-parallel conversion interface 110 is 1600Mbps, which can meet the design requirement.

In some embodiments, the processor 150 is further configured to dynamically configure the clock of the I/O serial-to-parallel conversion interface 110 to accommodate different resolution requirements for the output clock rate.

The devices selected in the embodiment are all industrial chips, and can be used in various severe environments. The FPGA chip has more flexible configuration, is convenient to integrate more functions, is used under the condition of strict requirement on the volume, simultaneously does not need to arrange RGB lines on the PCB in parallel, and greatly simplifies the PCB wiring. Meanwhile, the number of devices is greatly reduced, the area of the PCB is reduced, and the application of the military industry field and other harsh environments is well met.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.

The above-described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may also be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims (5)

1. Device based on FPGA realizes dual link DVI, its characterized in that includes:

the FPGA chip is used for converting the RGB data into DVI interface data;

a dual-link DVI interface for receiving the DVI interface data and transmitting the DVI interface data to an external display device.

2. The FPGA-based dual-link DVI apparatus of claim 1 wherein said FPGA chip includes an I/O serial-to-parallel conversion interface, said apparatus further comprising a DVI driver chip;

the I/O serial-parallel conversion interface is connected with the DVI driving chip and used for converting the DVI interface data into low-voltage differential signals and transmitting the low-voltage differential signals to the DVI driving chip;

the DVI driver chip with double-link DVI interface connection for with low-voltage differential signal converts the transition modulation differential signal into, and will transition modulation differential signal transmits extremely double-link DVI interface, double-link DVI interface be used for with transition modulation differential signal transmits extremely external display device.

3. The apparatus of claim 2, wherein the FPGA chip further comprises:

and the DVI encoder is connected with the I/O serial-parallel conversion interface and used for converting the RGB data into the DVI interface data and transmitting the DVI interface data to the I/O serial-parallel conversion interface.

4. The apparatus of claim 3, wherein the FPGA chip further comprises:

and the bit width matcher is respectively connected with the DVI encoder and the I/O serial-parallel conversion interface and is used for adjusting the bit width of the DVI interface data to be matched with the bit width supported by the I/O serial-parallel conversion interface.

5. The apparatus of claim 4, wherein the FPGA chip further comprises:

an I2C bus interface, the I2C bus interface being connected with the DVI driver chip, the DVI driver chip being connected with the external display device;

and the processor is respectively connected with the I2C bus interface and the I/O serial-parallel conversion interface, and is used for acquiring the resolution of the external display equipment through the I2C bus interface and the DVI driving chip and adjusting the transmission rate of the I/O serial-parallel conversion interface according to the resolution of the external display equipment.

Images