CN112702608A

CN112702608A - 2Lane LVDS video coding method and system

Info

Publication number: CN112702608A
Application number: CN202011555116.3A
Authority: CN
Inventors: 杨炳伟; 高伟林; 樊涛; 孙冲; 李连桂
Original assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Current assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Priority date: 2020-12-21
Filing date: 2020-12-21
Publication date: 2021-04-23
Anticipated expiration: 2040-12-21
Also published as: CN112702608B

Abstract

The invention provides a 2lane LVDS video coding method and a system, wherein the system comprises the following steps: the device comprises a synchronous code embedding module, an LVDS coding module, a phase-locked loop module and a reset module; the synchronization code embedding module is used for embedding synchronization code information required by hi3559 received data into a video stream; the LVDS coding module recombines video stream data on 2 lanes by adopting a FIFO _16to32 module, a FIFO _16to8 module and an 8bit _ to _1bit module and realizes parallel-serial conversion; the phase-locked loop module is used for providing an encoding clock of the LVDS encoding module; the reset module is used for ensuring that the fifo works normally, resetting the fifo when the LVDS coding module is initialized each time, and then sequentially starting the fifo through the delay module. The invention can provide the hi3559 with 2lane LVDS coding video signals with any resolution less than 1080P under the hardware bandwidth requirement of the hi 3559.

Description

2Lane LVDS video coding method and system

Technical Field

The present disclosure relates to the field of video encoding and decoding technologies, and in particular, to a 2lane LVDS video encoding method and system.

Background

LVDS, Low-voltage Differential Signaling, a Low-voltage Differential Signaling standard, is commonly used to transmit serial signal standards. The traditional LVDS coding is in the form of LVDS coding chips, one of which is to convert and code an existing video signal format into an LVDS level signal, and the LVDS signal complies with the LVDS display driving standard of a liquid crystal screen, for example, an LT8619C chip of dragon company codes an HDMI signal into an LVDS signal to drive a screen display. Another is an image detector, which directly encodes an image video signal into an LVDS signal output, which embeds synchronization codes in the signal, and some specific SOCs receive video data synchronously by judging the synchronization codes, such as image sensor IMX226 of sony corporation. The LVDS coding modes of the two modes adopt a chip to realize coding, so that no method is available if the chip scheme is not available in the market. For the haisi series SOC chips such as Hi3559, video interfaces with LVDS level standard are provided, which are originally applied to specific image sensor chips such as IMX226, but for some special application scenes such as transmitting PAL video signals or SDI video signals to Hi3559, no existing video conversion scheme is available on the market, and therefore, an FPGA is required to realize video conversion. When the FPGA is connected with the Hi3559, LVDS coding of the video is required to be completed according to the video time sequence of the Hi 3559. Therefore, it is necessary to provide a video encoding method, which can encode any resolution video signal with resolution less than 1080P into 2lane LVDS signal to the hi3559 under the hardware bandwidth requirement of the hi 3559.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a 2lane LVDS video encoding method and system, which can provide a 2lane LVDS encoded video signal with an arbitrary resolution smaller than 1080P for hi3559 under the requirement of hi3559 hardware bandwidth.

In order to achieve the above purpose, the invention provides the following technical scheme:

a2 lane LVDS video coding method comprises the following steps:

(1) the video data completes the embedding of the synchronous code through a synchronous code embedding module;

(2) two adjacent 16-bit pixel points are combined into 32-bit video data through a FIFO _16to32 module;

(3) the output image data carries out synchronous beat processing on the high 16 bits and the low 16 bits respectively, and then is input to an FIFO _16to8 module, and the FIFO _16to8 module divides the 16 bits into two front and back 8 bits of data;

(4) the output video stream signal is synchronously processed through a trigger;

(5) sending the video data to an 8bit _ to _1bit module, and serializing the 8bit data to obtain serial data;

(6) and outputting the serialized video data to the FPGA through the single-end to differential module.

Further, the clock input to the FIFO _16to32 module is clk1, and the output clock is clk2 divided by two.

Further, the FIFO _16to8 module input clock is clk2 divided by two and the output clock is pixel clock clk 1.

The invention also provides a 2lane LVDS video coding system, which comprises: the device comprises a synchronous code embedding module, an LVDS coding module, a phase-locked loop module and a reset module;

the synchronous code embedding module is used for embedding synchronous code information required by hi3559 for receiving data into a video stream;

the LVDS coding module comprises 1 FIFO _16to32 module, two FIFO _16to8 modules and two 8bit _ to _1bit modules (FIFO _8to1), and is used for recombining video data on 2 lanes and realizing parallel-serial conversion;

the phase-locked loop module is used for providing an encoding clock of the LVDS encoding module;

the reset module is used for ensuring that the fifo works normally, resetting the fifo when the LVDS coding module is initialized every time, and then sequentially starting the fifo through the delay module.

Further, the input video data of the synchronization code embedding module is 16-bit video data in YUV420 format.

Further, the synchronization code information required for the hi3559 to receive data includes a frame start synchronization code, a frame end synchronization code, a line start synchronization code, and a line end synchronization code.

The system further comprises a trigger module, wherein the trigger module is used for synchronously triggering the data in the process of transferring the data from one module to the next module so as to optimize the time sequence.

The invention discloses a 2lane LVDS video coding method and a system thereof, which have the advantages that: the FF module is used for synchronous time sequence optimization, and the FIFO is used as a data conversion medium, so that the design has good time sequence characteristics, and meanwhile, video signals with any resolution of less than 1080P can be encoded into 2lane LVDS signals to be transmitted to hi3559 under the requirement of hardware bandwidth. The coding method has the advantages of stable coding time sequence, strong universality and the like.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a block diagram of an implementation of LVDS video coding by 2lane in an embodiment of the present invention;

FIG. 2 is a timing diagram illustrating synchronization code embedding in accordance with an embodiment of the present invention;

FIG. 3 is a schematic diagram of clock generation in an embodiment of the present invention;

FIG. 4 is a schematic diagram of reset signal generation in an embodiment of the present invention;

FIG. 5 is a block diagram of an LVDS coding module according to an embodiment of the invention.

Detailed Description

The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

The block diagram of the 2lane LVDS video coding method is shown in FIG. 1, and is a 2lane LVDS coding method implementation block diagram, which mainly comprises a synchronous code embedding module, an LVDS coding module, a phase-locked loop module and a reset module.

1. Synchronous code embedded module

The synchronous code embedding module embeds the synchronous code information required by hi3559 receiving data into a video stream; the input video data of the synchronous code embedding module is 16-bit video data in YUV420 format; the format of the synchronization code required by hi3559 is shown in table 1, and is described as 16-ary, including a frame start synchronization code, a frame end synchronization code, a line start synchronization code, and a line end synchronization code; the sync code data is represented by 4 data of 16 bits to be embedded in the video stream instead of the corresponding image signal.

Table 1: synchronous code format

Frame start synchronization code	FFFF	0000	0000	SAV
					End of frame synchronization code	FFFF	0000	0000	EAV
Line start sync code	FFFF	0000	0000	SOL
					Line end synchronization code	FFFF	0000	0000	EOL

As shown in fig. 2, let the resolution of the video signal be m.n, the start-of-frame synchronization code is used as the start flag of the video active signal on line 1 of a field of video active signal, and the end-of-frame synchronization code is used as the end flag of the video active signal on line m of a field of video active signal; the line start synchronous code is used as a video effective start mark of a line 2 to a line m, and the line end synchronous code is used as an end mark of a line 1 to a line m-1.

The principle of the synchronization code embedding module of the present invention is shown in fig. 2, because the video stream data has only one channel, and the video data encoded by the last LVDS is 2 channels, and each LVDS channel needs to be embedded with the synchronization code data. The invention provides a concept that a synchronization code pair required for separating adjacent pixels subsequently is embedded into a video stream in a synchronization code embedding module, as shown in fig. 2, and the synchronization code data is FFFF, 0000, 0000, 0000, SAV (or EAV, EAV or SOL, SOL or EOL, EOL). As described in the previous paragraph, sync code data is embedded on both sides of the video DE signal, respectively. And the original video stream data is retained during the video active signal period, i.e., during the DE high level period.

1. Phase-locked loop module

The phase-Locked loop module provides an LVDS encoded clock, as shown in fig. 3, with a pixel clock clk1 of the input video, a frequency divided clock clk2, and a frequency multiplied clock clk3, where the Locked signal is a clock stable flag indicating that the phase-Locked loop operates stably. The relationship between the phase-locked loop generated clock and the pixel clock is clk 2-0.5 clk1, and clk 3-8 clk 1.

3. Reset module

The reset signal is used for ensuring that the fifo works normally, resetting the fifo when the LVDS coding module is initialized every time, and then sequentially starting the fifo through the delay module, so that the fifo works more stably. Without the reset signal, the phenomenon that the U component and the V component of the image are opposite when the input image disappears can be caused each time, and the picture color is distorted. The reset signals rst1 and rst2 are generated by delay blocks delay1 and delay2, corresponding to delayed beats half the fifo depth in fig. 5.

4. LVDS coding module

The functional block diagram of the LVDS coding module according to the present invention is shown in fig. 5, and includes 1 FIFO (FIFO _16to32) with 16 bits to32 bits, two FIFO (FIFO _16to8) with 16 bits to8 bits, and two modules (serialization modules) with 8 bits to1 bit. In addition, clk1, clk2 and clk3 signals are from a phase-locked loop module, and rst1 and rst2 signals are from a reset module. Synchronous trigger processing is required to be carried out on data through a trigger module (FF) in the process of transferring the data from one module to the next module, and the time sequence is optimized.

The principle and the working sequence of the LVDS coding module are as follows:

(1) the video data comes from a synchronous code embedding module, and the format of the synchronous code is shown in FIG. 2;

(2) two pixel points of 16 bits are combined into 32-bit video data through a FIFO _16to32 module, so that adjacent image data are distributed on two different lanes, and the two pixel point data become synchronous data. The input clock to FIFO _16to32 is clk1 and the output clock is clk2 divided by two.

(3) The output image data carries out synchronous beat processing on the high 16 bits and the low 16 bits respectively, and then is input to the FIFO _16to8 module, the FIFO _16to8 module divides the 16 bits of data into two front and back 8 bits of data, the input clock is clk2 divided by two, and the output clock is pixel clock clk 1.

(4) The output video stream signals are processed synchronously through the trigger, so that the video timing can be optimized.

(5) And sending the video data to an 8bit _ to _1bit module, and serializing the 8bit data to obtain serial data.

The present invention will be described in detail with reference to the following embodiments and accompanying drawings.

Assuming that the input resolution is 1080P 30Hz (1920 x 1080, clock frequency 74.25Hz), clk1 used in this example is 74.25Mhz, clk2 is a divide-by-two of clk1, is 37.125Mhz, clk3 is 594Mhz, and Xilinx K7325T is used as a logic operation platform.

The format of the synchronization code is the data shown in table 1, wherein the 16 th system of SAV is 8080, the 16 th system of EAV is 9d9d, the 16 th system of SOL is abab, and the 16 th system of EOL is b6b 6;

the FIFO _16to32 module is a FIFO module with the depth of 512 and the conversion from 16 bits to32 bits;

the FIFO _16to8 module is a FIFO module with the depth of 512 and the conversion from 16 bits to8 bits; the FF module is a trigger time sequence synchronization of 2 beats;

the 8bit _ to _1bit module is an Oserdes module of the Xilinx FPGA and is set to be 8bit input and 1bit serial output;

the single-end conversion differential module is OBUF _ DIFF of the Xilinx FPGA.

The flow of LVDS coding is as follows:

1) and the video data passes through the synchronous code embedding module to complete the embedding of the synchronous codes.

2) Two pixels of 16 bits are combined into 32-bit video data through a FIFO _16to32 module, so that adjacent image data are distributed on two different lanes, and the two pixel data become synchronous data, the clock input by the FIFO _16to32 is clk1, and the output clock is clk2 with frequency division of two.

3) The output image data carries out synchronous beat processing on the high 16 bits and the low 16 bits respectively, and then is input to the FIFO _16to8 module, the FIFO _16to8 module divides the 16 bits of data into two front and back 8 bits of data, the input clock is clk2 divided by two, and the output clock is pixel clock clk 1.

4) The output video stream signals are processed synchronously through the trigger, so that the video timing can be optimized.

5) And sending the video data to an 8bit _ to _1bit module, and serializing the 8bit data to obtain serial data.

6) And outputting the serialized video data to the FPGA through the single-end to differential module.

In the above embodiments, if the input resolution and the clock signal are directly adjusted to change the resolution, 2lane LVDS encoding can be completed.

For the hi3559 platform, the bandwidth of 2lane LVDS coding is limited by FPGA and hi3559 MIPI rx serial receiving module, theoretically, the video format of 2lane LVDS coding transmission does not exceed 1080P 30Hz at most.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A2 lane LVDS video coding method is characterized by comprising the following steps:

2. The LVDS video coding method with 2lane according to claim 1, wherein the clock input to the FIFO _16to32 module is clk1, and the output clock is clk2 divided by two.

3. The LVDS video coding method of 2lane according to claim 1, wherein the input clock of the FIFO _16to8 module is clk2 divided by two, and the output clock is pixel clock clk 1.

4. A 2lane LVDS video coding system, comprising: the device comprises a synchronous code embedding module, an LVDS coding module, a phase-locked loop module and a reset module;

the LVDS coding module comprises 1 FIFO _16to32 module, two FIFO _16to8 modules and two 8bit _ to _1bit modules, and is used for recombining video stream data on 2 lanes by adopting the FIFO _16to32 module, the FIFO _16to8 module and the 8bit _ to _1bit module and realizing parallel-serial conversion;

5. The 2lane LVDS video coding system according to claim 4, wherein the input video data of the synchronization code embedding module is 16-bit YUV420 format video data.

6. The 2lane LVDS video coding system according to claim 4, wherein the synchronization code information required by the hi3559 to receive data includes a frame start synchronization code, a frame end synchronization code, a line start synchronization code, and a line end synchronization code.

7. The 2lane LVDS video coding system according to claim 4, further comprising a trigger module for synchronously triggering processing of data during its transfer from one module to the next to optimize timing.