CN117009273A - HDMI receiving end interface controller processing method based on FPGA - Google Patents
HDMI receiving end interface controller processing method based on FPGA Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G06F15/00—Digital computers in general; Data processing equipment in general
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Abstract
The application provides a processing method of an HDMI receiving end interface controller based on an FPGA, which comprises a differential-to-single-end module, a serial-to-parallel module, a multi-bit synchronous data conversion module and a 10-bit synchronous data conversion module, wherein the differential-to-single-end module is used for receiving an image sent by an HDMI sending end, decomposing the image into a differential clock channel containing clock data information and a differential data channel containing the differential data information, respectively converting the differential clock channel into first differential data information and first clock data information, then sending the first differential data information and the first clock data information to a phase alignment module, adjusting the phases of the two channels, sending the phase alignment module to the serial-to-parallel module, converting serial data into multi-bit synchronous data, and then sending the multi-bit synchronous data to the 10-bit synchronous data module, and the multi-bit synchronous data into 8-bit synchronous data, wherein the multi-bit synchronous data comprises pixel points and line field synchronous information used for determining an effective area of the image, and calculating the resolution of the image according to the effective area.
Description
Technical Field
The application relates to the technical field, in particular to an HDMI receiving end interface controller processing method based on FPGA.
Background
The existing control of the HDMI interface is mainly FPGA (Field Programmable Gate Array) + physical layer coding and decoding chip or CPU (Central Processing Unit) + physical layer coding and decoding chip; the limitation of this approach is that the need to external physical layer chips limits the flexibility and interchangeability of the system (e.g., where the hardware board area requirements are high or where the cost control requirements are high), and processing the data becomes difficult when the sampling rate is too high.
Disclosure of Invention
The application aims to solve the problems, and provides a processing method of an HDMI receiving end interface controller based on an FPGA, which comprises the following steps:
the differential-to-single-ended module is configured to receive an image sent by an HDMI sending end, decompose the image into clock data information in a differential clock channel and differential data information in the differential data channel, convert the clock data information into first clock data information, convert the differential data information into first differential data information, and enable the first clock data information and the first differential data information to be serial data;
the phase alignment module is configured to receive and adjust phases of the differential clock channel and the differential data channel, align the differential clock channel and the differential data channel, and respectively form a first differential clock channel and a first differential data channel;
the serial-to-parallel module is configured to receive first clock data information in the first differential clock channel and first differential data information in the first differential data channel and convert the first clock data information and the first differential data information into multi-bit parallel synchronous data;
the 10-bit-to-8-bit module is configured to receive the multi-bit parallel synchronous data and convert the multi-bit parallel synchronous data into 8-bit parallel data, the 8-bit parallel data comprises color information of a plurality of R, G, B channels and line field synchronous information, each R, G, B channel color information forms a pixel point, the line field synchronous information is used for determining an effective area of an image, and the resolution of the image in the effective area is calculated according to the effective area of the image.
According to the technical scheme provided by the embodiment of the application, the steps of decomposing the image into clock data information in the differential clock channel and differential data information in the differential data channel specifically comprise:
the clock data information and the differential data information comprise a forward end and a reverse end, the forward end is connected with a differential data positive input pin of the differential input buffer, the reverse end is connected with a differential data negative input pin of the differential input buffer, and a data buffering output pin of the differential input buffer is connected with the phase alignment module.
According to the technical scheme provided by the embodiment of the application, the step of converting the clock data information into the first clock data information comprises the following steps:
and inputting the clock data information into the differential-to-single-ended module to obtain first sub-clock data information, and inputting the first sub-clock data information into the PLL module to obtain the first clock data information, wherein the first clock data information comprises a 1-time clock and a 5-time clock.
According to the technical scheme provided by the embodiment of the application, the step of adjusting the phases of the differential clock channel and the differential data channel to align the phases comprises the following steps:
and performing phase adjustment by using a delay clock built in the FPGA chip.
According to the technical scheme provided by the embodiment of the application, in the phase adjustment process, the counter circuit is utilized to count the differential clock channel and the data identification bits of the differential data channel, and when the differential clock channel and the data identification bits of the differential data channel are judged to be consistent, the differential clock channel and the differential data channel are judged to be aligned.
According to the technical scheme provided by the embodiment of the application, the serial-to-parallel module is configured to receive the second clock data information and the second differential data information and convert the second clock data information and the second differential data information into multi-bit parallel synchronous data, and the step of converting the multi-bit parallel synchronous data comprises the following steps:
and inputting the second clock data information and the second differential data information into a primitive input serializer to obtain the multi-bit parallel synchronous data of 2 bits, 8 bits, 10 bits and 14 bits.
According to the technical scheme provided by the embodiment of the application, the differential data channel comprises 3 sub-differential data channels, and each sub-differential data channel contains one piece of differential data information.
Compared with the prior art, the application has the beneficial effects that: the differential-to-single-ended module in the application firstly receives an image sent by an HDMI sending end, and decomposes the image into clock data information in a differential clock channel and differential data information in the differential data channel, and converts the clock data information and the differential data information to form first clock data information and first differential data information respectively, wherein the first clock data information and the first differential data information are serial data; then the phase alignment module receives and adjusts the phase between the differential clock channel and the differential data channel until the phases between the two channels are aligned, and forms a first differential clock channel and a first differential data channel respectively, and then the serial-to-parallel module receives the first clock data information in the first differential clock channel and the first differential data information in the first differential data channel and converts the first clock data information into multi-bit parallel synchronous data; then the 10-bit-to-8-bit module receives the multi-bit parallel synchronous data and converts the multi-bit parallel synchronous data into 8-bit parallel data, wherein the 8-bit parallel data comprises a plurality of R, G, B color information and row field synchronous information, each R, G, B color information can form a pixel point, the row field synchronous information can determine an effective area of an image, and then the resolution of the image in the effective area is calculated according to the effective area;
in the using process, the differential-to-single-end module receives signals sent by the HDMI sending end, wherein the signals comprise two channels, namely a differential clock channel and a differential data channel, the differential clock channel contains clock data information, the differential data channel contains differential data information, and then the differential-to-single-end module converts the two information respectively to form first clock data information and first differential data information, and the first clock data information and the first differential data information are serial data; the differential to single-ended module sends the differential clock channel with the first clock data information and the differential data channel with the first differential data information to the phase alignment module, the phase alignment module adjusts the phases of the two channels after receiving the differential clock channel and the differential data channel to align the phases of the two channels, the first differential clock channel and the first differential data channel are respectively formed after the two channels are aligned, the first differential clock channel still comprises the first clock data information after the two channels are formed, the first differential data channel still comprises the first differential data information, the phase alignment module sends the first differential data channel and the first differential clock channel and the signals respectively contained in the first differential clock channel to the serial to parallel module, after the serial-to-parallel module receives the information, the first differential data information and the first clock data information of the serial data are converted into multi-bit parallel synchronous data, the multi-bit parallel synchronous data are sent to a 10-bit to 8-bit module, the 10-bit to 8-bit module receives the multi-bit parallel synchronous data and converts the multi-bit parallel synchronous data into 8-bit parallel data, the 8-bit parallel data comprise a plurality of R, G, B channel color information and row field synchronous information, the channel color information of each R, G, B channel color information is a pixel point, the row field synchronous information is used for determining an effective area of an image, and after the effective area of the image is known, the resolution of the image in the effective area can be calculated according to the length and the width of the effective area; the application integrates the physical layer receiving function into the FPGA, reduces the use of external chips, can improve the compatibility of the system, can be applicable to occasions with higher requirements on the area of a hardware board card or occasions with higher requirements on cost control, and can calculate the resolution of an image without being externally connected with other chips for processing when the sampling rate is too high.
Drawings
FIG. 1 is a flow chart of a method according to an embodiment of the present application;
fig. 2 is an IBUFDS primitive device model provided in an embodiment of the present application;
FIG. 3 is an IDELAYE2 primitive device model provided by an embodiment of the present application;
FIG. 4 is a diagram of counting data identification bits provided by an embodiment of the present application;
FIG. 5 is a timing waveform design and calibration steps according to an embodiment of the present application;
fig. 6 is a configuration structure diagram of two primitive concatenation provided in an embodiment of the present application.
Detailed Description
In order that those skilled in the art may better understand the technical solutions of the present application, the following detailed description of the present application with reference to the accompanying drawings is provided for exemplary and explanatory purposes only and should not be construed as limiting the scope of the present application.
S1, a differential-to-single-ended module, wherein the differential-to-single-ended module is configured to receive an image sent by an HDMI (high definition multimedia interface) sending end, decompose the image into clock data information in a differential clock channel and differential data information in the differential data channel, convert the clock data information into first clock data information, convert the differential data information into first differential data information, and both the first clock data information and the first differential data information are serial data;
A. the step of decomposing the image into clock data information in the differential clock channel and differential data information in the differential data channel specifically comprises the following steps:
the clock data information and the differential data information comprise a forward end and a reverse end, the forward end is connected with a differential data positive input pin of the differential input buffer, the reverse end is connected with a differential data negative input pin of the differential input buffer, and a data buffering output pin of the differential input buffer is connected with the phase alignment module.
B. The step of converting the clock data information into first clock data information includes:
inputting the clock data information into the differential-to-single-ended module to obtain first sub-clock data information, and inputting the first sub-clock data information into a PLL module to obtain the first clock data information, wherein the first clock data information comprises a 1-time clock and a 5-time clock;
C. each of the sub-differential data lanes contains one of the differential data information.
Specifically, in this embodiment, the differential to single-ended module will firstly receive an image sent by the HDMI transmitting end, and decompose the image to obtain a differential clock channel and a differential data channel, where the differential clock channel includes clock data information, and the differential data channel includes differential data information, and then the differential to single-ended module will convert the clock data information into first sub-clock data information, and input the first sub-clock data information into a PLL (Phase-Locked Loop) module to obtain first clock data information, where the first clock data information includes a 1-time clock and a 5-time clock, and the PLL module may also align phases of the 1-time clock and the 5-time clock to ensure that data can be accurately received, that is, the received clock signal may be multiplied by the PLL module so as to keep synchronization with the received data. The clock after frequency multiplication can provide a more stable sampling rate to ensure that HDMI data is correctly read, differential data information is converted into first differential data information, after the conversion, the first clock data information and the first differential data information are serial data, and when the conversion is performed, an IBUFDS primitive (IBUFDS is a differential input buffer inside an FPGA chip and is used for converting differential signals into single-ended signals) inside the FPGA chip is utilized to convert the differential signals into the single-ended signals, and the specific conversion process is as follows: firstly, an image is decomposed to obtain a differential clock channel containing clock data information and a differential data channel containing differential data information, the clock data information and the differential data information both comprise a positive end and a negative end, the IBUFDS primitive comprises a differential data positive input pin, a differential data negative input pin and a data buffer output pin, as shown in fig. 2, the positive end is connected to the differential data positive input pin, namely an I pin, the negative end is connected to the differential data negative input pin, namely an IB pin, then the data buffer output pin, namely an O pin, is connected to a phase alignment module, and an IO (input output flag) bit of the IBUFDS primitive is set to be in a differential input mode, so that differential signals can be converted into single-ended signals, namely the first clock data information and the first differential data information are both single-ended signals and are serial data.
S2, a phase alignment module, wherein the phase alignment module is configured to receive and adjust phases of the differential clock channel and the differential data channel, align the differential clock channel and the differential data channel, and respectively form a first differential clock channel and a first differential data channel;
A. performing phase adjustment by using IDELAYE2 built in the FPGA chip;
B. and in the phase adjustment process, counting the differential clock channel and the data identification bit of the differential data channel by using a counter circuit, and judging that the differential clock channel is aligned with the differential data channel when judging that the differential clock channel is consistent with the data identification bit of the differential data channel.
Specifically, in this embodiment, because the lengths of the HDMI bus are inconsistent, the difference between the hardware board wiring and the video clocks with different resolutions may cause a phase difference between the differential data received by the HDMI, where the phase difference may cause jitter and distortion of the received differential data, so that the accuracy of the video data may be affected, so that the error rate of the collected video data may be particularly high, and therefore, it is required to design a phase alignment module to adjust the phase relationship between the differential clock channel and the differential data channel, so as to keep synchronization, thereby eliminating the influence caused by the phase difference, so as to ensure that the received video data can accurately restore original pixel point information, in the HDMI interface, one differential signal is transmitted through two lines, and is used for transmitting clock signals, and the other differential signal is used for transmitting video data, where the differential data channel includes 3 sub-differential data channels, each sub-differential data channel includes one differential data information, and in a specific adjustment process, the first clock differential data information after being converted by the differential signal conversion module and the first clock differential data channel are synchronously transmitted to an elyd, and the phase relationship between the first clock differential data channel and an elye-signal is adjusted to an elye-port model 2, and an eld 2 is implemented, and a phase relationship between the two-buffer is implemented, and an elye 2 is shown in an buffer model, and an buffer is implemented by an elye 2, and a phase-adjusted model is shown in an elye 2, and a model is in a phase-adjusted model, and a figure is 2:
TABLE 1
| Port (port) | Meaning of |
| I | Differential data positive input |
| IB | Differential data negative input |
| O | Data buffer output |
| C | Clock signal input |
| REGRST | Reset signal input |
| INC | Increasing or decreasing delay tap input signals |
| CE | Increasing or decreasing delay tap enable signal |
| DATAOUT | Data output signal |
The IDELAYE2 primitive can be divided into 64 delay taps, the delay of 78ps can be increased by adding one tap, the number of delay taps can be reduced or increased according to specific delay requirements, and when CE (increasing or decreasing delay tap enabling signal) and INC (increasing or decreasing delay tap input signal) are high-level signals at the same time, the number of delay taps can be increased; when CE is a high level signal and INC is a low level signal, the number of delay taps can be reduced; therefore, the phase alignment can be achieved by operating the high and low levels of CE and INC, in the phase adjustment process, a counter circuit is also required to be used to count the differential clock channel and the data identification bits of the differential data channel, as shown in fig. 4, the counter circuit is subjected to operations of adding one, holding or clearing according to the data combination of the front and back time, the timing waveform design diagram and the correction steps are as shown in fig. 5, when count=2 and the data is 354, the phase alignment of the differential signals received by the HDMI receiving end is synchronously completed, that is, when it is judged that the data identification bits of the two channels are consistent, it is possible to judge that the phases of the differential clock channel and the differential data channel are aligned, and form a first differential clock channel and a first differential data channel respectively after that, and in addition, when the primitive IDELAYE2 is used, IDELAYCTRL (module) needs to be combined simultaneously. The delay tap number of the IDELAYE2 is provided by a reference clock of IDELAYCTRL, the top-level instantiation primitive written by the two primitives is as follows, wherein the ser_data input by an IDATAIN (input data interface) port is data needing to be phase aligned, the IDELAYE2_out output by a DATAOUT (data output signal) port is data after being phase aligned, and the delay time of data output is controlled by a CE port and an INC port simultaneously.
S3, a serial-to-parallel module, wherein the serial-to-parallel module is configured to receive first clock data information in the first differential clock channel and first differential data information in the first differential data channel and convert the first clock data information and the first differential data information into multi-bit parallel synchronous data;
A. the serial-to-parallel module is configured to receive the second clock data information and the second differential data information and convert them into multi-bit parallel synchronous data, and the step of converting the multi-bit parallel synchronous data includes:
and inputting the second clock data information and the second differential data information into a primitive input serializer to obtain the multi-bit parallel synchronous data of 2 bits, 8 bits, 10 bits and 14 bits.
Specifically, in this embodiment, the first clock data information in the first differential clock channel and the first differential data information in the first differential data channel are input into the serial-to-parallel module for processing, and after the processing is completed, multi-bit parallel synchronous data can be obtained, and the serial-to-parallel module also uses the primitive ISERDESE (input serializer) in Xilinx. The primitive supports conversion of serial data streams into 2-bit, 8-bit, 10-bit, and 14-bit multi-bit parallel synchronization data. However, a set of primitives can only be converted into 8-bit parallel data at most, so in order to obtain 10-bit parallel data, a cascade structure of two ISERDESE2 primitives is required to be adopted in the design process, wherein one ISERDESE2 primitive is used as a host, the other ISERDESE2 primitive is used as a slave, and is used for processing the rest 2-bit data, and as shown in fig. 6, the configuration structure diagram of the cascade of two primitives is provided. It should be noted that: the parallel data output by ISERDESE2 is in a data format of high order and low order interchange, and the comparison table 2 is that:
TABLE 2
Q is the output of the ISERDESE2 primitive, D is the serial data stream required to be converted by design, the ISERDESE2 host template primitive can be given according to a cascade configuration schematic diagram of two primitives, wherein the port D is an input port of serial data, Q1-Q8 are output ports of parallel data after conversion, and a slave code only needs to connect the shifttin 1-shifttin 2 with the shifttout 1-shifttout 2 of the host after instantiating the host code again according to the configuration schematic diagram.
And S4, a 10-bit-to-8-bit module, wherein the 10-bit-to-8-bit module is configured to receive the multi-bit parallel synchronous data and convert the multi-bit synchronous data into 8-bit parallel data, the 8-bit parallel data comprises color information of a plurality of R, G, B channels and line field synchronous information, each R, G, B channel of color information forms a pixel point, the line field synchronous information is used for determining an effective area of an image, and the resolution ratio of the image in the effective area is calculated according to the effective area of the image.
Specifically, in this embodiment, after multi-bit parallel synchronous data is obtained, the multi-bit parallel synchronous data is input to a 10-bit to 8-bit module, 10-bit parallel data is converted into 8-bit parallel data, and the 8-bit parallel data includes R, G, B and line field synchronous information, where the line field synchronous information can be used to mark the start and end of a video image, and it generally sends a special signal at the start position of each video image for synchronous image processing and display, by which the effective area of the image can be determined, and the resolution of the image inside the effective area can be calculated according to the effective area of the image. The 10bit data by parallelization is defined as 10bit [9:0], and the output pixel value is defined as 8bit_data [7:0].
The part of key conversion algorithm to be operated is as follows:
wire[7:0]data；
assign data＝(10bit[9])？～10bit[7:0]:10bit[7:0]；
8bit_data[0]<＝data[0]；
8bit_data[1]<＝(10bit[8])？(data[1]^data[0]):(data[1]～^data[0])；
8bit_data[2]<＝(10bit[8])？(data[2]^data[1]):(data[2]～^data[1])；
8bit_data[3]<＝(10bit[8])？(data[3]^data[2]):(data[3]～^data[2])；
8bit_data[4]<＝(10bit[8])？(data[4]^data[3]):(data[4]～^data[3])；
8bit_data[5]<＝(10bit[8])？(data[5]^data[4]):(data[5]～^data[4])；
8bit_data[6]<＝(10bit[8])？(data[6]^data[5]):(data[6]～^data[5])；
8bit_data[7]<＝(10bit[8])？(data[7]^data[6]):(data[7]～^data[6])；
marking the start and end marks of a video image according to the line field synchronous signals; the number of lines of the one-field image can be calculated according to the rising edge of the effective signal in the effective area in the one-field image, the number of pixels of one line can be counted, and the resolution of the video image can be calculated.
The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. The foregoing is merely illustrative of the preferred embodiments of this application, and it is noted that there is objectively no limit to the specific structure disclosed herein, since numerous modifications, adaptations and variations can be made by those skilled in the art without departing from the principles of the application, and the above-described features can be combined in any suitable manner; such modifications, variations and combinations, or the direct application of the inventive concepts and aspects to other applications without modification, are contemplated as falling within the scope of the present application.
Claims (7)
1. An HDMI receiving terminal interface controller processing method based on FPGA is characterized by comprising the following steps:
the differential-to-single-ended module is configured to receive an image sent by an HDMI sending end, decompose the image into clock data information in a differential clock channel and differential data information in the differential data channel, convert the clock data information into first clock data information, convert the differential data information into first differential data information, and enable the first clock data information and the first differential data information to be serial data;
the phase alignment module is configured to receive and adjust phases of the differential clock channel and the differential data channel, align the differential clock channel and the differential data channel, and respectively form a first differential clock channel and a first differential data channel;
the serial-to-parallel module is configured to receive first clock data information in the first differential clock channel and first differential data information in the first differential data channel and convert the first clock data information and the first differential data information into multi-bit parallel synchronous data;
the 10-bit-to-8-bit module is configured to receive the multi-bit parallel synchronous data and convert the multi-bit parallel synchronous data into 8-bit parallel data, the 8-bit parallel data comprises color information of a plurality of R, G, B channels and line field synchronous information, each R, G, B channel color information forms a pixel point, the line field synchronous information is used for determining an effective area of an image, and the resolution of the image in the effective area is calculated according to the effective area of the image.
2. The method for processing the HDMI sink interface controller based on the FPGA of claim 1, wherein the step of decomposing the image into clock data information in the differential clock channel and differential data information in the differential data channel specifically comprises:
the clock data information and the differential data information comprise a forward end and a reverse end, the forward end is connected with a differential data positive input pin of the differential input buffer, the reverse end is connected with a differential data negative input pin of the differential input buffer, and a data buffering output pin of the differential input buffer is connected with the phase alignment module.
3. The method for processing the HDMI sink interface controller based on FPGA of claim 2, wherein the step of converting the clock data information into the first clock data information comprises:
and inputting the clock data information into the differential-to-single-ended module to obtain first sub-clock data information, and inputting the first sub-clock data information into the PLL module to obtain the first clock data information, wherein the first clock data information comprises a 1-time clock and a 5-time clock.
4. The method for processing the HDMI sink interface controller based on FPGA of claim 3, wherein said adjusting the phase of the differential clock channel and the phase of the differential data channel to align the differential clock channel and the differential data channel comprises:
and performing phase adjustment by using a delay clock built in the FPGA chip.
5. The method according to claim 4, wherein during the phase adjustment, a counter circuit is used to count the data identification bits of the differential clock channel and the differential data channel, and when it is determined that the data identification bits of the differential clock channel and the differential data channel are identical, it is determined that the differential clock channel is aligned with the differential data channel.
6. The method according to claim 5, wherein the step of converting the second clock data information and the second differential data information into multi-bit parallel synchronous data comprises:
and inputting the second clock data information and the second differential data information into an input serializer to obtain the multi-bit parallel synchronous data of 2 bits, 8 bits, 10 bits and 14 bits.
7. The method of processing an HDMI sink interface controller based on an FPGA of claim 6, wherein said differential data channels comprise 3 sub-differential data channels, each of said sub-differential data channels having one of said differential data information therein.
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| CN (1) | CN117009273A (en) |
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2023
- 2023-07-31 CN CN202310946188.8A patent/CN117009273A/en active Pending
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