CN113179359B - Serial image data training system based on synchronous words - Google Patents
Serial image data training system based on synchronous words Download PDFInfo
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- CN113179359B CN113179359B CN202110427711.7A CN202110427711A CN113179359B CN 113179359 B CN113179359 B CN 113179359B CN 202110427711 A CN202110427711 A CN 202110427711A CN 113179359 B CN113179359 B CN 113179359B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N5/04—Synchronising
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
Abstract
A serial image data training system based on synchronous words relates to a training system of a CMOS image sensor, and solves the problem that the image has a code disorder phenomenon caused by temperature drift in the imaging process due to the fact that the temperature change of a CMOS detector is large or the thermal control measure cannot ensure that the detector changes in a small temperature range in the prior art; the driving and control signals generated by the imaging controller are sent to the imaging detector after passing through the driving and control circuit; digital image data output by the imaging detector is processed by the imaging controller and then output by the data transmission interface circuit; a writing phase comprising an idle phase, a bit correction phase based on an accompanying clock, a word correction phase based on an accompanying clock, a channel correction phase based on a synchronous word and a training result; the invention can adapt to large-scale temperature change without special dynamic training.
Description
Technical Field
The invention relates to a training system of a CMOS image sensor, in particular to a serial image data training system based on synchronous words.
Background
CMOS image sensor applications, typically direct output of digital image data. Because digital image data has high quantization bit number and large data volume, the digital image data is transmitted in a serial mode. On the receiving side, it is necessary to perform serial-to-parallel conversion of input serial image data, and an adaptive adjustment process for accurately converting serial data into parallel data is called training.
In the application of high line frequency, the serial clock frequency of the CMOS detector is high, and the margin of serial image data sampling is small. When the temperature of the detector changes greatly or the thermal control measures cannot ensure that the detector changes in a small temperature range, the phenomenon of image distortion due to temperature drift may occur in the imaging process.
Aiming at long-time continuous imaging, one solution is to improve the design of a detector, and output serial image data and an accompanying clock adopt the same delay link, so that delay deviation caused by temperature change is avoided; meanwhile, before the effective image data is output, four synchronous words are output, the position of the effective image data is indicated through detection of the synchronous words, and the change of the position of the output effective image data caused by delay deviation of an external synchronous control signal at different temperatures is avoided. Therefore, the original training method needs to be improved, whether the channel training is successful or not is detected based on the synchronous words in the channel training stage, and the position of the last synchronous word and the relative delay pixel clock number of the synchronous control signal occur; after the channel training is finished, a data valid signal is generated after the last synchronous word is detected each time.
Disclosure of Invention
The invention provides a serial image data training system based on synchronous words, aiming at solving the problem that the phenomenon of image messy codes occurs in the imaging process due to temperature drift because the temperature change of the CMOS detector is large or the thermal control measure can not ensure that the detector is changed in a small temperature range in the prior art.
A serial image data training system based on synchronous words comprises an imaging detector, a driving and control circuit, an imaging controller, a memory and a data transmission interface circuit; the driving and control signals generated by the imaging controller are sent to the imaging detector after passing through the driving and control circuit; digital image data output by the imaging detector is processed by the imaging controller and then output by the data transmission interface circuit;
the training system comprises five stages, namely an idle stage, a bit correction stage based on an accompanying clock, a word correction stage based on the accompanying clock, a channel correction stage based on a synchronous word and a writing stage of a training result;
after a new channel training starting signal is detected in the idle stage, entering a bit correction stage based on an accompanying clock;
in the bit correction stage based on the accompanying clock, performing bit correction, and entering a word correction stage based on the accompanying clock after the bit correction is finished;
in the word correction stage based on the accompanying clock, carrying out word correction, and entering a channel correction stage based on synchronous words after the word correction is finished; in the channel correction stage based on the synchronous words, channel correction is carried out, and after the channel training is finished, a training result writing stage is started;
writing the training result in a writing stage of the training result, and entering an idle stage after the training result is written;
the channel training mode adopted in the channel correction phase based on the synchronous words is as follows: resetting the counter by using the positive pulse of the line trigger pulse signal sync, and stopping counting after the counter counts to the maximum line period length; simultaneously, clearing the final position of the channel correction by using the positive pulse of the line trigger pulse signal sync;
sequentially detecting a first synchronous word, a second synchronous word, a third synchronous word and a fourth synchronous word at four continuous positions, when the fourth synchronous word is detected, locking the current counting value of a counting signal, and marking the position 1 of a mark for successful channel training;
when the count value of the counter reaches the maximum line cycle length, a first synchronous word, a second synchronous word, a third synchronous word and a fourth synchronous word are not detected at four continuous positions in sequence, and the mark of successful channel training is set to be 0 at the low position;
and intercepting a non-zero value of the counting signal in the telemetry information, wherein the non-zero value represents that channel training is successful, and the non-zero value is a delay value of a sync pulse of a fourth synchronous word relative to a row trigger pulse signal sync pulse.
The invention has the beneficial effects that:
1. training is carried out based on a clock accompanying scheme, a sampling clock of serial data and the serial data synchronously change along with the temperature, and the phase deviation of the sampling clock and the serial data is kept within 40ps in the temperature change process, so that the situation that data sampling errors do not occur even for large-range temperature changes after the bit correction in the training process is successful can be ensured;
2. based on the synchronous word detection of four different modes, the situation that training is successful and the acquired image has messy codes due to different delay time caused by special code patterns can be avoided; when the sync word detection of four different modes can be detected correctly, the code patterns in different gray levels can be applied. The position of effective data is determined in real time through synchronous word detection of four different modes, large-range temperature change can be adapted, and special dynamic training is not needed.
Drawings
FIG. 1 is a schematic block diagram of a synchronous word-based serial image data training system according to the present invention;
FIG. 2 is a flow chart of a synchronous word-based serial image data training system according to the present invention;
FIG. 3 is a flowchart illustrating the steps of generating the valid data signal LVAL in the training system for serial image data based on sync word according to the present invention.
Detailed Description
The embodiment is described with reference to fig. 1 to 3, and a serial image data training system based on a sync word, such as the imaging system shown in fig. 1, includes an imaging detector, a driving and control circuit, an imaging controller, a memory and a data transmission interface circuit; the driving and control signals generated by the imaging controller are sent to the imaging detector after passing through the driving and control circuit. The digital image data output by the imaging detector is processed by the imaging controller and then output by the data transmission interface circuit.
In the embodiment, the relative phase of the parallel data output by the imaging detector and the accompanying clock changes little with the temperature, and the relative phase deviation of the output data and the accompanying clock does not exceed 40ps in the temperature change range of-55 ℃ to 125 ℃.
In this embodiment, the imaging detector outputs a training word after a training word control signal train is raised (high level), and outputs four synchronous words sync _ code first and then outputs light-sensitive image data under the condition of a normal working time sequence; the four synchronous words are different, the highest of the first synchronous word is 1, and the rest are 0; in the second synchronous word, the lowest bit is 0, and the rest are 1; the third synchronous character is the negation of the training character, and the fourth synchronous character is the negation of the lowest training character.
The training system of the present embodiment includes five stages, an idle stage, a bit correction stage based on an associated clock, a word correction stage based on an associated clock, a channel correction stage based on sync _ code, and a writing stage of a training result; after a new channel training starting signal is detected in the idle stage, entering a bit correction stage based on an accompanying clock; in the bit correction phase based on the accompanying clock, entering a word correction phase based on the accompanying clock after the bit correction is finished; in the word correction stage based on the accompanying clock, after the word correction is finished, entering a channel correction stage based on sync _ code; in a channel correction stage based on sync _ code (synchronous word), after channel training is finished, entering a writing stage of a training result; and in the writing stage of the training result, entering an idle stage after the training result is written.
The channel training mode in this embodiment is as follows: resetting a counter by using the positive pulse of the sync, and stopping counting after the counter counts to the maximum row period length; meanwhile, clearing the final position of the channel correction by using the positive pulse of the sync; when the first, second, third and fourth sync words are detected in four successive positions in sequence, the counting signal is intercepted when the fourth sync word is detected, and the successful channel training flag is set to high 1, while when the counting value of the counter has reached the maximum line period length and the first, second, third and fourth sync words have not been detected in four successive positions in sequence, the successful channel training flag is set to low 0. A non-zero value of the count signal in the telemetry message is intercepted, which represents that channel training was successful and is the delay of the fourth sync _ code relative to the sync pulse.
In this embodiment, the phase flow of generating the valid data signal LVAL mainly includes six phases, i.e., a blanking phase in which LVAL is low level, a first sync word detection phase, a second sync word detection phase, a third sync word detection phase, a fourth sync word detection phase, and a high level phase. When the detector is in a power-on reset or training stage, entering a blanking stage with LVAL at a low level; in a blanking stage that LVAL is low level, when power-on is finished and training is finished, entering a stage of detecting a first synchronous word; in the stage of detecting the first synchronous word, when the first synchronous word is detected, the stage of detecting the second synchronous word is entered; in the stage of detecting the second synchronous word, when the second synchronous word is detected, the stage of detecting the third synchronous word is entered, otherwise, the stage of detecting the first synchronous word is entered; in the stage of detecting the third synchronous word, when the third synchronous word is detected, the stage of detecting the fourth synchronous word is entered, otherwise, the stage of detecting the first synchronous word is entered; in the stage of detecting the fourth synchronous word, when the fourth synchronous word is detected, entering a stage of LVAL being high level, otherwise entering a stage of detecting the first synchronous word; when LVAL is high level, the first sync word detecting stage is entered after the counting is finished.
In this embodiment, the imaging detector uses a TDICMOS detector from long optical core corporation; the data transmission interface circuit adopts a TLK2711 chip; the driving and control circuit is mainly based on the level conversion chip 164245; the imaging controller mainly adopts an FPGA and a refreshing chip of Shanghai double-denier microelectronics corporation.
Claims (4)
1. A serial image data training system based on synchronous words comprises an imaging detector, a driving and control circuit, an imaging controller, a memory and a data transmission interface circuit; the driving and control signals generated by the imaging controller are sent to the imaging detector after passing through the driving and control circuit; digital image data output by the imaging detector is processed by the imaging controller and then output by the data transmission interface circuit;
the method is characterized in that:
the training system comprises five stages, namely an idle stage, a bit correction stage based on an accompanying clock, a word correction stage based on the accompanying clock, a channel correction stage based on a synchronous word and a writing stage of a training result;
after a new channel training starting signal is detected in the idle stage, entering a bit correction stage based on an accompanying clock;
in the bit correction stage based on the accompanying clock, performing bit correction, and entering a word correction stage based on the accompanying clock after the bit correction is finished;
in the word correction stage based on the accompanying clock, carrying out word correction, and entering a channel correction stage based on synchronous words after the word correction is finished; in the channel correction stage based on the synchronous words, channel correction is carried out, and after the channel training is finished, a training result writing stage is started;
writing the training result in a writing stage of the training result, and entering an idle stage after the training result is written;
the channel training mode adopted in the channel correction phase based on the synchronous words is as follows: resetting the counter by using the positive pulse of the line trigger pulse signal sync, and stopping counting after the counter counts to the maximum line period length; simultaneously, clearing the final position of the channel correction by using the positive pulse of the line trigger pulse signal sync;
sequentially detecting a first synchronous word, a second synchronous word, a third synchronous word and a fourth synchronous word at four continuous positions, when the fourth synchronous word is detected, locking the current counting value of a counting signal, and marking the position 1 of a mark for successful channel training;
when the count value of the counter reaches the maximum line cycle length, a first synchronous word, a second synchronous word, a third synchronous word and a fourth synchronous word are not detected at four continuous positions in sequence, and the mark of successful channel training is set to be 0 at the low position;
and intercepting a non-zero value of the counting signal in the telemetry information, wherein the non-zero value represents that channel training is successful, and the non-zero value is a delay value of a sync pulse of a fourth synchronous word relative to a row trigger pulse signal sync pulse.
2. The system of claim 1, wherein: the imaging detector outputs training words after outputting training word control signals train to be high level, and under the condition of normal working time sequence, four synchronous words are output firstly, and then photosensitive image data are output; the four synchronous words are different, the highest of the first synchronous word is 1, and the rest are 0; in the second synchronous word, the lowest bit is 0, and the rest are 1; the third synchronous word is taken as the inverse of the corresponding bit of the training word, and the fourth synchronous word is taken as the inverse of the LSB of the lowest bit of the training word.
3. The system of claim 1, wherein: after the channel training is finished, the imaging controller generates a driving working time sequence signal of the detector, and generates a data effective signal after a fourth synchronous word is detected;
the phase flow for generating the data valid signal LVAL mainly includes six phases, which are a blanking phase of a low level, a phase for detecting a first sync word, a phase for detecting a second sync word, a phase for detecting a third sync word, a phase for detecting a fourth sync word, and a phase of a high level;
when the imaging detector is in a power-on reset or training stage, entering a blanking stage of low level; in a blanking stage that LVAL is low level, when power-on is finished and training is finished, entering a stage of detecting a first synchronous word;
in the stage of detecting the first synchronous word, when the first synchronous word is detected, the stage of detecting the second synchronous word is entered;
in the stage of detecting the second synchronous word, when the second synchronous word is detected, the stage of detecting the third synchronous word is entered, otherwise, the stage of detecting the first synchronous word is entered;
in the stage of detecting the third synchronous word, when the third synchronous word is detected, the stage of detecting the fourth synchronous word is entered, otherwise, the stage of detecting the first synchronous word is entered;
in the stage of detecting the fourth synchronous word, when the fourth synchronous word is detected, entering a stage of LVAL being high level, otherwise entering a stage of detecting the first synchronous word;
when LVAL is high level, the first sync word detecting stage is entered after the counting is finished.
4. The system of claim 1, wherein: the relative phase of the serial data output by the imaging detector and the accompanying clock is within the range of-55 ℃ to 125 ℃ along with the temperature variation; the relative phase deviation of the output serial data and the accompanying clock does not exceed 40 ps.
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