CN204836358U - Linear array CCD drive arrangement - Google Patents

Abstract

The utility model provides a linear array CCD drive arrangement, includes power module (1), the minimum system circuit (2) of CPLD, level shifting circuit (3), linear array CCD interface circuit (4) and peripheral interface circuit (5). The power pin or the port of the minimum system circuit (2) of CPLD, level shifting circuit (3), linear array CCD interface circuit (4) and peripheral interface circuit (5) are connected respectively to the voltage output port of power module (1), the input port of level shifting circuit (4) is connected to the chronogenesis pulse output port of CPLD minimum system circuit (2), and the output of peripheral interface circuit (5) is then connected to the chronogenesis parameter control port of CPLD minimum system circuit (2), the chronogenesis input pin of linear array CCD interface circuit (4) is connected to the delivery outlet of level shifting circuit (3), the CCD sensor is installed on linear array CCD interface circuit (4). The utility model discloses a synchronous count mode generates linear array CCD drive chronogenesis, realizes the nimble control to chronogenesis parameters such as driving frequency and light integration time.

Description

A kind of line array CCD drive unit

Technical field

The utility model relates to a kind of photoelectric conversion device, particularly relates to a kind of Linear CCD Driver control device.

Background technology

Line array CCD, as a kind of novel semi-conductor integrated optoelectronic device, has that resolution is high, fast response time and a feature such as measuring range is large, and in dimensional measurement, picture point location and bar code scanning etc., application is very extensive.Can normally work under the time sequential pulse that CCD device only requires in the feature that meets drives, output photoelectric switching signal, and also due to the difference of structure, principle and performance, Linear CCD Driver difference is very large.Therefore, CCD driver' s timing controls to be an important technology in line array CCD application.

At present, the time sequence driving circuit of line array CCD drives method, EPROM to drive method, Micro Controller Unit (MCU) driving method and programmable logic device driving method etc. to realize mainly through digital circuit.Digital circuit drives and EPROM drives method to adopt discrete component design driven circuit, there is circuit structure complexity, does not have the problem of autgmentability.Utility model patent 201420623953.9 " the CCD drive circuit of hand-hold type Vertical Mill measurement for angle in 2 D instrument " adopts discrete digital circuit device layout CCD drive circuit, there is baroque problem.Patent 200620125875.5 " a kind of outer synchronization linear array CCD pickup drive controller " adopts Micro Controller Unit (MCU) driving method to generate driver' s timing by control single chip computer I/O mouth level, and main existence is high to single-chip microcomputer performance requirement, system resource takies large problem.The digital integrated circuit of CPLD be a kind of user according to needing separately constitutive logic function voluntarily, have that integrated level is high, speed be fast, feature that good reliability, flexibility are high, be suitable for, to sequential or the higher application scenario of combinational logic requirement, the application requirement of CCD driver' s timing can being met completely.Take CPLD as core design Linear Array CCD Driving Circuit, can realize controlling flexibly driver' s timing parameter, thus the integrated level of raising drive unit, stability and practicality.

Utility model content:

The purpose of this utility model proposes the line array CCD drive unit that a kind of structure is simple, integrated level is high, practical, solves existing drive unit Problems existing.

The utility model line array CCD drive unit comprises power module, CPLD minimum system circuit, level shifting circuit, line array CCD interface circuit and peripheral interface circuit.The voltage output end mouth of power module connects power pin or the port of CPLD minimum system circuit, level shifting circuit, line array CCD interface circuit and peripheral interface circuit respectively, for foregoing circuit is powered; The sequential output port of CPLD minimum system circuit connects the input of level shifting circuit; The output of level shifting circuit connects the sequential input pin of line array CCD interface circuit; The output of peripheral interface circuit connects the sequencing control port of CPLD minimum system circuit.

Power module is that whole line array CCD drive unit is powered, and according to the operating voltage requirement of CPLD, CCD and peripheral circuit device, provides 3.3V, 10V and 5V tri-kinds of direct voltage outputs respectively.

CPLD minimum system circuit comprises CPLD chip, crystal oscillating circuit, reset circuit, JTAG download circuit and status indicator lamp, crystal oscillating circuit, reset circuit and JTAG download circuit are connected with the pin of CPLD chip corresponding function respectively, and status indicator lamp is connected with the I/O mouth of CPLD.According to the driver' s timing requirement of corresponding model line array CCD, program generator during employing hardware description language design driven, is downloaded to file destination by jtag interface in CPLD chip and realizes the output of specific CCD driver' s timing after emulation testing checking.The feature that CPLD hardware programmable and the online repeated downloads of JTAG use, makes to be that the CCD design of driving timing sequence of core has very strong flexibility and autgmentability with CPLD.Both can adjust with satisfied application requirement to time sequence parameter according to actual conditions, and also can meet different model CCD under redesign driver and adjustment interface case and drive requirement.

The input of level shifting circuit connects the sequential output I/O mouth of CPLD minimum system circuit, the output of level shifting circuit connects CCD interface circuit, realize carrying out level conversion to meet the level demand of CCD driver' s timing to the pulse of CPLD output timing, and export the driver' s timing connection after conversion to CCD interface circuit.

The output of line array CCD interface circuit is connected line array CCD and level shifting circuit respectively with input.Line array CCD interface circuit is provided with ccd sensor, for line array CCD provides mounting interface and driver' s timing input interface.

The output of peripheral interface circuit connects the time sequence parameter control I/O mouth of CPLD minimum system circuit, realizes the setting of CPLD time sequence parameter.The input of peripheral interface circuit connects custom system as expansion mouth.CPLD monitors the level state of peripheral interface, realizes the flexible control to driver' s timing parameter according to interface level combinations of states, and directly exports the driver' s timing after adjustment.Monitoring to output timing and debugging can also be realized by peripheral interface circuit, ensure that time sequence parameter adjustment result meets application requirement.

Beneficial effect: the utility model take CPLD as core design line array CCD drive unit, and the simple integrated level of circuit structure is high, improves the reliability of drive circuit.Meanwhile, utilize that CPLD device operating frequencies is high, the feature of hardware programmable, this drive unit can improve the operating frequency of Linear CCD Driver, and realizes the flexible setting to time sequence parameter, has stronger practicality and autgmentability.

Accompanying drawing explanation

Fig. 1 is the example structure block diagram of the utility model line array CCD drive unit;

Fig. 2 is the schematic diagram of the CPLD minimum system circuit of the utility model line array CCD drive unit;

Fig. 3 is the utility model line array CCD drive unit time stimulatiom figure;

Fig. 4 is the CPLD time stimulatiom the result of the utility model line array CCD drive unit;

Fig. 5 is the actual Output rusults of driver' s timing of the utility model line array CCD drive unit.

In Fig. 1: power module 1, CPLD minimum system circuit 2, level shifting circuit 3, line array CCD interface circuit 4, peripheral interface circuit 5, CPLD chip 6, crystal oscillating circuit 7, reset circuit 8, JTAG download circuit 9 and status indicator lamp 10.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further details.

As shown in Figure 1, the utility model line array CCD drive unit comprises power module 1, CPLD minimum system circuit 2, level shifting circuit 3, line array CCD interface circuit 4 and peripheral interface circuit 5.

Power module 1 provides operating circuit for all modules of drive unit, and power module 1 voltage output end mouth connects power pin or the port of CPLD minimum system circuit 2, level shifting circuit 3, line array CCD interface circuit 4 and peripheral interface circuit 5 respectively; The time sequential pulse output port of CPLD minimum system circuit 2 connects the input port of level shifting circuit 3, and the time sequence parameter control port of CPLD minimum system circuit 2 then connects the output of peripheral interface circuit 5; The delivery outlet of level shifting circuit 3 connects the sequential input pin of line array CCD interface circuit 4; Ccd sensor is arranged on line array CCD interface circuit 4.

CPLD minimum system circuit 2 comprises CPLD chip 6, crystal oscillating circuit 7, reset circuit 8, JTAG download circuit 9 and status indicator lamp 10.As shown in Figure 2, crystal oscillating circuit 7, reset circuit 8 and JTAG download circuit 9 are connected with the pin of CPLD chip 6 corresponding function respectively.Status indicator lamp 10 is connected with the I/O mouth of CPLD chip 6.

In embodiment of the present utility model, line array CCD selects Toshiba TCD1711DG, and it is as quick cell size 4.7 μm × 4.7 μm, and pixel center distance 4.7 μm, clock pulse typical operating frequency is 1.0MHz.TCD1711DG driver' s timing is made up of transfer pulse SH, clock signal Φ 1, clock signal Φ 2, reset pulse RS and clamp pulse CP five road pulse signal.CPLD chip selection altera corp EPM240T100 chip, level shifting circuit selects 74HCT245 chip and 74HCT04 chip.

With the hardware circuit that the CPLD chip EPM240T100 selected is core design line array CCD TCD1711DG drive unit.As shown in Figure 1, the core cell that CPLD minimum system circuit 2 controls for driver' s timing, the driver' s timing met the demands is exported to line array CCD interface circuit 4, CPLD minimum system circuit 2 and is controlled by peripheral interface circuit 5 pairs of driver' s timing parameters by the output timing of CPLD minimum system circuit 2 after level shifting circuit 3.

According to the requirement of driver' s timing figure in TCD1711DG technical manual, VerilogHDL hardware description language is selected to carry out the programming of CCD driver' s timing.As shown in Figure 3, meet fixed relationship between the drive pulse signal of TCD1711DG five road, sequential node can be marked off according to driving pulse state transition.Synchronous counting variable is set, at each node, low and high level set is carried out to five road driving pulses successively according to variograph numerical value, thus realize the state transitions of pulse, export original driver' s timing pulse by CPLDI/O mouth.

Select suitable crystal oscillator as the clock source of CPLD, the operating frequency of the driver' s timing of design can meet the requirement of TCD1711DG completely.

Owing to increasing transfer pulse after the Charger transfer pulse of every frame driver' s timing, not impact is exported on CCD valid pixel, but CCD optical-integral-time can be changed.Therefore, when adopting synchronous counting patten's design CCD driver' s timing, Charger transfer pulse can also be counted set condition variable Q, thus realize the flexible control to CCD optical-integral-time.The level state of peripheral interface circuit 5 is scanned, the state variable count value corresponding according to the different optical-integral-time of interface level combinations of states setting CCD by CPLD.

After driver' s timing control program design completes, adopt software approach to carry out functional simulation checking, simulation result is shown in Fig. 4.

After software emulation checking is carried out to the driver' s timing of design, by JTAG mode, file destination is downloaded in the CPLD chip of drive unit.Utilize oscilloscope to monitor the driver' s timing that line array CCD interface circuit 4 exports CCD to, as shown in Figure 5, time sequence parameter meets the requirement of TCD1711DG technical manual to actual driver' s timing Output rusults.

Claims (3)

1. a line array CCD drive unit, it is characterized in that, described line array CCD drive unit comprises power module (1), CPLD minimum system circuit (2), level shifting circuit (3), line array CCD interface circuit (4) and peripheral interface circuit (5); The voltage output end mouth of power module (1) connects power pin or the port of CPLD minimum system circuit (2), level shifting circuit (3), line array CCD interface circuit (4) and peripheral interface circuit (5) respectively; The time sequential pulse output port of CPLD minimum system circuit (2) connects the input port of level shifting circuit (4), and the time sequence parameter control port of CPLD minimum system circuit (2) then connects the output of peripheral interface circuit (5); The delivery outlet of level shifting circuit (3) connects the sequential input pin of line array CCD interface circuit (4); Ccd sensor is arranged on line array CCD interface circuit (4).

2. according to line array CCD drive unit according to claim 1, it is characterized in that, described CPLD minimum system circuit (2) comprises CPLD chip (6), crystal oscillating circuit (7), reset circuit (8), JTAG download circuit (9) and status indicator lamp (10); Crystal oscillating circuit (7), reset circuit (8) are connected with the pin of CPLD chip (6) corresponding function respectively with JTAG download circuit (9), and status indicator lamp (10) is connected with the I/O mouth of CPLD chip (6).

3. according to line array CCD drive unit according to claim 1, it is characterized in that, the output timing of described CPLD minimum system circuit (2) is after level shifting circuit (3), the driver' s timing met the demands is exported to line array CCD interface circuit (4), CPLD minimum system circuit (2) is controlled driver' s timing parameter by peripheral interface circuit (5).