CN204834628U - Semiconductor transistor packaging structure - Google Patents
Semiconductor transistor packaging structure Download PDFInfo
- Publication number
- CN204834628U CN204834628U CN201520186070.0U CN201520186070U CN204834628U CN 204834628 U CN204834628 U CN 204834628U CN 201520186070 U CN201520186070 U CN 201520186070U CN 204834628 U CN204834628 U CN 204834628U
- Authority
- CN
- China
- Prior art keywords
- chip
- tie line
- semiconductor transistor
- metal tie
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 22
- 229910052737 gold Inorganic materials 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 238000003466 welding Methods 0.000 abstract description 4
- 238000012797 qualification Methods 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract 1
- 238000004891 communication Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000007747 plating Methods 0.000 description 4
- 239000004568 cement Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
A semiconductor transistor package structure is suitable for the package structure of the transistor such as the insulated gate bipolar transistor or the metal-oxide-semiconductor field effect transistor, etc. the semiconductor transistor package structure is mainly used as the connecting wire of the electrical connection between the chip and the lead frame or the base circuit board, and the second layer of metal is plated before welding, so as to reduce the defects of easy oxidation, difficult jointing, etc. of the connecting wire, not only improve the speed and qualification rate of the semiconductor transistor during packaging, but also prolong the service life of the transistor.
Description
Technical field
The utility model relates to a kind of semiconductor transistor encapsulating structure, particularly one applies to as insulated gate bipolar transistor (IGBT, or the semiconductor transistor encapsulating structure of the transistor such as metal-oxide half field effect transistor (MOSFET, Metal-Oxide-SemiconductorField-EffectTransistor) InsulatedGateBipolarTransistor).
Background technology
Semiconductor transistor encapsulating structure, as shown in Figure 1, main containing lead frame or pedestal circuit board 3, be provided with in it and connect weld pad 31, the second end 52 for communication conductive wire 5 connects to be used, this lead frame or pedestal circuit board 3 utilize cement 2 to be bonded with chip 1, this chip 1 is provided with chip pad 11, in this chip pad 11, weldering is provided with gold stud bump 4, and together with the first end 51 of communication conductive wire 5 is welded on this gold stud bump 4, what be so communicated with between chip 1 and lead frame or pedestal circuit board 3 is electrical, but the material being generally used for communication conductive wire 5 is in order to reduce costs and take robustness into account, copper how can be utilized for the material of communication conductive wire 5, but the quality of copper is harder, plastotype comparatively differs, and copper engages not easily with gold, can allow the boding difficulties of communication conductive wire 5 and gold stud bump 4, and the material of copper has oxidizable characteristic, once produce oxidation, just the function electrically conducted can be affected, therefore easily shorten the useful life of semiconductor transistor and reduce manufacture qualification rate.
Prior art
Chip 1
Chip pad 11
Cement 2
Lead frame or pedestal circuit board 3
Connect weld pad 31
Gold stud bump 4
Communication conductive wire 5
First end 51
Second end 52
The utility model
Chip 10
Chip pad 101
Sticker 20
Lead frame or pedestal circuit board 30
Link weld pad 301
Gold stud bump 40
Metal tie line 50
Interior layer 501
Exterior layer 502
First end 5021
Second end 5022
Utility model content
Technical problem to be solved in the utility model is the problems referred to above in order to effectively solve prior art, a kind of semiconductor transistor encapsulating structure is provided, not only can improve the speed of transistor encapsulation process, improve outside process yields, the useful life of transistor can also be extended simultaneously.
To achieve these goals, the utility model provides a kind of semiconductor transistor encapsulating structure, wherein, comprising:
One lead frame or pedestal circuit board, the second end weldering be embedded with in this lead frame or pedestal circuit board for metal tie line is established and carries out the link weld pad of electrically connect;
One chip utilizing sticker to be fixedly installed, is placed in lead frame or pedestal circuit board, and the upper surface of this chip first end be provided with for metal tie line directly welds to establish and links with the chip pad forming electrically connect;
One for reaching the metal tie line of electrically connect, and include internal layer portion and outer portion, the chip pad of first end and chip is connected, and the second end and lead frame or pedestal circuit board are connected.
Above-mentioned semiconductor transistor encapsulating structure, wherein, the first end this chip pad is formed in advance for this metal tie line welds the gold stud bump establishing link.
Above-mentioned semiconductor transistor encapsulating structure, wherein, the material of the interior layer of this metal tie line is copper.
Above-mentioned semiconductor transistor encapsulating structure, wherein, the material of the exterior layer of this metal tie line is gold, silver or palladium.
Above-mentioned semiconductor transistor encapsulating structure, wherein, the exterior layer of this metal tie line is the periphery that electroplating is placed on this interior layer.
Beneficial functional of the present utility model is:
The utility model electrically welds after mainly utilizing and communication conductive wire being carried out two layers of metal plating in advance again, so can reduce that this communication conductive wire is oxidizable, the not easily disappearance such as joint, avoid communication conductive wire oxidation, improve the object not easily engaged, to reach the advantages such as the useful life of encapsulation speed, transistor qualification rate and the prolongation transistor with raising semiconductor transistor.
Below in conjunction with the drawings and specific embodiments, the utility model is described in detail, but not as to restriction of the present utility model.
Accompanying drawing explanation
Fig. 1 is the side-looking combination schematic diagram of prior art semiconductor transistor encapsulating structure;
Fig. 2 is the side-looking combination schematic diagram of the utility model semiconductor transistor encapsulating structure.
Wherein, Reference numeral
Embodiment
Below in conjunction with accompanying drawing, structural principle of the present invention and operation principle are described in detail:
Refer to Fig. 2, mainly include a lead frame or pedestal circuit board 30, be embedded with in this lead frame or pedestal circuit board 30 and link weld pad 301, can establish for the second end 5022 weldering of metal tie line 50 and carry out electrically connect, the telecommunications of chip 10 can be conducted on lead frame or pedestal circuit board 30 to impel;
Above lead frame or pedestal circuit board 30, be coated with sticker 20, this sticker 20 is put chip 10, utilizes the program of baking cooling and shaping, chip 10 can be made to be fixedly arranged on lead frame or pedestal circuit board 30;
One chip 10, upper surface is provided with chip pad 101, this chip pad 101 directly can be welded for the first end 5021 of metal tie line 50 and be established link, also after can being formed with gold stud bump 40 in advance, again the weldering of the first end 5021 of metal tie line 50 is located on gold stud bump 40, to reach better electrically connect;
One metal tie line 50, include internal layer portion 501 and outer portion 502, the main component in this internal layer portion 501 is copper, copper is a kind of metal with high oxidation speciality, once produce oxidation, effect of its electrically connect will with successively decrease, and in order to the metal tie line 50 effectively improving copper material be easy to be oxidized metallic character, the first end 5021 of metal tie line 50 and the second end 5022 to be welded respectively in the chip pad 101 being located at chip 10 or on the link weld pad 301 of gold stud bump 40 and lead frame or pedestal circuit board 30 before, the leading technology utilizing plating, the exterior layer 502 of oxidation can not be produced at periphery, the internal layer portion 501 of this metal tie line 50 plating one deck, the material of this exterior layer 502 can be gold, silver or palladium etc. not easily produce oxidation and the strong metal material of electrically connect,
Therefore, first the metal outer layer 502 first not easily producing oxidation at the foreign-plated last layer of interior layer 501 of metal tie line 50 is wanted, then utilize sticker 20 that chip 10 is fixedly arranged on the top of lead frame or pedestal circuit board 30, and then gold stud bump 40 is formed in the chip pad 101 of chip 10, finally utilize the welding manner of ultrasonic vibrating, first first end 5021 weldering carrying out the metal tie line 50 that two-layer plating completes is located on metal salient point 40, then drawing blocks after metal tie line 50 to preseting length, and the second end 5022 weldering of truncation surface i.e. metal tie line 50 is located on the link weld pad 301 of lead frame or pedestal circuit board 30, so just can complete the electrically connect of chip 10 and lead frame or pedestal circuit board 30, so just complete the technique of chipset, finally again this chipset is encapsulated,
In sum, the semiconductor transistor encapsulating structure that the utility model is done, compared with the process structure of the semiconductor transistor of prior art, the utility model can not only effectively improve metal tie line 50 oxidizable and cause telecommunications contact not good disappearance outside, more because copper and gold are belong to the two kinds of metallicses also do not engaged on welding, therefore be that to belong to zygosity preferably golden at the material of the exterior layer 502 of metal tie line 50, silver, when palladium, also be easier to make metal tie line 50 save the larger time in the process doing ultrasonic waves welding, also the situation engaging not good disconnected news is avoided to occur, therefore the process yields of chip module can be improved, reduce the process time and improve the amount of producing, it has novelty really, progressive and industry applications are undoubtedly.
Certainly; the utility model also can have other various embodiments; when not deviating from the utility model spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and distortion according to the utility model, but these change accordingly and are out of shape the protection range that all should belong to the claim appended by the utility model.
Claims (5)
1. a semiconductor transistor encapsulating structure, is characterized in that, comprising:
One lead frame or pedestal circuit board, the second end weldering be embedded with in this lead frame or pedestal circuit board for metal tie line is established and carries out the link weld pad of electrically connect;
One chip utilizing sticker to be fixedly installed, is placed in lead frame or pedestal circuit board, and the upper surface of this chip first end be provided with for metal tie line directly welds to establish and links with the chip pad forming electrically connect;
One for reaching the metal tie line of electrically connect, and include internal layer portion and outer portion, the chip pad of first end and chip is connected, and the second end and lead frame or pedestal circuit board are connected.
2. semiconductor transistor encapsulating structure as claimed in claim 1, is characterized in that, the first end this chip pad is formed in advance for this metal tie line welds the gold stud bump establishing link.
3. semiconductor transistor encapsulating structure as claimed in claim 1, it is characterized in that, the material of the interior layer of this metal tie line is copper.
4. semiconductor transistor encapsulating structure as claimed in claim 1, it is characterized in that, the material of the exterior layer of this metal tie line is gold, silver or palladium.
5. semiconductor transistor encapsulating structure as claimed in claim 1, it is characterized in that, the exterior layer of this metal tie line is the periphery that electroplating is placed on this interior layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361806385P | 2013-03-28 | 2013-03-28 | |
| TW103205584 | 2014-03-28 | ||
| TW103205584U TWM508118U (en) | 2013-03-28 | 2014-03-28 | Improved semiconductor transistor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204834628U true CN204834628U (en) | 2015-12-02 |
Family
ID=54700091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520186070.0U Active CN204834628U (en) | 2013-03-28 | 2015-03-30 | Semiconductor transistor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204834628U (en) |
-
2015
- 2015-03-30 CN CN201520186070.0U patent/CN204834628U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |