CN204810668U - 印制线路板 - Google Patents
印制线路板 Download PDFInfo
- Publication number
- CN204810668U CN204810668U CN201490000034.4U CN201490000034U CN204810668U CN 204810668 U CN204810668 U CN 204810668U CN 201490000034 U CN201490000034 U CN 201490000034U CN 204810668 U CN204810668 U CN 204810668U
- Authority
- CN
- China
- Prior art keywords
- layer circuit
- electrode
- electronic component
- layer
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
本申请公开了一种印制线路板,电子元件的第一电极通过导电层与外层线路电连接,第二电极直接与内层线路电连接,实现非引线或引脚键合的电路图形连接方式,从而避免了应力和电磁干扰噪声的影响,提高了印制线路板的性能。
Description
技术领域
本申请涉及电路领域,尤其涉及一种印制线路板。
背景技术
现有的电子元件埋入式印制线路板中,电子元件一般通过引线或者引脚与电路图形电连接,例如,常规的电源电子模块中,电源半导体芯片,包括MOSFET或IGBT芯片通常采用引线键合方式与基板上的电路图形连接。
由于引线或引脚连接通常具有较长的互连尺寸,会产生较大的应力和电磁干扰噪声,影响了印制线路板的性能。
发明内容
本申请旨在至少在一定程度上解决上述技术问题之一。
本申请提供一种印制线路板,包括由里向外依次设置的:第一绝缘层、内层线路、埋入层以及外层线路,所述埋入层上开设有贯穿该埋入层的通槽,该通槽的位于所述内层线路的底面设有用于定位电子元件的绝缘定位柱,该绝缘定位柱位于所述电子元件的两侧,且所述电子元件与所述通槽的侧壁之间填充有绝缘隔层以在电子元件的第一电极与第二电极之间绝缘,所述电子元件内置于所述通槽中且所述第一电极与所述内层线路电连接,所述第二电极通过导电层与所述外层线路电连接。
进一步地,所述外层线路与内层线路之间通过金属化盲孔电连接。
进一步地,所述第一绝缘层为绝缘芯板。
本申请的有益效果是:
通过提供一种印制线路板,电子元件的第一电极通过导电层与外层线路电连接,第二电极直接与内层线路电连接,实现非引线或引脚键合的电路图形连接方式,从而避免了应力和电磁干扰噪声的影响,提高了印制线路板的性能。
附图说明
图1为本申请实施例的印制线路板的剖视图。
具体实施方式
下面详细描述本申请的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,旨在用于解释本申请,而不能理解为对本申请的限制。
在本申请的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。
此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
在本申请中,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中,除非另有明确的规定和限定,第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触,也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且,第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度小于第二特征。
下面通过具体实施方式结合附图对本申请作进一步详细说明。
请参考图1,本实施例提供一种印制线路板,包括由里向外依次设置的:第一绝缘层1、内层线路2、埋入层3以及外层线路4。埋入层3上开设有贯穿该埋入层3的通槽31,该通槽31的位于内层线路2的底面设有用于定位电子元件5的绝缘定位柱32,该绝缘定位柱32位于电子元件5的两侧,且电子元件5与通槽31的侧壁之间填充有绝缘隔层33以在电子元件5的第一电极51与第二电极52之间绝缘。电子元件5内置于通槽31中且第一电极51与内层线路2电连接,第二电极52通过导电层33与外层线路4电连接。第一绝缘层1为绝缘芯板。
另外,当需要在外层线路与内层线路之间实现电连接时,外层线路与内层线路之间可通过金属化盲孔电连接。
这样,电子元件的第一电极通过导电层与外层线路电连接,第二电极直接与内层线路电连接,实现非引线或引脚键合的电路图形连接方式,从而避免了应力和电磁干扰噪声的影响,提高了印制线路板的性能。
在本说明书的描述中,参考术语“一个实施方式”、“一些实施方式”、“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中,对上述术语的示意性表述不一定指的是相同的实施例或示例。而且,描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明,不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说,在不脱离本申请构思的前提下,还可以做出若干简单推演或替换。
Claims (3)
1.一种印制线路板,包括由里向外依次设置的:第一绝缘层、内层线路、埋入层以及外层线路,其特征在于,所述埋入层上开设有贯穿该埋入层的通槽,该通槽的位于所述内层线路的底面设有用于定位电子元件的绝缘定位柱,该绝缘定位柱位于所述电子元件的两侧,且所述电子元件与所述通槽的侧壁之间填充有绝缘隔层以在电子元件的第一电极与第二电极之间绝缘,所述电子元件内置于所述通槽中且所述第一电极与所述内层线路电连接,所述第二电极通过导电层与所述外层线路电连接。
2.如权利要求1所述的印制线路板,其特征在于,所述外层线路与内层线路之间通过金属化盲孔电连接。
3.如权利要求1所述的印制线路板,其特征在于,所述第一绝缘层为绝缘芯板。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2014/074830 WO2015149365A1 (zh) | 2014-04-04 | 2014-04-04 | 印制线路板 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN204810668U true CN204810668U (zh) | 2015-11-25 |
Family
ID=54239331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201490000034.4U Expired - Fee Related CN204810668U (zh) | 2014-04-04 | 2014-04-04 | 印制线路板 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN204810668U (zh) |
WO (1) | WO2015149365A1 (zh) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004007006A (ja) * | 2003-09-16 | 2004-01-08 | Kyocera Corp | 多層配線基板 |
CN2785312Y (zh) * | 2004-12-13 | 2006-05-31 | 威盛电子股份有限公司 | 埋入式被动元件的组装结构 |
KR100704936B1 (ko) * | 2005-06-22 | 2007-04-09 | 삼성전기주식회사 | 전자부품 내장 인쇄회로기판 및 그 제작방법 |
KR100651563B1 (ko) * | 2005-07-07 | 2006-11-29 | 삼성전기주식회사 | 전자부품이 내장된 배선기판의 제조방법 |
-
2014
- 2014-04-04 CN CN201490000034.4U patent/CN204810668U/zh not_active Expired - Fee Related
- 2014-04-04 WO PCT/CN2014/074830 patent/WO2015149365A1/zh active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2015149365A1 (zh) | 2015-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI260056B (en) | Module structure having an embedded chip | |
CN106340493A (zh) | 功率电子模块 | |
US8824165B2 (en) | Electronic package structure | |
WO2008051596A3 (en) | Solid state light sheet and encapsulated bare die semiconductor circuits | |
KR101941711B1 (ko) | 전력 반도체 | |
EP3410476A1 (en) | Semiconductor module | |
US9924589B2 (en) | Circuit board | |
WO2018069476A1 (en) | Mounting assembly with a heatsink | |
JP6226068B2 (ja) | 半導体装置 | |
CN109587974A (zh) | 柔性电路板及该柔性电路板的制造方法 | |
CN104517952B (zh) | 功率半导体模块和用于制造功率半导体模块的方法 | |
US20100276188A1 (en) | Method and apparatus for improving power gain and loss for interconect configurations | |
CN106252332B (zh) | 热敏电阻搭载装置及热敏电阻部件 | |
US10070563B2 (en) | Electronic control unit | |
US9655238B2 (en) | Wiring board, method for manufacturing wiring board, and electronic device | |
CN204810668U (zh) | 印制线路板 | |
CN203446102U (zh) | 电路板及具有其的控制器 | |
EP2658355A2 (en) | Circuit board, electric device, and method of manufacturing circuit board | |
US8453917B1 (en) | Wave soldering of surface-mounting electronic devices on printed circuit board | |
WO2010129002A1 (en) | Method and apparatus for improving power and loss for interconect configurations | |
CN109817793B (zh) | Led模块 | |
JP5679579B2 (ja) | 配線基板 | |
US6989590B2 (en) | Power semiconductor device with a control circuit board that includes filled through holes | |
CN201893993U (zh) | 一种双面金属基线路板 | |
CN202818296U (zh) | 双面小蓝牙模块 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151125 Termination date: 20170404 |