CN204790972U - Super multithread broadband accurate control module based on FPGA - Google Patents

Abstract

The utility model relates to a super multithread broadband accurate control module based on FPGA, be equipped with a plurality of grades of buffer groups, the data output end of the data input end while of every buffer that subordinate's buffer was organized in the adjacent two -stage buffer group and a N buffer of higher level's buffer group is connected, higher level's buffer that different buffers are connected is different, buffer group of subordinate is a buffer only, the N that the number of buffer is the buffer number of its buffer group of adjacent subordinate respectively in all the other grade buffer groups doubly, N is for being more than or equal to 2 natural number, the buffer adopts FIFO, and a pulse source should be connected to the data input terminal pair of every buffer in higher level's buffer group. The utility model discloses can solve super multithread multiple -pulse and judge the delay problem that produces in the FPGA wiring, realize the accurate control in super multithread broadband again.

Description

Based on the accurate control module in super multithread broadband of FPGA

Technical field

The utility model relates to a kind of wire laying mode of accurate control realizing multithread, super multithread broadband in FPGA.

Background technology

In high speed test instrument as in 10,000,000,000 net testers, kilomega network test instrumentation, the broadband of multithread controls to be the key in logical design, and the precise degrees of bandwidth determines whole instrument function grade.And current multithread broadband controls often there is multiple-pulse and judges delay issue, have impact on the control accuracy of bandwidth.

Utility model content

In order to overcome the above-mentioned defect under prior art, the purpose of this utility model is to provide a kind of accurate control module in super multithread broadband based on FPGA, also be a kind of wire laying mode of accurate control of super multithread broadband simultaneously, super multithread multiple-pulse can be solved and judge delay issue, thus the accurate control in super multithread broadband can be realized.

The technical solution of the utility model is:

A kind of accurate control module in super multithread broadband based on FPGA, be provided with some grades of buffer groups, the data input pin of each buffer of adjacent two-level cache Qi Zuzhong subordinate buffer group is connected with the data output end of N number of buffer of higher level's buffer group simultaneously, higher level's buffer that different buffer connects is different, most subordinate buffer group only has a buffer, in all the other grade of buffer group, the number of buffer is respectively the N of the buffer number of its adjacent subordinate buffer group doubly, N be more than or equal to 2 natural number.

N is preferably greater than or equal to 4.

More preferably, the progression of buffer group is 5, and most subordinate buffer group has a buffer, and in all the other grade of buffer group, the number of buffer is respectively 4 times of the buffer number of its adjacent subordinate buffer group, and the buffer number of most higher level's buffer group is 256.

Described buffer preferably adopts FIFO.

In most higher level's buffer group, the data input pin correspondence of each buffer connects an impulse source, namely with super multithread one_to_one corresponding.

Described impulse source can be time controller.

Described some grades of buffer groups are all integrated on one piece of circuit board, and described circuit board is provided with mounting hole, and the neighboring area in the aperture of described mounting hole on circuit board two sides is each is fixedly coated with an insulating resilient layer.

Described insulating resilient layer can be rubber layer.

The beneficial effect of utility model is:

Employing multi-level buffer, subordinate's buffer memory control the wire laying mode of the multiple buffer memory of higher level simultaneously, solve the delay issue that super multithread multiple-pulse judges to produce in FPGA wiring well, complete again the accurate control in super multithread broadband.

Owing to arranging elastic layer around the mounting hole of the circuit board upper and lower surface at described some grades of buffer group places, when being screwed circuit board, Elastic Contact between screw and circuit board and between circuit board and circuit board installed surface, cushioning effect can be played preferably, combinational circuit of the present utility model can be made thus to adapt to more application scenarios.

Accompanying drawing explanation

Fig. 1 is structure principle chart of the present utility model;

Fig. 2 is fifo module of the present utility model citing.

Embodiment

The utility model provides a kind of accurate control module in super multithread broadband based on FPGA, is described below for 256 streams.See Fig. 1, the source of generation of bandwidth is the time controller of 256 streams, and 256 time controllers produce 256 streams and send pulse, and the speed of these 256 transmission pulses is less than or equal to the total bandwidth of 100%.

256 send pulse and illustrate see Fig. 2 with 256 FIFO(pins respectively) store, the buffer group that these 256 FIFO are formed is as first order buffer module.FIFO is adjusted to First-WordFall-Through pattern (namely dout line showing the pattern of data), as long as have pulse data in FIFO, empty signal will be dragged down, and judges for next stage buffer mode state machine.

Second level buffer module is the transmission pulse that 64 FIFO, each FIFO are responsible for 4 FIFO storing upper level, and each FIFO at the corresponding levels is by independently state machine control.The operation of state machine is, each cycle checks the empty state of these 4 FIFO successively, if dragged down, then the transmission pulse of this FIFO is deposited in FIFO at the corresponding levels;

Third level buffer module is 16 FIFO, and operating process is consistent with the second level;

Fourth stage buffer module is 4 FIFO, and operating process and the second level, the third level are consistent.

Level V buffer module namely most next stage buffer group is 1 FIFO, when all transmission pulses are all stored into after in this FIFO, test instrumentation design below then can take out the transmission pulse signal in this FIFO easily, according to accurate bandwidth instruction group bag, gives out a contract for a project.

Design resource of the present utility model mainly uses logical resource and the storage resources RAM of FPGA, therefore realizes mainly on FPGA or on AISIC chip.

Described some grades of buffer groups are all integrated on one piece of circuit board, and described circuit board is provided with mounting hole, and the neighboring area in the aperture of described mounting hole on circuit board two sides is each is fixedly coated with an insulating resilient layer.Described insulating resilient layer can be rubber layer.Utilize this insulating resilient layer can play certain cushioning effect.

The end face of described circuit board and/or bottom surface preferably arrange heat conduction copper sheet, described heat conduction copper sheet can be positioned at the periphery of high power consuming devices, and bond on circuit boards by silicone adhesive, these devices are connected to by copper cash or heat through-hole etc., form thermal dissipating path, improve thermal behavior, thus improve the reliability of its place equipment.

Claims (9)

1. the accurate control module in super multithread broadband based on FPGA, it is characterized in that being provided with some grades of buffer groups, the data input pin of each buffer of adjacent two-level cache Qi Zuzhong subordinate buffer group is connected with the data output end of N number of buffer of higher level's buffer group simultaneously, higher level's buffer that different buffer connects is different, most subordinate buffer group only has a buffer, in all the other grade of buffer group, the number of buffer is respectively the N of the buffer number of its adjacent subordinate buffer group doubly, N be more than or equal to 2 natural number.

2., as claimed in claim 1 based on the accurate control module in super multithread broadband of FPGA, it is characterized in that N >=4.

3. as claimed in claim 2 based on the accurate control module in super multithread broadband of FPGA, it is characterized in that the progression of buffer group is 5, most subordinate buffer group has a buffer, in all the other grade of buffer group, the number of buffer is respectively 4 times of the buffer number of its adjacent subordinate buffer group, and the buffer number of most higher level's buffer group is 256.

4. the accurate control module in super multithread broadband based on FPGA as described in claim 1,2 or 3, is characterized in that described buffer is FIFO.

5., as claimed in claim 4 based on the accurate control module in super multithread broadband of FPGA, it is characterized in that the data input pin correspondence of each buffer in most higher level's buffer group connects an impulse source.

6., as claimed in claim 5 based on the accurate control module in super multithread broadband of FPGA, it is characterized in that described impulse source is time controller.

7. as claimed in claim 6 based on the accurate control module in super multithread broadband of FPGA, it is characterized in that described some grades of buffer groups are all integrated on one piece of circuit board, described circuit board is provided with mounting hole, and the neighboring area in the aperture of described mounting hole on circuit board two sides is each is fixedly coated with an insulating resilient layer.

8., as claimed in claim 7 based on the accurate control module in super multithread broadband of FPGA, it is characterized in that described insulating resilient layer is rubber layer.

9. as claimed in claim 8 based on the accurate control module in super multithread broadband of FPGA, it is characterized in that end face and/or the bottom surface of described circuit board arrange heat conduction copper sheet, described heat conduction copper sheet bonds on circuit boards by silicone adhesive, is connected to high power consuming devices by copper cash or heat through-hole.