CN203490334U - Device for open-circuit or short-circuit test of chip - Google Patents
Device for open-circuit or short-circuit test of chip Download PDFInfo
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- CN203490334U CN203490334U CN201320531712.7U CN201320531712U CN203490334U CN 203490334 U CN203490334 U CN 203490334U CN 201320531712 U CN201320531712 U CN 201320531712U CN 203490334 U CN203490334 U CN 203490334U
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Abstract
The utility model relates to the field of semiconductor test, and provides a device for open-circuit or short-circuit test of a chip. The device is characterized by comprising a plurality of shift registers which are connected with a high-voltage circuit and a protection circuit; and a resistor which is connected with a low-voltage circuit and the chip, wherein the chip is connected with the protection circuit. The plurality of shift registers can be connected either in parallel or in series. According to the utility model, the quantity of digital channels of the device is increased, so that the problems of inefficiency of the digital channels and limitation on the machine are effectively solved, and the device has the advantages of low test cost, high test efficiency, high precision and simple operation.
Description
Technical field
The utility model semiconductor test field, particularly a kind of test chip is opened the device of short circuit.
Background technology
Along with electronic communication technology develop rapidly, and the quickening of chip renewal speed, at present a lot of signaling control protocol products are all saved the storaging chip of synchronous DRAM and master chip stack encapsulation packaging cost and solve speed issue.Because the network of master chip and storaging chip is not what combine, so just relate to the problem of direct-connected line between master chip and storaging chip.Storaging chip pin is many, if all from substrate cabling, then signal is extracted by ball piece, so whatever the chip of packing forms, just need to increase pin, thereby increases cost.Once pin increases, the size of encapsulation also can increase, and further increases cost, expands inferior position.
The method that solves at present open-short circuit is mainly divided into: each pin parameter measurement unit module (PPMU) method of testing, Z function walking (Function Walking Z) method of testing.PPMU method of testing is to utilize test chip to open the performance of short-circuiting means board itself, by pin parameter measurement unit (PMU), measures.The restriction of opening this body structure of short-circuiting means board due to test chip, the corresponding board passage of each chip pin, needs board to configure corresponding port number, and for chip, also need whole pins all to encapsulate, cause the cost of board and chip greatly to improve; The restriction that Function Walking Z method of testing has effectively solved tester table, for cost-saving, some board configurations PMU unit, rather than PPMU unit, therefore take 64 or 128 channel serial tests, increased like this test duration, and then reduced testing efficiency.
Therefore, semiconductor test field is badly in need of a kind ofly can extend testing chip opening short circuit digital channel, reduces testing cost, is improved testing efficiency, precision test chip high, simple to operate is opened the device of short circuit.
Utility model content
The utility model provides a kind of test chip to open the device of short circuit, and technical scheme is as follows:
Test chip is opened a device for short circuit, it is characterized in that, comprising:
A plurality of shift registers, are connected with high-voltage circuit, holding circuit;
Resistance, is connected with low-voltage lines, chip;
This chip is connected with this holding circuit.
As above a kind of test chip is opened the device of short circuit, wherein, adopts connected mode in parallel between a plurality of shift registers.
As above a kind of test chip is opened the device of short circuit, wherein, adopts the connected mode of series connection between a plurality of shift registers.
The beneficial effects of the utility model are:
1. a shift register can be extended to an input pin 8 or 16 output pins.
2. by shift register, expand measurable pin number amount, reduce work times, thereby reduce testing cost.
3. without adopting 64 or 128 channel serial tests, save the test duration, improve testing efficiency.
4. precision is high, simple to operate, has applicability more widely.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, describe the utility model in detail:
Fig. 1 is the structural representation that a kind of test chip of the utility model is opened the device of short circuit.
Embodiment
For measure, creation characteristic that the utility model technology is realized, reach object and effect is easy to understand, below in conjunction with concrete diagram, further set forth the utility model.
Fig. 1 is the structural representation that a kind of test chip of the utility model is opened the device of short circuit.A kind of test chip of the present utility model is driven short-circuiting means and is comprised: shift register 102,103,104, is connected with high-voltage circuit 101, holding circuit 105 respectively; Resistance 106, is connected with low-voltage lines 107, chip 108; Chip 108, is connected with holding circuit 105.
Between shift register 102,103,104, both can adopt connected mode in parallel, also can adopt the connected mode of series connection.
In the present embodiment, contain 3 shift registers, in testing process, according to the needs of chip 108, can use 1 or 2 above shift registers.
During the utility model work, first, low-voltage lines 107 is given the electric signal of 108 1 built-in being input as of chip " 0 " by resistance 106, then, high-tension line 101 offers shift register 102 high-voltage signals by 1 input pin, high-voltage signal is by holding circuit 105, by 8 or 16 output pins, high-voltage signal is passed to chip 108, chip 108 is detected, if output electrical signals is all " 1 ", again high-tension line 101 is offered to shift register 103 successively by input pin, 104 high-voltage signals, high-voltage signal is by holding circuit 105, by output pin, high-voltage signal is passed to chip 108, chip 108 is detected, if output electrical signals is all " 1 ", it is path, if there is one to be open circuit or short circuit for " 0 " in output electrical signals, as fruit chip 108 detects as short-circuit condition, can give 105 1 very high voltage electric signal of holding circuit in the other direction, the single direction transmission principle by holding circuit 105, can not cause the damage of shift register 102,103,104 simultaneously.As can be seen here, the utility model can be extended to an input pin 8 or 16 output pins with a shift register, has reduced test and has opened the work times of short circuit, thereby reduced testing cost.
More than show and described ultimate principle of the present utility model, principal character and advantage of the present utility model.The technician of the industry should understand; the utility model is not restricted to the described embodiments; that in above-described embodiment and instructions, describes just illustrates principle of the present utility model; under the prerequisite that does not depart from the utility model spirit and scope, the utility model also has various changes and modifications, and these changes and improvements all fall within the scope of claimed the utility model.The claimed scope of the utility model is defined by appending claims and equivalent thereof.
Claims (3)
1. test chip is opened a device for short circuit, it is characterized in that, comprising:
A plurality of shift registers, are connected with high-voltage circuit, holding circuit;
Resistance, is connected with low-voltage lines, chip;
This chip is connected with this holding circuit.
2. a kind of test chip according to claim 1 is opened the device of short circuit, it is characterized in that, adopts connected mode in parallel between the plurality of shift register.
3. a kind of test chip according to claim 1 is opened the device of short circuit, it is characterized in that, adopts the connected mode of series connection between the plurality of shift register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320531712.7U CN203490334U (en) | 2013-08-28 | 2013-08-28 | Device for open-circuit or short-circuit test of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320531712.7U CN203490334U (en) | 2013-08-28 | 2013-08-28 | Device for open-circuit or short-circuit test of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203490334U true CN203490334U (en) | 2014-03-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320531712.7U Expired - Fee Related CN203490334U (en) | 2013-08-28 | 2013-08-28 | Device for open-circuit or short-circuit test of chip |
Country Status (1)
| Country | Link |
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| CN (1) | CN203490334U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108226751A (en) * | 2017-12-14 | 2018-06-29 | 芯海科技（深圳）股份有限公司 | A kind of multiprocessor collaboration chip performance assessment system and method |
| CN109490748A (en) * | 2018-09-13 | 2019-03-19 | 深圳市卓精微智能机器人设备有限公司 | A kind of OS test macro |
| CN110954804A (en) * | 2019-12-19 | 2020-04-03 | 上海御渡半导体科技有限公司 | Device and method for accurately diagnosing cBit array faults in batch |
-
2013
- 2013-08-28 CN CN201320531712.7U patent/CN203490334U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108226751A (en) * | 2017-12-14 | 2018-06-29 | 芯海科技（深圳）股份有限公司 | A kind of multiprocessor collaboration chip performance assessment system and method |
| CN109490748A (en) * | 2018-09-13 | 2019-03-19 | 深圳市卓精微智能机器人设备有限公司 | A kind of OS test macro |
| CN110954804A (en) * | 2019-12-19 | 2020-04-03 | 上海御渡半导体科技有限公司 | Device and method for accurately diagnosing cBit array faults in batch |
| WO2021120806A1 (en) * | 2019-12-19 | 2021-06-24 | 上海御渡半导体科技有限公司 | Apparatus and method for accurately diagnosing cbit array fault in batches |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140319 Termination date: 20170828 |
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| CF01 | Termination of patent right due to non-payment of annual fee |