CN204497273U - A kind of entry chip package - Google Patents
A kind of entry chip package Download PDFInfo
- Publication number
- CN204497273U CN204497273U CN201520122405.2U CN201520122405U CN204497273U CN 204497273 U CN204497273 U CN 204497273U CN 201520122405 U CN201520122405 U CN 201520122405U CN 204497273 U CN204497273 U CN 204497273U
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- Prior art keywords
- chip
- support plate
- package
- mpw
- utility
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- 239000000463 material Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 20
- 238000005538 encapsulation Methods 0.000 abstract description 15
- 241000218202 Coptis Species 0.000 description 14
- 235000002991 Coptis groenlandica Nutrition 0.000 description 14
- 238000004806 packaging method and process Methods 0.000 description 10
- 239000003292 glue Substances 0.000 description 8
- 238000012856 packing Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 7
- 238000011056 performance test Methods 0.000 description 6
- 238000012795 verification Methods 0.000 description 6
- 238000003466 welding Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000012019 product validation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000035807 sensation Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Abstract
The utility model discloses a kind of entry chip package, comprise the support plate for chip attachment, the two ends of described support plate are also provided with multiple electric external terminal, and support plate surrounding is provided with package wall, package wall and support plate surround cavity, and chip is connected with electric external terminal by bonding wire.The utility model is by preformed encapsulating process, not exclusively encapsulate on support plate before paster, therefore time of complete encapsulating mould and fund input after the paster in traditional handicraft can be avoided, reduce costs, shorten the launch products time, meet MPW MPW product requirement encapsulation simple needs flexibly.
Description
Technical field
The utility model relates to a kind of entry chip package CAHP (Chips Adaptable Housing Package).
Background technology
Along with the requirement of electronic product to Time To Market is more and more higher, how to carry out chip electrical connection, simplified package, chip protection, realize product electric performance test fast, more and more become the problem that product design company is concerned about.
For reducing product research and development in early stage, checking cost, the form of product many employings MPW MPW is processed, and carries out electric performance test after encapsulation.Generally speaking, the most frequently used verification method adopts traditional chip packaging method and technological process, by chip attachment on support plate, after using the modes such as gold thread welding to realize chip and support plate electric interconnection, carries out chip electric performance test by external terminal.In known chip encapsulation technology, common encapsulating structure as shown in Figure 1A, specialized designs processing mates support plate with chip, and chip and this support plate are welded by gold thread or upside-down mounting mounts and realizes being electrically connected, then carries out encapsulating and complete chip package.It mainly comprises a support plate 5; the chip 3 that this support plate mounts; a plurality of bonding wire 2 for the connection of chip and support plate circuit, and arranges the connection of a plurality of external terminal 1 for support plate circuit and external circuit on support plate, and whole chip carries out encapsulating protection by encapsulated member 4a.
In said structure, chip realizes realizing being electrically connected, for being externally connected to an external printed circuit board with the external terminal 1 on support plate with metal wire solder technology (Wire Bonding).This packaging structure separately comprises an adhesive body, with encapsulating chip and gold thread.This kind of project organization is excellent, becomes the chip-packaging structure that use is comparatively general.But in this kind of structure, on the one hand, need to carry out independent support plate design for different chip, namely for the chip of different size, support plate versatility is poor; On the other hand, due to the demand of chip package, as used encapsulating material to encapsulate chip in Figure 1A, the encapsulating mold that the chip due to different-thickness uses is different, and the fund of mould and time drop into general larger.
Product checking in the early stage mode of MPW MPW that adopts carries out Product processing more, because MPW product category is changeable, quantity is few, different product chip size is different, and welding demand is different, encapsulation need carry out support plate design, mould customized development, and time and cost drop into larger.As can be seen here, above-mentioned known chip packaging method and package body structure can not meet that Product Validation work-in-process quantity is few, kind is many, the requirement that seeking time is short, flexibility ratio is high.
For improving its versatility further, reducing costs input, completing checking fast, shorten product introduction market hours, make following entry chip-packaging structure and method.
Utility model content
For solving the deficiency that prior art exists, the utility model discloses a kind of entry chip package, the feature that the application is many for MPW product category, quantity is few, time cost is high, cavity is surrounded by package wall in advance on encapsulating carrier plate, paster, bonding wire in cavity, under the prerequisite without the need to carrying out the design of independent support plate and mould input, realize the testing authentication of chip fast packing.
For achieving the above object, concrete scheme of the present utility model is as follows:
A kind of entry chip package, comprise the support plate for chip attachment, the two ends of described support plate are also provided with multiple electric external terminal, and support plate surrounding is provided with package wall, package wall and support plate surround cavity, and chip is connected with electric external terminal by bonding wire.
Described support plate is metal framework, organic printed circuit board or ceramic substrate.
Be provided with lid above the cavity that described package wall is formed on support plate, package wall material is epoxy resin.
A kind of entry chip packaging method, comprises the following steps:
Step one: carried out sidewall encapsulation before the encapsulation of support plate paster, support plate obtains the cavity of surrounding sidewall middle flat;
Step 2: carry out chip attachment in cavity, is welded on gold thread on chip, drips glue and protects, make chip and gold thread and extraneous physical isolation, connect extraneous printed circuit board carry out electric performance test by external terminal after adding chip in sidewall.
Described step one cavity is provided with lid.
Described lid is crown cap, has cover, filter or polarisation functional cover.
Described chip is radio frequency products chip, chip of micro-electro-mechanical system, sensor class chip or filter.
In cavity, carry out chip attachment in described step 2, chip attachment is single-chip attachment or multi-chip attachment; Multi-chip attachment mounts or stacking attachment side by side for chip.
Described method is verified for the encapsulation of supporting MPW-MPW product.
After carrying out chip attachment in described step 2 in cavity, this chip also realizes electrical connection by flip-chip FC.
Chip fast packing verification method, before pasting chip, forms package wall structure in support plate surrounding.Support plate is not by the restriction of material, and organic material printed wiring board, metal framework support plate, ceramic substrate are all in this case protection range.
This chip fast packing verification method is not by the impact of packaged chip product category, and each chips such as radio frequency products chip, chip of micro-electro-mechanical system, sensor class chip, filter all can use this method to realize fast packing checking, all at this case protection range.
On this encapsulating carrier plate after pasting chip, not by the restriction of chips welding form, this packaged chip welds by gold thread, also can realize electrical connection by upside-down mounting FC; Can be single-chip attachment, also can be multi-chip attachment; Multi-chip attachment can be that chip mounts side by side, stacking attachment.Above implementation, all at this case protection range.
Can supply chip testing after chip attachment, the restriction of this scheme not tested person method, can be test after the complete component mounter of encapsulation, or press-fit in testing base and test, or the exposed pin that directly carries out of chip is surveyed all at this case protection range.
Surrounding package wall is added lid not by the restriction of material, can be crown cap, have cover, filter, polarisation functional cover, all protect by this case.
The method is not by the change of chip package kind, and ball grid array BGA package, the encapsulation of all employing this programme forms such as quad flat non-pin QFN encapsulation is all protected by this case.
The utility model is particularly suitable for product engineering phase authentication, is especially applicable to the encapsulation checking of supporting MPW-MPW product.
The application is without the need to carrying out the customization of specific products support plate, mould customization, but on support plate, paster, welding gold thread, simple dripping after glue is protected can carry out electric performance test.
The beneficial effects of the utility model:
The utility model is by preformed encapsulating process, not exclusively encapsulate on support plate before paster, therefore time of complete encapsulating mould and fund input after the paster in traditional handicraft can be avoided, reduce costs, shorten the launch products time, meet MPW MPW product requirement encapsulation simple needs flexibly.
Accompanying drawing explanation
Figure 1A is existing conventional chip-packaging structure.
Figure 1B is according to a kind of entry chip package CAHP structural representation of the present utility model.
In figure, 1, external terminal, 2, gold thread, 3, chip, 4, sidewall, 4a, encapsulated member, 5, support plate, 6, drip glue.
Embodiment:
Below in conjunction with accompanying drawing, the utility model is described in detail:
As shown in Figure 1B, package wall is made in advance on support plate, surrounding sidewall forms cavity on support plate, in cavity after paster, welding gold thread, for testing adding lid on cavity after, avoiding the mould carrying out encapsulating for different product support plate and dropping into, shortening product and put goods on the market the time, reduce product packaging cost, realize the fast verification of product low cost.
For setting forth the utility model further for the technological means reaching predetermined utility model object and take and effect, below in conjunction with accompanying drawing preferred embodiment, to according to a kind of entry chip package CAHP of the present utility model and embodiment, structure, feature and effect thereof, be described in detail as follows.
According to a preferred embodiment of the present utility model, disclose a kind of entry chip package CAHP verification method, Figure 1B uses encapsulating structure profile in this verification method.
First refer to shown in accompanying drawing 1B, this CAHP entry chip package, it is illustrated as the better enforcement structure of CAHP entry chip package of the present utility model, is described by the encapsulating structure of accompanying drawing.This encapsulating structure comprises support plate 5, chip 3, multiple external terminal 1, and this external terminal is for being externally bonded to external printed circuit board.
Support plate 5 meets the universal of encapsulating carrier plate, the one side attachment of carrying out chip 3 with electrically weld.For improving packaging efficiency further, shortening chip package and product put goods on the market the time, carried out sidewall 4 and encapsulated before the encapsulation of support plate paster.
What support plate obtained is the cavity of surrounding sidewall, middle flat.In cavity, carry out chip 3 mount, gold thread 2 welds, and drips after glue 6 carries out simple protective, makes chip and gold thread and extraneous physical isolation, connects extraneous printed circuit board carry out electric performance test by external terminal.
In said structure, by preformed encapsulating process, not exclusively encapsulate on support plate before paster, therefore time of complete encapsulating mould and fund input after the paster in traditional handicraft can be avoided, reduce costs, shorten the launch products time, meet MPW MPW product requirement encapsulation simple needs flexibly.
And this CAHP entry chip package uses flexibly, is not restricted because of the difference of carrier plate material, can be implemented on the metal used at present, all support plates such as organic, ceramic and realize; Not by the restriction of product packing forms, go for all encapsulating structures such as BGA BGA Package, LGA land grid array; By the restriction of electrical connection methods, can be gold thread binding, upside-down mounting attachment, single-chip attachment, all modes such as multi-chip stacking mounts, multi-chip mounts side by side; Not by the impact of product category, it can be the encapsulation checking of all product chips such as storage class, logic class, sensor class; Chip protected mode is flexible, can drip glue protection, also can add a cover protection after paster.
Therefore, the package wall that the present embodiment is formed before utilizing paster, drips glue 6 after adding paster, replaces encapsulated member 4a in Figure 1A, and then omit traditional encapsulating mold required time, fund input in sidewall, realizes the checking of entry chip fast packing flexibly.Many for MPW MPW product category, quantity is few, to Time To Market require high, need reduce the demand of packaging time and cost, this utility model method is particularly useful for each checking demand of MPW product, realize MPW chip fast packing verify.
According to the utility model, as can be seen from said structure, support plate leaves the terminal for chip electrical connection, or realize chip by gold thread welding and be connected with the electric attribute of support plate, or realize chip by flip-chip and support plate is electrically connected.According to the demand of chip terminal complexity and reliability, support plate can the different materials such as choice for use metal framework, organic printed circuit board, pottery.According to the difference of product test protection demand; after chip attachment, electrical connection; seal by dripping glue, the mode such as to seal carries out chip, gold thread is protected; in addition; according to product demand; glass, metal, organic material lid can be selected, as light sensation chip adopts filtering functions lid, pressure sensor to adopt specific materials glue to encapsulate.Do not limit by encapsulating structure, bonding pattern, air-proof condition, the condition of adding a cover kind, use flexibly, be particularly useful for MPW MPW product, realize fast packing checking.
By reference to the accompanying drawings embodiment of the present utility model is described although above-mentioned; but the restriction not to the utility model protection range; one of ordinary skill in the art should be understood that; on the basis of the technical solution of the utility model, those skilled in the art do not need to pay various amendment or distortion that creative work can make still within protection range of the present utility model.
Claims (3)
1. an entry chip package, is characterized in that, comprises the support plate for chip attachment, the two ends of described support plate are also provided with multiple electric external terminal, support plate surrounding is provided with package wall, and package wall and support plate surround cavity, and chip is connected with electric external terminal by bonding wire.
2. a kind of entry chip package as claimed in claim 1, is characterized in that, described support plate is metal framework, organic printed circuit board or ceramic substrate.
3. a kind of entry chip package as claimed in claim 1, is characterized in that, is provided with lid above the cavity that described package wall is formed on support plate, and package wall material is epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520122405.2U CN204497273U (en) | 2015-03-02 | 2015-03-02 | A kind of entry chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520122405.2U CN204497273U (en) | 2015-03-02 | 2015-03-02 | A kind of entry chip package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204497273U true CN204497273U (en) | 2015-07-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520122405.2U Expired - Fee Related CN204497273U (en) | 2015-03-02 | 2015-03-02 | A kind of entry chip package |
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| Country | Link |
|---|---|
| CN (1) | CN204497273U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733451A (en) * | 2015-03-02 | 2015-06-24 | 山东盛品电子技术有限公司 | Chips adaptable housing package and method |
-
2015
- 2015-03-02 CN CN201520122405.2U patent/CN204497273U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733451A (en) * | 2015-03-02 | 2015-06-24 | 山东盛品电子技术有限公司 | Chips adaptable housing package and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150722 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |