CN103400826B - Semiconductor packages and manufacture method thereof - Google Patents
Semiconductor packages and manufacture method thereof Download PDFInfo
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- CN103400826B CN103400826B CN201310249959.4A CN201310249959A CN103400826B CN 103400826 B CN103400826 B CN 103400826B CN 201310249959 A CN201310249959 A CN 201310249959A CN 103400826 B CN103400826 B CN 103400826B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Providing a kind of semiconductor packages, this semiconductor packages includes: substrate, including the separated from one another and grounding pattern of electric insulation and pad；Semiconductor chip, is arranged on substrate, and includes active surface and non-active relative with active surface；Projection, is arranged between active surface with pad to electrically connect active surface with pad；And conductive member, above and it is electrically connected to ground at least some of of pattern including being arranged on non-active.
Description
Technical field
The present invention relates to a kind of semiconductor packages and manufacture method thereof, more particularly, relate to one and have
The semiconductor packages of the electrical property that improve and manufacture method thereof.
Background technology
Common semiconductor packages includes that chip is just being loaded on the semiconductor packages on substrate and flip-chip in base
Semiconductor packages on plate.In chip is just being loaded on the semiconductor packages on substrate, the back side of chip is passed through
Adhesive layer is arranged in the wafer support portion of substrate, and the active surface of chip is electrically connected to substrate by bonding line
Surface on pad, pad is electrically connected to the external connection terminal of such as soldered ball by the lead-in wire within substrate
Son.In flip-chip semiconductor packages on substrate, the active surface of chip is electrically connected to by projection
Pad on the surface of substrate, the outside that pad is electrically connected to such as soldered ball by the lead-in wire within substrate connects
Connecting terminal.
Along with circuit and the increase of the complexity of package layout, the width of circuit pattern becomes more and more narrow,
Spacing between circuit pattern becomes more and more less, the problem therefore causing signal integrity.
Summary of the invention
The one or more exemplary embodiment of the present invention provides a kind of electrical property having and improve
Semiconductor packages and manufacture method thereof.
According to an aspect of the present invention, it is provided that a kind of semiconductor packages, this semiconductor packages includes: base
Plate, including the separated from one another and grounding pattern of electric insulation and pad；Semiconductor chip, is arranged on substrate
On, and include active surface and non-active relative with active surface；Projection, is arranged on active surface and pad
Between so that active surface is electrically connected with pad；And conductive member, upper and electric including being arranged on non-active
It is connected at least some of of grounding pattern.
Described semiconductor packages may also include the described connection structure electrically connected with grounding pattern at least partially
Part.
Connecting elements can include at least one in conductive paste and metal wire.
Conductive member may also include from described at least some of extension be directly electrically connected to grounding pattern to
Few another part.
Described can cover non-active at least partially more than 20% area.
Described can substantially completely cover non-active at least partially.
Conductive member can include at least one in conductive adhesive tape and metal forming.
Substrate can have and is provided with grounding pattern and the first surface of pad and relative with first surface
Second surface, substrate may also include another pad arranged on a second surface and is arranged on the interior of substrate
Portion also can wrap with the inner lead electrically connected with another pad described by described pad, described semiconductor packages
Include the external connection terminals being arranged on another pad described.
Described semiconductor packages may also include pad and grounding pattern and semiconductor chip, projection and leads
The plastic-sealed body of electric components encapsulating.
According to a further aspect in the invention, it is provided that a kind of method manufacturing semiconductor packages, the method bag
Include following step: providing intermediate products, intermediate products include substrate, semiconductor chip, projection and conduction
Component, substrate includes the separated from one another and grounding pattern of electric insulation and pad, and semiconductor chip is arranged on
On substrate and include active surface and non-active relative with active surface, projection is arranged on active surface and pad
Between so that active surface is electrically connected with pad, conductive member includes be arranged on non-active at least one
Point；And it is electrically connected to ground pattern at least partially by described.
The step providing intermediate products comprises the steps that will partly be led with the projection being arranged between active surface and pad
Body chip is arranged on substrate；Then, non-active is arranged described at least partially.
There is provided intermediate products step comprise the steps that arrange on non-active described at least partially；Then,
With the projection being arranged between active surface and pad, semiconductor chip is arranged on substrate.
The described step being electrically connected to ground pattern at least partially is comprised the steps that institute by connecting elements
State and be electrically connected to ground pattern at least partially.
Conductive member may also include at least another part from described at least some of extension, by described at least
A part is electrically connected to ground the step of pattern and comprises the steps that and be directly electrically connected to by described at least another part
Grounding pattern.
Described method may also include pad and grounding pattern and semiconductor chip, projection and conductive member
Encapsulating.
Substrate can have and is provided with grounding pattern and the first surface of pad and relative with first surface
Second surface, substrate may also include another pad arranged on a second surface and is arranged on the interior of substrate
Portion may additionally include institute with the inner lead electrically connected with another pad described by described pad, described method
State layout external connection terminals on another pad.
Accompanying drawing explanation
By description to embodiment below in conjunction with the accompanying drawings, above and/or other aspect of the present invention and advantage
Will be clear from and be easier to understand, in the accompanying drawings:
Fig. 1 is the schematic cross sectional views of semiconductor packages according to an exemplary embodiment of the present invention；
Fig. 2 is the showing before semiconductor package is contained in plastic packaging according to an exemplary embodiment of the present invention in Fig. 1
Meaning property plane graph；And
Fig. 3 to Fig. 6 is sequentially to illustrate to manufacture the most partly leading in Fig. 1
The schematic cross sectional views of the method for body encapsulation.
Detailed description of the invention
Hereinafter, with reference to the accompanying drawings to be more fully described the present invention, the present invention shown in the drawings
Exemplary embodiment.The present invention can implement in a number of different ways, and is not construed as
It is confined to embodiments set forth here.In the accompanying drawings, for clarity, the chi in layer and region can be exaggerated
Very little.
Fig. 1 is the schematic cross sectional views of semiconductor packages 100 according to an exemplary embodiment of the present invention, figure
2 is the signal before plastic packaging of the semiconductor packages according to an exemplary embodiment of the present invention 100 in Fig. 1
Property plane graph.With reference to Fig. 1, semiconductor packages 100 includes substrate according to an exemplary embodiment of the present invention
110, the semiconductor chip 120 that is arranged on substrate 110 and be arranged on substrate 110 and semiconductor chip
With the projection (bump) 130 that substrate 110 is electrically connected with semiconductor chip 120 between 120.Therefore,
Semiconductor packages 100 includes the semiconductor chip 120 being inverted on substrate 110.
Substrate 110 can be printed circuit board (PCB) (PCB).Substrate 110 has first surface (on such as,
Surface) 111 and relative with first surface 111 (or back to first surface 111) second surface (such as,
Lower surface) 112.Substrate 110 can include the first pad 113 being arranged on first surface 111, arrange
The second pad 114 on second surface 112 and be arranged on the inside of substrate 110 with by the first pad
113 inner leads 115 electrically connected with the second pad 114.
Substrate 110 also includes the grounding pattern 116 being arranged on first surface 111, grounding pattern 116
Separate and electric insulation with the first pad 113.In the exemplary embodiment, grounding pattern 116 has not
By semiconductor chip 120 cover at least some of.
Semiconductor chip 120 has active surface 121 and relative with active surface 121 (or back to active surface 121)
Non-active (such as, the back side) 122.Active surface 121 can in the face of substrate 110, more specifically,
First surface 111 in the face of substrate 110.Semiconductor chip 120 can include being arranged on active surface 121
Pad (not shown).Semiconductor chip 120 can include many sub-semiconductor chips sequentially stacked.
Projection 130 may be provided on the active surface 121(such as active surface 121 of semiconductor chip 120
Pad, not shown) with the first pad on the first surface 111(such as first surface 111 of substrate 110
113) between, so that substrate 110 is electrically connected with semiconductor chip 120.
Semiconductor packages 100 may also include and is arranged in the second pad according to an exemplary embodiment of the present invention
External connection terminals 150 on 114, is used for being connected to external devices so that semiconductor chip 120 can lead to
Cross projection the 130, first pad 113, inner lead the 115, second pad 114 and external connection terminals 150
It is electrically interconnected with external devices.External connection terminals 150 can be soldered ball.
Seeing figures.1.and.2, semiconductor packages 100 also includes leading according to an exemplary embodiment of the present invention
Electric components 140.Conductive member 140 has on the non-active face 122 being arranged on semiconductor chip 120
At least partially, and conductive member 140 is electrically connected to the grounding pattern 116 of substrate 110.Such as, conduction
Component 140 can be electrically connected to the grounding pattern 116 of substrate 110 by the connecting elements 170 of conduction.At this
In the case of Zhong, the grounding pattern 116 of conductive member 140, connecting elements 170 and substrate 110 constitutes ground connection
Path, thus the electrostatic grounding that can will produce on semiconductor chip 120.Therefore, semiconductor package is improved
Fill the signal integrity of 100, thus improve the electrical property of semiconductor packages 100.
Seeing figures.1.and.2, conductive member 140 is completely covered or substantially completely covers semiconductor chip
The non-active face 122 of 120 is to form large-area ground plane, so that ground signalling maximizes and notable
Improve the electrical property of semiconductor packages.But, the invention is not restricted to this.Conductive member can cover and (or account for
According to) the non-active face 122 of semiconductor chip 120 more than 20% area, preferably more than 40%
Area, the area of more preferably more than 60%, the most preferably area of more than 80%, thus formed big
The ground plane of area, to increase ground signalling and to improve the electrical property of semiconductor packages.In another exemplary
In embodiment, conductive member may also include and extends to cover semiconductor chip 120 from non-active face 122
A part for the side surface substantially vertical with non-active face 122.
Conductive member 140 can be with the conductive member being conductive adhesive tape, metal forming or other forms.Conduction
Adhesive tape can be the adhesive die attachment film (DAF, die attach film) of conduction.Using conductive adhesive tape
In the case of conductive member 140, conductive adhesive tape can be attached to the non-active of semiconductor chip 120
On face 122.In the case of using metal forming as conductive member 140, electroconductive binder may be provided at
So that metal forming is adhered to semiconductor chip between metal forming and the non-active face 122 of semiconductor chip 120
The non-active face 122 of 120.
Connecting elements 170 can be with the connecting elements of conduction being conductive paste, metal wire or other forms.?
In the case of using conductive paste as connecting elements 170, can be by injecting, spray, sending (dispense)
Easily apply connecting elements 170.
Although as in figure 2 it is shown, conductive member 140 is by being arranged on the substantially corner in non-active face 122
Four connecting elements 170 are electrically connected respectively to the four grounded pattern 116 of substrate 110, but connecting elements
170 and the quantity of grounding pattern 116 unrestricted, if conductive member 140, connecting elements 170 and connect
Ground pattern 116 constitutes suitable grounded circuit.
Although as depicted in figs. 1 and 2, conductive member 140 is electrically connected to substrate by connecting elements 170
The grounding pattern 116 of 110, but the invention is not restricted to this.In a further exemplary embodiment, conductive member
The grounding pattern 116 of substrate 110 can be extended to from the non-active face 122 of semiconductor chip 120, thus
It is electrically connected to the grounding pattern 116 of substrate 110.Specifically, conductive member can be from semiconductor chip 120
Non-active face 122 extend directly into the grounding pattern 116 of substrate 110, be thus electrically connected to substrate 110
Grounding pattern 116.It addition, conductive member can prolong from the non-active face 122 of semiconductor chip 120
Reach the side surface substantially vertical with non-active face 122 of semiconductor chip 120, and further extend into
The grounding pattern 116 of substrate 110, is thus electrically connected to the grounding pattern 116 of substrate 110.Therefore, may be used
To omit connecting elements 170.It is adapted to extend into grounding pattern 116 in which case it is possible to use have
The conductive adhesive tape of a part or metal forming as conductive member.
Semiconductor packages 100 may also include the first of substrate 110 according to an exemplary embodiment of the present invention
The first pad 113 on surface 111 and grounding pattern 116 and semiconductor chip 120, projection 130,
The plastic-sealed body 180 of conductive member 140, connecting elements 170 encapsulating.Plastic-sealed body 180 can be epoxy-plastic packaging
Body.
Hereinafter, manufacture will be described with reference to Fig. 3 to Fig. 6 the most partly to lead
The method of body encapsulation 100.Fig. 3 to Fig. 6 be sequentially illustrate manufacture in Fig. 1 according to example of the present invention
The schematic cross sectional views of the method for the semiconductor packages 100 of property embodiment.
With reference to Fig. 3, it is provided that the semiconductor chip 120 that include substrate 110, is arranged on substrate 110, set
Put between substrate 110 with semiconductor chip 120 so that substrate 110 is electrically connected with semiconductor chip 120
Projection 130 and the conductive member 140 that is arranged on the non-active face 122 of semiconductor chip 120
Intermediate products.
In one exemplary embodiment, can utilize convex by known method (such as, Reflow Soldering)
Semiconductor chip 120 is arranged on substrate 110 by block 130, then in the non-master of semiconductor chip 120
On dynamic face 122, conductive member 140 is set.In a further exemplary embodiment, can be at semiconductor chip 120
Non-active face 122 on conductive member 140 is set, then by known method (such as, Reflow Soldering)
Projection 130 is utilized to be arranged on substrate 110 by semiconductor chip 120.Conductive member 140 can be to lead
Electricity adhesive tape, metal forming or the conductive member of other forms.Conductive adhesive tape can be that the chip of conduction glues
Membrane (DAF).In the case of using conductive adhesive tape as conductive member 140, can be viscous by conduction
Crossed belt is attached on the non-active face 122 of semiconductor chip 120.Using metal forming as conductive member
In the case of 140, conduction can be set between metal forming and the non-active face 122 of semiconductor chip 120
Binding agent to adhere to the non-active face 122 of semiconductor chip 120 by metal forming.
As shown in Figure 3, conductive member 140 is completely covered or substantially completely covers semiconductor chip 120
Non-active face 122, but the invention is not restricted to this.Conductive member can cover (or occupying) semiconductor core
The area of more than the 20% of the non-active face 122 of sheet 120, the area of preferably more than 40%, more excellent
The area of selection of land more than 60%, the most preferably area of more than 80%.In a further exemplary embodiment,
Conductive member may also include extend from non-active face 122 to cover semiconductor chip 120 with non-active
A part for 122 substantially vertical side surfaces.
In the exemplary embodiment, conductive member 140 also can have be suitable at semiconductor chip 120 non-
The part extended outside the scope of active surface 122 such that it is able to be connected to the grounding pattern of substrate 110
116。
With reference to Fig. 4, conduction is set between the grounding pattern 116 of conductive member 140 and substrate 110
Connecting elements 170, to be electrically connected to the grounding pattern 116 of substrate 110 by conductive member 140.Conduction structure
The grounding pattern 116 of part 140, connecting elements 170 and substrate 110 constitutes grounded circuit, improves and partly leads
The signal integrity of body encapsulation 100, thus improve the electrical property of semiconductor packages 100.
Connecting elements 170 can be with the connecting elements of conduction being conductive paste, metal wire or other forms.?
In the case of using conductive paste as connecting elements 170, can be held by injection, injection or dispensing
Change places and apply connecting elements 170.
Although as shown in Figure 4, conductive member 140 being electrically connected to substrate 110 by connecting elements 170
Grounding pattern 116, but the invention is not restricted to this.Also have at conductive member and be suitable at semiconductor chip
It is extended so as to be connectable to the grounding pattern of substrate 110 outside the scope in the non-active face 122 of 120
In the case of the part of 116, a described part can be connected to the grounding pattern 116 of substrate 110.
Specifically, a described part can be directly connected to the grounding pattern 116 of substrate 110, or make described
A part extends on the side surface substantially vertical with non-active face 122 of semiconductor chip 120, then
It is connected to the grounding pattern 116 of substrate 110.Therefore, it can omit the step arranging connecting elements 170.
With reference to Fig. 5, formed and the first pad 113 on the first surface 111 of substrate 110 and ground connection are schemed
Case 116 and semiconductor chip 120, projection 130, conductive member 140, connecting elements 170 encapsulating
Plastic-sealed body 180.In the exemplary embodiment, can be by known method (such as, mould and solidify)
Plastic-sealed body 180 is formed by epoxy-plastic packaging material.
With reference to Fig. 6, the second pad 114 of substrate 110 is arranged for connection to the outside of external devices
Connect terminal 150 so that semiconductor chip 120 can be drawn by projection the 130, first pad 113, inside
Line the 115, second pad 114 and external connection terminals 150 are electrically interconnected with external devices.In exemplary enforcement
In example, can be by known method (such as, Reflow Soldering) solder ball placement as external connection terminals 150.
Thus, the manufacture of semiconductor packages 100 is completed.
Can perform what reference Fig. 6 described before the step forming plastic-sealed body 180 described with reference to Fig. 5
Arrange the step of external connection terminals 150.
Semiconductor packages includes being arranged on the non-active of semiconductor chip according to an exemplary embodiment of the present invention
On face and be electrically connected to ground the conductive member of pattern, thus form grounded circuit with grounding pattern, improve
The signal integrity of semiconductor packages, thus improve the electrical property of semiconductor packages.Additionally, conduction
Component can cover the area of more than the 20% of non-active of (or occupying) semiconductor chip, such as, cover
Or substantially completely cover non-active of semiconductor chip to form large-area ground plane, thus increase
Ground signalling also improves the electrical property of semiconductor packages.
Although the exemplary embodiment with reference to the present invention specifically illustrates and describes the present invention, but this area
It is to be understood by the skilled artisans that without departing from the spirit and scope of the present invention, can make in form
With the various changes in details.
Claims (7)
1. a semiconductor packages, described semiconductor packages includes:
Substrate, including the separated from one another and grounding pattern of electric insulation and pad；
Semiconductor chip, is arranged on substrate, and includes active surface and non-active relative with active surface；
Projection, is arranged between active surface with pad to electrically connect active surface with pad；
Conductive member, at least some of including be arranged on non-active；
Connecting elements, electrically connects described with grounding pattern at least partially, and includes conductive paste and metal
At least one in line；And
Plastic-sealed body, by pad and grounding pattern and semiconductor chip, projection and conductive member encapsulating and with
Pad and grounding pattern and semiconductor chip, projection and each in conductive member contact,
Wherein, conductive member includes at least one in conductive adhesive tape and metal forming,
Wherein, the area of more than the 20% of non-active of described at least some of covering.
Semiconductor packages the most according to claim 1, wherein, described the completeest
Non-active of all standing.
Semiconductor packages the most according to claim 1, wherein, substrate has and is provided with ground connection
Pattern and the first surface of pad and the second surface relative with first surface,
Substrate also includes another pad arranged on a second surface and is arranged on the inside of substrate with by institute
State the inner lead that pad electrically connects with another pad described,
Described semiconductor packages also includes the external connection terminals being arranged on another pad described.
4. the method manufacturing semiconductor packages, described method comprises the steps:
Thering is provided intermediate products, intermediate products include substrate, semiconductor chip, projection and conductive member, base
Plate includes the separated from one another and grounding pattern of electric insulation and pad, and semiconductor chip is arranged on substrate also
Including active surface and non-active relative with active surface, projection is arranged between active surface and pad with will
Active surface electrically connects with pad, and it is at least some of that conductive member includes being arranged on non-active, conduction
Component includes at least one in conductive adhesive tape and metal forming；And
Pattern it is electrically connected to ground at least partially by described by connecting elements,
By plastic-sealed body, pad and grounding pattern and semiconductor chip, projection and conductive member are encapsulated also
And plastic-sealed body contacts with each in pad and grounding pattern and semiconductor chip, projection and conductive member,
Wherein, connecting elements includes at least one in conductive paste and metal wire,
Wherein, the area of more than the 20% of non-active of described at least some of covering.
The method of manufacture semiconductor packages the most according to claim 4, wherein, it is provided that intermediate products
Step include: with the projection being arranged between active surface and pad, semiconductor chip is arranged on substrate；
Then, non-active is arranged described at least partially.
The method of manufacture semiconductor packages the most according to claim 4, wherein, it is provided that intermediate products
Step include: arrange on non-active described at least partially；Then, be arranged on active surface with
Semiconductor chip is arranged on substrate by the projection between pad.
The method of manufacture semiconductor packages the most according to claim 4, wherein, substrate has on it
Being provided with grounding pattern and the first surface of pad and the second surface relative with first surface, substrate also wraps
Include arrange another pad on a second surface and be arranged on the inside of substrate with by described pad with described
The inner lead of another pad electrical connection, described method is additionally included on another pad described and arranges outside company
Connecting terminal.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310249959.4A CN103400826B (en) | 2013-06-21 | 2013-06-21 | Semiconductor packages and manufacture method thereof |
| KR20130130443A KR20140148273A (en) | 2013-06-21 | 2013-10-30 | Semiconductor package and method for fabricating the same |
| US14/307,807 US20140374901A1 (en) | 2013-06-21 | 2014-06-18 | Semiconductor package and method of fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310249959.4A CN103400826B (en) | 2013-06-21 | 2013-06-21 | Semiconductor packages and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103400826A CN103400826A (en) | 2013-11-20 |
| CN103400826B true CN103400826B (en) | 2016-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310249959.4A Active CN103400826B (en) | 2013-06-21 | 2013-06-21 | Semiconductor packages and manufacture method thereof |
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| KR (1) | KR20140148273A (en) |
| CN (1) | CN103400826B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405771B (en) * | 2014-09-11 | 2018-11-27 | 旭景科技股份有限公司 | Chip is in the method on printed circuit board |
| CN105609489B (en) * | 2015-12-29 | 2019-06-18 | 中国工程物理研究院电子工程研究所 | The structure of modularized encapsulation is carried out to chip based on improved waveguide probe transition |
| CN112164659A (en) * | 2020-09-23 | 2021-01-01 | 湖北三江航天险峰电子信息有限公司 | Welding method of radio frequency assembly |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1466206A (en) * | 2002-06-28 | 2004-01-07 | ��Ʒ���ܹ�ҵ�ɷ�����˾ | Ball grid array (BGA) semiconductor package |
| CN101315919A (en) * | 2007-07-30 | 2008-12-03 | 日月光半导体制造股份有限公司 | Chip packaging structure and technique |
| CN102956589A (en) * | 2011-08-19 | 2013-03-06 | 欣兴电子股份有限公司 | Semiconductor package structure and method for fabricating the same |
| CN103151327A (en) * | 2013-03-29 | 2013-06-12 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacturing method thereof |
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| CN102315135B (en) * | 2010-07-09 | 2014-08-20 | 联咏科技股份有限公司 | Chip package and manufacturing process thereof |
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2013
- 2013-06-21 CN CN201310249959.4A patent/CN103400826B/en active Active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1466206A (en) * | 2002-06-28 | 2004-01-07 | ��Ʒ���ܹ�ҵ�ɷ�����˾ | Ball grid array (BGA) semiconductor package |
| CN101315919A (en) * | 2007-07-30 | 2008-12-03 | 日月光半导体制造股份有限公司 | Chip packaging structure and technique |
| CN102956589A (en) * | 2011-08-19 | 2013-03-06 | 欣兴电子股份有限公司 | Semiconductor package structure and method for fabricating the same |
| CN103151327A (en) * | 2013-03-29 | 2013-06-12 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacturing method thereof |
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| CN103400826A (en) | 2013-11-20 |
| KR20140148273A (en) | 2014-12-31 |
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