CN204495485U - The low-power consumption multi-point temp detection system of integrated circuit SOC (system on a chip) - Google Patents
The low-power consumption multi-point temp detection system of integrated circuit SOC (system on a chip) Download PDFInfo
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- CN204495485U CN204495485U CN201520215076.6U CN201520215076U CN204495485U CN 204495485 U CN204495485 U CN 204495485U CN 201520215076 U CN201520215076 U CN 201520215076U CN 204495485 U CN204495485 U CN 204495485U
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Abstract
A kind of low-power consumption multi-point temp detection system of integrated circuit SOC (system on a chip) comprises temperature sensor module, Temperature control module, analog to digital converter module, temperature selector module, temperature memory module and test controller module.The output terminal of temperature sensor module is connected with the input end of Temperature control module by signal wire, the output terminal of Temperature control module is connected by the input end of signal wire with analog to digital converter module, the output terminal of analog to digital converter module selects module and low temperature to select the input end of module to be connected by signal wire and the high temperature in temperature selector module, high temperature selects module and low temperature to select the output terminal of module to be connected with the high temperature storage module input in temperature memory module and low temperature memory module input end respectively by signal wire, high temperature storage module output terminal and low temperature memory module output terminal are connected with the input end of the high temperature test scheduler module in test controller module and low-temperature test scheduler module input end respectively by signal wire.
Description
Technical field
The utility model relates to integrated circuit verification measuring technology, particularly a kind of multi-point temp detection system of integrated circuit SOC (system on a chip) being carried out to Low-power test.
Background technology
When validation test is carried out to the integrated circuit adopting deep sub-micron technique to realize, on integrated circuit chip there is high power consumption and highdensity impact in the core of internal system in test process, cause the core in SOC (system on a chip) to produce high temperature, the too high meeting of core temperature causes core to produce hot spot or damage.Therefore, high temperature should be avoided in test process on the impact of SOC (system on a chip) core as far as possible.If high temperature appears in the core in test process in SOC (system on a chip), must process in test process, reduce the core temperature in SOC (system on a chip).
Traditional temperature testing method is that the edge adopting thermal resistance diode to receive core carries out temperature sampling, because test point is single, error is comparatively large, so the temperature measured is inaccurate; Besides for the test dispatching of temperature restraint not having subregion, if the combination temps of two tests are greater than given temperature range, test just can not walk abreast, thus causes multiple test can not perform more concurrent testing in the scope that temperature allows.
Summary of the invention
The purpose of this utility model be overcome prior art above-mentioned deficiency and a kind of multi-point temp detection system of integrated circuit SOC (system on a chip) being carried out to Low-power test is provided.
The technical solution of the utility model is: a kind of low-power consumption multi-point temp detection system of integrated circuit SOC (system on a chip), comprises temperature sensor module, Temperature control module, analog to digital converter module, temperature selector module, temperature memory module and test controller module.
Being provided with high temperature in described temperature selector module selects module and low temperature to select module.
High temperature storage module and low temperature memory module is provided with in described temperature memory module.
Be provided with high temperature test scheduler module and low-temperature test scheduler module in described test controller module, the output terminal of high temperature test scheduler module and low-temperature test scheduler module is connected with test bus.
The output terminal of temperature sensor module is connected by the input end of signal wire with the temperature decision logic circuit module in Temperature control module, the output terminal of Temperature control module is connected by the input end of signal wire with analog to digital converter module, the output terminal of analog to digital converter module selects module and low temperature to select the input end of module to be connected by signal wire and the high temperature in temperature selector module, high temperature in temperature selector module selects module and low temperature to select the output terminal of module to be connected with the high temperature storage module input in temperature memory module and low temperature memory module input end respectively by signal wire, high temperature storage module output terminal and low temperature memory module output terminal are connected with the input end of the high temperature test scheduler module in test controller module and low-temperature test scheduler module input end respectively by signal wire.
Described temperature sensor module comprises a plurality of temperature sensor, carries out multipoint acquisition by temperature sensor to the core in SOC (system on a chip).
Described Temperature control module comprises temperature decision logic circuit module, MUX module, hyperthermic treatment circuit module, cooling processing circuit module and continues test circuit module, the output terminal of temperature decision logic circuit module is connected by the input end of signal wire with MUX module, the output terminal of MUX module is connected with hyperthermic treatment circuit module, processing circuit module of lowering the temperature and the input end that continues test circuit module respectively by signal wire, and the temperature control end of Temperature control module is provided with temperature control bus.
The utility model compared with prior art has following features:
1, the temperature that the temperature specific heat resistor-diode surveyed due to core inside is surveyed at the edge of core is more reliable, carries out the temperature of multipoint acquisition more accurately, reliably by multiple temperature sensor in SOC (system on a chip) core inside.
2, the temperature of Temperature control module to temperature sensor feedback correspondingly processes, and effectively can avoid the generation of core local overheating phenomenon.
3, for the test dispatching of temperature restraint, if the combination temp of two tests is greater than given temperature range and just can not walks abreast, the temperature value satisfied condition is passed to temperature memory module by Temperature control module, temperature value stores by high temperature and low temperature by temperature memory module respectively, the test of high-temperature area and other test because temperature limiting is incompatible and isolated, low-temperature space and other test compatible can with more test Parallel Scheduling, thus raising testing efficiency, reduce test application time.
Below in conjunction with the drawings and specific embodiments, detailed construction of the present utility model is further described.
Accompanying drawing explanation
Accompanying drawing 1 is the structural representation of the low-power consumption multi-point temp detection system of integrated circuit SOC (system on a chip);
Accompanying drawing 2 is the structural representation of Temperature control module.
Embodiment
A low-power consumption multi-point temp detection system for integrated circuit SOC (system on a chip), comprises temperature sensor module 1, Temperature control module 2, analog to digital converter module 3, temperature selector module 4, temperature memory module 5 and test controller module 6.
Being provided with high temperature in described temperature selector module 4 selects module 4-1 and low temperature to select module 4-2.
High temperature storage module 5-1 and low temperature memory module 5-2 is provided with in described temperature memory module 5.
Be provided with high temperature test scheduler module 6-1 and low-temperature test scheduler module 6-2 in described test controller module 6, the output terminal of high temperature test scheduler module 6-1 and low-temperature test scheduler module 6-2 is connected with test bus 7.
The output terminal of temperature sensor module 1 is connected by the input end of signal wire with the temperature decision logic circuit module 2-1 in Temperature control module 2, the output terminal of Temperature control module 2 is connected by the input end of signal wire with analog to digital converter module 3, the output terminal of analog to digital converter module 3 selects module 4-1 and low temperature to select the input end of module 4-2 to be connected by signal wire and the high temperature in temperature selector module 4, high temperature in temperature selector module 4 selects module 4-1 and low temperature to select the output terminal of module 4-2 to be connected with the high temperature storage module 5-1 input end in temperature memory module 5 and low temperature memory module 5-2 input end respectively by signal wire, high temperature storage module 5-1 output terminal and low temperature memory module 5-2 output terminal are connected with the input end of the high temperature test scheduler module 6-1 in test controller module 6 and low-temperature test scheduler module 6-2 input end respectively by signal wire.
Described temperature sensor module 1 comprises a plurality of temperature sensor, carries out multipoint acquisition by temperature sensor to the core in SOC (system on a chip).
Described Temperature control module 2 comprises temperature decision logic circuit module 2-1, MUX module 2-2, hyperthermic treatment circuit module 2-3, cooling processing circuit module 2-4 and continuation test circuit module 2-5, the output terminal of temperature decision logic circuit module 2-1 is connected by the input end of signal wire with MUX module 2-2, the output terminal of MUX module 2-2 by signal wire respectively with hyperthermic treatment circuit module 2-3, the input end of cooling processing circuit module 2-4 and continuation test circuit module 2-5 connects, the temperature control end of Temperature control module 2 is provided with temperature control bus 2-6.
When validation test is carried out to integrated circuit SOC (system on a chip) 8, core 8-1 ~ 8-N in the corresponding integrated circuit SOC (system on a chip) 8 of a plurality of temperature sensors difference of temperature sensor module 1, temperature control bus 2-6 on Temperature control module 2 is connected with the core 8-1 ~ 8-N in integrated circuit SOC (system on a chip) 8 respectively, and the test bus 7 in test controller module 6 is connected with the core 8-1 ~ 8-N in integrated circuit SOC (system on a chip) 8 respectively.
Multipoint acquisition is carried out by the temperature of temperature sensor to the core 8-1 ~ 8-N in SOC (system on a chip), temperature decision logic circuit module 2-1 in Temperature control module 2 judges the temperature that temperature sensor module 1 gathers, hyperthermic treatment or cooling process is selected by MUX module 2-2, then by temperature control bus 2-6, the control signal of hyperthermic treatment circuit module 2-3 or cooling processing circuit module 2-4 is fed back to SOC (system on a chip), heat up to needing the core heating up or lower the temperature in SOC (system on a chip) or lower the temperature, the core reaching probe temperature standard is selected to proceed test, and temperature value is outputted to analog to digital converter module 3 by the output terminal continuing test circuit module 2-5, by temperature signal being outputted to temperature selector module 4 after analog to digital conversion, temperature signal is distinguished by high temperature and low temperature by temperature selector module 4, the high temperature storage module 5-1 that high temperature signal enters in temperature memory module 5 stores, the low temperature memory module 5-2 that low-temperature signal enters in temperature memory module 5 stores, the high temperature signal that high temperature storage module 5-1 stores and the low-temperature signal that low temperature memory module 5-2 stores enter high temperature test scheduler module 6-1 in test controller module 6 and low-temperature test scheduler module 6-2 respectively, United Dispatching is carried out by the 7 pairs of core tests of the test bus on controller module 6.
When needs heat up to core, adopt active heated pattern, by outer circuits, core is energized, increase voltage, core temperature is raised.
When needs are lowered the temperature to core, adopting passive refrigerating mode, by stopping test, core temperature being reduced.
In order to verify the validity of the low-power consumption multi-point temp detection system of this integrated circuit SOC (system on a chip), select ITC ' 02 benchmark SoC(SOC (system on a chip)) the p93791 circuit of platform carries out emulation experiment.P93791 is circuit largest in preferred circuit, comprises 32 cores, wherein has 18 memory cores, and 14 Logic Cores, have stronger representativeness to the complexity of circuit test.The allocation of computer of experiment is association ThinkServer series TD340 model, internal memory 8G, CPU model: E5-2407 v2,4 core Intel Xeons, dominant frequency 2.4GHz.Table 1 is experimental result.
Table 1 experimental result
| Core number | The test application time (clock periodicity) of classic method test | The test application time (clock periodicity) of native system test | Ratio (%) is reduced with classic method contrast test Applicative time |
| 5 | 29977 | 28003 | 6.59% |
| 10 | 31864 | 28761 | 9.74% |
| 15 | 32873 | 28976 | 11.85% |
| 20 | 34772 | 29879 | 14.07% |
| 25 | 36095 | 30654 | 15.07% |
| 30 | 37846 | 31576 | 16.57% |
The data of table 1 are when temperature range 80-100 DEG C that specifies and test bus width are 60, adopt the optimum test application time that native system and classic method obtain, traditional method of testing is that the edge adopting thermal resistance diode to receive core carries out temperature sampling.As can be seen from experimental data, when adopting native system test, the increase test application time along with core number reduces ratio and also increases, than classic method to test application time decreased average 12.32% thereupon.
Claims (3)
1. a low-power consumption multi-point temp detection system for integrated circuit SOC (system on a chip), is characterized in that: comprise temperature sensor module, Temperature control module, analog to digital converter module, temperature selector module, temperature memory module and test controller module;
Being provided with high temperature in described temperature selector module selects module and low temperature to select module;
High temperature storage module and low temperature memory module is provided with in described temperature memory module;
Be provided with high temperature test scheduler module and low-temperature test scheduler module in described test controller module, the output terminal of high temperature test scheduler module and low-temperature test scheduler module is connected with test bus;
The output terminal of temperature sensor module is connected by the input end of signal wire with the temperature decision logic circuit module in Temperature control module, the output terminal of Temperature control module is connected by the input end of signal wire with analog to digital converter module, the output terminal of analog to digital converter module selects module and low temperature to select the input end of module to be connected by signal wire and the high temperature in temperature selector module, high temperature in temperature selector module selects module and low temperature to select the output terminal of module to be connected with the high temperature storage module input in temperature memory module and low temperature memory module input end respectively by signal wire, high temperature storage module output terminal and low temperature memory module output terminal are connected with the input end of the high temperature test scheduler module in test controller module and low-temperature test scheduler module input end respectively by signal wire.
2. the low-power consumption multi-point temp detection system of a kind of integrated circuit SOC (system on a chip) according to claim 1, it is characterized in that: described temperature sensor module comprises a plurality of temperature sensor, by temperature sensor, multipoint acquisition is carried out to the core in SOC (system on a chip).
3. the low-power consumption multi-point temp detection system of a kind of integrated circuit SOC (system on a chip) according to claim 1 and 2, it is characterized in that: described Temperature control module comprises temperature decision logic circuit module, MUX module, hyperthermic treatment circuit module, cooling processing circuit module and continuation test circuit module, the output terminal of temperature decision logic circuit module is connected by the input end of signal wire with MUX module, the output terminal of MUX module by signal wire respectively with hyperthermic treatment circuit module, the input end of cooling processing circuit module and continuation test circuit module connects, the temperature control end of Temperature control module is provided with temperature control bus.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741560A (en) * | 2017-10-16 | 2018-02-27 | 上海御渡半导体科技有限公司 | A kind of application method of integrated circuit test device |
| CN117007883A (en) * | 2023-07-21 | 2023-11-07 | 深圳群芯微电子有限责任公司 | Multipoint temperature testing system for photoelectric coupler |
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2015
- 2015-04-10 CN CN201520215076.6U patent/CN204495485U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741560A (en) * | 2017-10-16 | 2018-02-27 | 上海御渡半导体科技有限公司 | A kind of application method of integrated circuit test device |
| CN117007883A (en) * | 2023-07-21 | 2023-11-07 | 深圳群芯微电子有限责任公司 | Multipoint temperature testing system for photoelectric coupler |
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