CN204424251U - 多芯片半导体封装结构 - Google Patents
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Abstract
本实用新型公开了一种多芯片半导体封装结构,该封装结构,包括半导体芯片,半导体芯片的第二表面形成有向第一表面延伸的开口和凹槽,且凹槽与半导体芯片的元件区背对,开口与半导体芯片的第一焊垫背对并暴露第一焊垫;第二表面、凹槽的内壁和开口的内壁上依次形成有第一绝缘层、金属布线层和第二绝缘层,凹槽内放置有至少一个功能芯片,凹槽内的其他空余空间填充有绝缘材料,且金属布线层电连接第一焊垫和功能芯片的焊垫,该封装结构能够在不增加封装厚度的基础上实现系统封装。
Description
技术领域
本实用新型涉及半导体封装结构与工艺,具体是涉及一种多芯片半导体封装结构。
背景技术
随着各式便携信息装置对内存特性需求日益多元化及电子产品的短、小、轻、薄的发展趋势,目前,半导体芯片封装结构的发展方向是将数个芯片封装在一个系统内的多芯片(Multi-Chip Package,MCP)封装结构。用以实现在一个封装体上达到多种功能或多种性能的要求。多芯片封装结构是将不同类型的芯片,如记忆芯片、存储器芯片、flash芯片等整合在一个封装体内。
然而,在有限的芯片面积下整合多个芯片,材料的封装厚度、可靠性及成本问题都需要解决。
发明内容
为了解决上述技术问题,本实用新型提出一种多芯片半导体封装结构,能够在不增加封装厚度的基础上实现系统封装,节约成本。
为实现上述目的,本实用新型的技术方案是这样实现的:
一种多芯片半导体封装结构,包括半导体芯片,所述半导体芯片具有第一表面和与其背对的第二表面;所述第一表面具有元件区和位于所述元件区周边的若干个第一焊垫,所述第二表面形成有向所述第一表面延伸的开口和凹槽,且所述凹槽与所述元件区背对,所述开口与第一焊垫背对并暴露所述第一焊垫;所述第二表面、所述凹槽的内壁和所述开口的内壁上依次形成有第一绝缘层、金属布线层和第二绝缘层,所述凹槽内放置有至少一个功能芯片,所述凹槽内的其他空余空间填充有绝缘材料,且所述金属布线层电连接所述第一焊垫和所述功能芯片的焊垫。
作为本实用新型的进一步改进,所述凹槽内间隔放置有两个所述功能芯片,两个所述功能芯片的焊垫分别与所述金属布线层电连接,且所述功能芯片和所述绝缘材料均位于所述第一绝缘层和所述金属布线层之间。
作为本实用新型的进一步改进,所述第二绝缘层上留有若干缺口,所述缺口内形成有电连接所述金属布线层的对外连接点。
作为本实用新型的进一步改进,所述对外连接点为BGA或LGA。
作为本实用新型的进一步改进,另设有连接层,所述功能芯片通过所述连接层连接于所述凹槽内第一绝缘层或所述半导体芯片上。
作为本实用新型的进一步改进,所述功能芯片为处理芯片或记忆芯片或flash芯片或前述的组合芯片。
作为本实用新型的进一步改进,所述绝缘材料为环氧树脂或聚酰亚胺或苯并环丁烯或聚苯并恶唑或酚醛树脂或聚氨酯。
作为本实用新型的进一步改进,所述元件区上设有保护层。
本实用新型的有益效果是:本实用新型提供一种多芯片半导体封装结构,通过在半导体芯片的第二表面上形成与第一表面的第一焊垫的背对的开口,并在开口内形成金属布线层,能够将半导体芯片第一表面的第一焊垫的电性引到半导体芯片的第二表面,同时在金属布线层上设置有若干BGA或LGA,这样,在与外部器件进行连接时,利用BGA或LGA的倒装焊工艺,代替打线的线焊工艺,因此,能够达到缩小半导体芯片的封装体积,满足半导体芯片小型化发展的要求。且通过在半导体芯片的第二表面上形成背对元件区的凹槽,将具有某些特定功能的功能芯片放置其中,并通过填充绝缘材料将其固定,然后,通过重布线工艺将功能芯片的焊垫与晶圆上半导体芯片的焊垫进行电性连接。这样,不仅可以降低封装厚度,还可以实现系统封装。
附图说明
图1为本实用新型实施例1步骤a中提供的晶圆结构示意图;
图2为本实用新型实施例1步骤b后的晶圆结构示意图;
图3为本实用新型实施例1步骤c后的晶圆结构示意图;
图4为本实用新型实施例1步骤d中铺设第一绝缘层后的晶圆结构示意图;
图5为本实用新型实施例1步骤d后的晶圆结构示意图;
图6为本实用新型实施例1步骤e后的晶圆结构示意图;
图7为本实用新型实施例1步骤f后的晶圆结构示意图;
图8为本实用新型实施例1步骤g后的晶圆结构示意图;
图9为本实用新型实施例1步骤h后的晶圆结构示意图;
图10为本实用新型实施例1步骤i后的晶圆结构示意图;
图11为本实用新型实施例1步骤j后的晶圆结构示意图;
图12为本实用新型实施例1步骤k后形成的多芯片半导体封装结构的示意图;
图13为本实用新型实施例2多芯片半导体封装结构示意图。
结合附图,作以下说明:
1——半导体芯片 101——第一焊垫
102——元件区 103——第一表面
104——第二表面 2——开口
3——凹槽 4——第一绝缘层
5——金属布线层 6——第二绝缘层
7——功能芯片 701——功能芯片的焊垫
8——绝缘材料 9——对外连接点
10——缺口 11——保护层
具体实施方式
实施例1
如图12所示,一种多芯片半导体封装结构,包括半导体芯片1,所述半导体芯片具有第一表面103和与其背对的第二表面104;所述第一表面具有元件区102和位于所述元件区周边的若干个第一焊垫101,元件区用来接收光源或者接收用户指纹信息,第一焊垫电性连接所述元件区;所述第二表面形成有向所述第一表面延伸的开口2和凹槽3,且所述凹槽与所述元件区背对,所述开口与第一焊垫背对并暴露所述第一焊垫;所述第二表面、所述凹槽的内壁和所述开口的内壁上依次形成有第一绝缘层4、金属布线层5和第二绝缘层6,第二绝缘层覆盖于金属布线层之上,用于保护层金属布线层不被氧化腐蚀,所述凹槽内放置有至少一个功能芯片7,所述凹槽内的其他空余空间填充有绝缘材料8,且所述金属布线层电连接所述第一焊垫和所述功能芯片的焊垫701。
上述结构中,通过在半导体芯片的第二表面上形成与第一表面的第一焊垫的背对的开口,并在开口内形成金属布线层,能够将半导体芯片第一表面的第一焊垫的电性引到半导体芯片的第二表面,同时在金属布线层上设置有若干BGA或LGA,这样,在与外部器件进行连接时,利用BGA或LGA的倒装焊工艺,代替打线的线焊工艺,因此,能够达到缩小半导体芯片的封装体积,满足半导体芯片小型化发展的要求。且通过在半导体芯片的第二表面上形成背对元件区的凹槽,将具有某些特定功能的功能芯片放置其中,并通过填充绝缘材料将其固定,然后,通过重布线工艺将功能芯片的焊垫与晶圆上半导体芯片的焊垫进行电性连接。这样,不仅可以降低封装厚度,还可以实现芯片的系统封装。
优选的,所述凹槽内间隔放置有两个所述功能芯片,两个所述功能芯片的焊垫分别与所述金属布线层电连接,且所述功能芯片和所述绝缘材料均位于所述第一绝缘层和所述金属布线层之间。可选的,所述功能芯片为处理芯片或记忆芯片或flash芯片或前述的组合芯片。
优选的,所述第二绝缘层上留有若干缺口,所述缺口内形成有电连接所述金属布线层的对外连接点9,可选的,所述对外连接点为BGA(Ball Grid Array的缩写),也可以为LGA(LandGrid Array的缩写)。
可选的,另设有连接层,所述功能芯片通过所述连接层连接于所述凹槽内第一绝缘层或所述半导体芯片上。
可选的,所述绝缘材料可以为环氧树脂或聚酰亚胺或苯并环丁烯或聚苯并恶唑或酚醛树脂或聚氨酯。
可选的,所述金属布线层的材料为铜或铝或镍或金或钛或前述组合的合金。
作为一种优选实施例,本实施例1多芯片半导体封装结构的制作方法,包括如下步骤:
a、参见图1,准备一具有若干个半导体芯片的晶圆,每个所述半导体芯片具有第一表面103和与第一表面背对的第二表面104;所述半导体芯片的第一表面上具有元件区102和位于所述元件区周边的若干第一焊垫101,若干个所述第一焊垫电连接所述元件区;
b、参见图2,对所述晶圆的第二表面进行减薄,晶圆的减薄方式可以为机械研磨或者刻蚀工艺实现;
c、参见图3,在所述晶圆的第二表面上与每个半导体芯片的第一焊垫背对的位置刻出开口2,同时,在所述晶圆的第二表面与每个半导体芯片的元件区背对的位置刻出凹槽3;具体的,形成开口和凹槽的方法是:首先,在晶圆的第二表面104上铺设一层光刻胶,通过曝光、显影等工艺将需要刻出开口与凹槽的地方进行暴露;接着,采用干法刻蚀或者湿法刻蚀,将开口与凹槽刻出。形成的开口形状可以为上下开口相等的直孔,也可以为上下开口不等的斜孔,且开口底部需要将第一焊垫暴露;凹槽形状可以为长方形、圆形等根据需要所设定的形状。
d、参见图4和图5在步骤c形成的晶圆的第二表面、每个开口的内壁、每个凹槽的内壁上覆盖一层第一绝缘层4,并使每个开口对应的第一焊垫暴露出来;暴露第一焊垫的方法可通过机械切割的方式切掉部分第一焊垫,露出第一焊垫的侧壁;也可以通过蚀刻工艺将焊垫的表面露出。
e、参见图6,在步骤d后的每个凹槽内放置至少一个功能芯片7,并使功能芯片的焊垫背向凹槽的底部;功能芯片可以为Processor(处理)芯片,Memory(记忆)芯片等功能芯片,功能芯片与封装完成的半导体芯片一起构成具有多种功能的系统封装芯片。
f、参见图7,在步骤e后的每个凹槽内填充绝缘材料8,并使绝缘材料与第二表面上的第一绝缘层平齐;即用绝缘材料将凹槽充分填充,绝缘材料可以为环氧树脂、聚酰亚胺、苯并环丁烯、聚苯并恶唑或或酚醛树脂或聚氨酯或其他适合的高分子材料。
g、参见图8,通过光刻工艺将步骤f后的功能芯片的焊垫暴露出来;
h、参见图9,在步骤g形成的第一绝缘层上、暴露出的第一焊垫的位置和暴露出的功能芯片的焊垫的位置沉积一层金属布线层5,形成第一焊垫与各功能芯片的焊垫以及各功能芯片焊垫之间的互连;
i、参见图10,在步骤h后的金属布线层外形成一层第二绝缘层6,并在其上留有若干缺口10;
j、参见图11,在步骤i形成的每个缺口内形成电连接金属布线层的对外连接点9;对外连接点可以为BGA,也可以为LGA。
k、参见图12,对晶圆进行切割,分立为单颗芯片,形成单个的多芯片半导体封装结构。
可选的,步骤d放在步骤e之后,且步骤e中在凹槽内放置功能芯片前先涂覆一层连接层,再放置于凹槽内。
实施例2
本实施例2包含实施例中所有技术特征,如图13所示,其区别在于,所述元件区上设有保护层11。保护层用于保护传感芯片的感应区不受损伤,可选的,所述保护层的材质为玻璃或膜及玻璃陶瓷等保护材料,较佳的,所述保护层的厚度在1-400微米之间。
综上,本实用新型提出一种多芯片半导体封装结构,且该封装结构中具有的凹槽为封装厚度的减小提供了有利条件,利用凹槽结构,将其他功能芯片放置其中,通过重布线工艺将线路进行互连,实现了系统封装。因此,该封装结构能够降低封装厚度,满足半导体芯片小型化发展的要求;该制作方法利用晶圆级芯片尺寸封装技术,先进行整体封装,再将晶圆切割成单颗芯片,降低了生产成本。
以上实施例是参照附图,对本实用新型的优选实施例进行详细说明。本实用新型适用于所有多芯片半导体的封装。本领域的技术人员通过对上述实施例进行各种形式上的修改或变更,或者将其运用于不同多芯片半导体的封装结构,但不背离本实用新型的实质的情况下,都落在本实用新型的保护范围之内。
Claims (8)
1.一种多芯片半导体封装结构,包括半导体芯片(1),所述半导体芯片具有第一表面(103)和与其背对的第二表面(104);所述第一表面具有元件区(102)和位于所述元件区周边的若干个第一焊垫(101),其特征在于:所述第二表面形成有向所述第一表面延伸的开口(2)和凹槽(3),且所述凹槽与所述元件区背对,所述开口与第一焊垫背对并暴露所述第一焊垫;所述第二表面、所述凹槽的内壁和所述开口的内壁上依次形成有第一绝缘层(4)、金属布线层(5)和第二绝缘层(6),所述凹槽内放置有至少一个功能芯片(7),所述凹槽内的其他空余空间填充有绝缘材料(8),且所述金属布线层电连接所述第一焊垫和所述功能芯片的焊垫(701)。
2.根据权利要求1所述的多芯片半导体封装结构,其特征在于:所述凹槽内间隔放置有两个所述功能芯片,两个所述功能芯片的焊垫分别与所述金属布线层电连接,且所述功能芯片和所述绝缘材料均位于所述第一绝缘层和所述金属布线层之间。
3.根据权利要求1所述的多芯片半导体封装结构,其特征在于:所述第二绝缘层上留有若干缺口,所述缺口内形成有电连接所述金属布线层的对外连接点(9)。
4.根据权利要求3所述的多芯片半导体封装结构,其特征在于:所述对外连接点为BGA或LGA。
5.根据权利要求1所述的多芯片半导体封装结构,其特征在于:另设有连接层,所述功能芯片通过所述连接层连接于所述凹槽内第一绝缘层或所述半导体芯片上。
6.根据权利要求1所述的多芯片半导体封装结构,其特征在于:所述功能芯片为处理芯片或记忆芯片或flash芯片或前述的组合芯片。
7.根据权利要求1所述的多芯片半导体封装结构,其特征在于:所述绝缘材料为环氧树脂或聚酰亚胺或苯并环丁烯或聚苯并恶唑或酚醛树脂或聚氨酯。
8.根据权利要求1所述的多芯片半导体封装结构,其特征在于:所述元件区上设有保护层(11)。
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