CN204289502U - The flip LED chips that light extraction efficiency high heat dispersion is good - Google Patents
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Abstract
The utility model provides the flip LED chips that a kind of light extraction efficiency high heat dispersion is good, comprise epitaxial substrate, in extension substrate top surface sequentially laminated with N-type epitaxy layer, luminescent layer, and P type epitaxial loayer, it offers shrinkage pool to described P type epitaxial loayer, and described shrinkage pool penetrates described luminescent layer downwards and extends to described N-type epitaxy layer, at described P type epitaxial loayer upper surface sequentially laminated with P contact metal layer, P block protective layer, and P surface electrode layer, and the lower surface of described P block protective layer overlaps with the upper surface of P contact metal layer, corresponding to the N-type epitaxy layer upper surface of the bottom of described shrinkage pool sequentially laminated with N contact metal layer, N surface electrode layer, and leave space between the edge of N contact metal layer and described shrinkage pool, its wall of described space is provided with insulating barrier.The flip LED chips that the utility model provides has good heat conductive electric conductivity and is conducive to improving LED chip light extraction efficiency.
Description
Technical field
The utility model belongs to the manufacture field of luminescent device, relates to a kind of light-emitting diode chip for backlight unit of inverted structure.
Background technology
Light-emitting diode (LED) light source have high efficiency, the long-life, not containing the advantage of the harmful substances such as Hg.Along with the fast development of LED technology, the performance such as brightness, life-span of LED is obtained for great lifting, makes the application of LED more and more extensive, from outdoor lightings such as street lamps to city's intraoral illuminations such as decorative lamps, uses all one after another or be replaced with LED as light source.
In semiconductor lighting industry, generally the structure of LED chip is divided into formal dress chip structure, vertical chip structure and flip chip structure three class.Compared with other two kinds of chip structures, flip chip structure has that heat dispersion is good, light extraction efficiency is high, saturation current is high and the advantage such as cost of manufacture is moderate, has been subjected to the attention of Ge great LED chip producer.When encapsulating, flip LED chips is directly connected with substrate by surperficial bump metal layer, does not need gold thread to connect, and is therefore also referred to as without gold thread encapsulation technology, has resistance to heavy current impact and reliable long-term working advantages of higher.
The method of existing making flip LED chips, as shown in Figure 1, generally need through six key steps.Step one: as shown in Fig. 2-a, part P type epitaxial loayer 13, luminescent layer 12 and N-type epitaxy layer 11 in etching epitaxial substrate 10 are with forming station stage structure, general employing ICP (Inductive Coupled Plasma) dry etching, etch mask adopts photoresist or silicon dioxide layer.Step 2: as shown in Fig. 2-b, arranges N contact metal layer 20 on N-type epitaxy layer 11 surface, is completed by electron beam evaporation process collocation lithography stripping technique.Step 3: as shown in fig. 2-c, arranges P contact metal layer 21 on P type epitaxial loayer 13 surface, is completed by electron beam evaporation process collocation lithography corrosion process.Step 4: as shown in Fig. 2-d, arranges P block protective layer 22 on P contact metal layer 21 surface, is completed by electron beam evaporation process collocation lithography corrosion process, and P block protective layer is for stopping the metal migration of P contact metal layer.Step 5: as shown in Fig. 2-e, have the insulating barrier 23 of through hole in chip surface preparation, insulating layer material is generally SiO
2, completed by PECVD (Plasma Enhanced Chemical Vapor Deposition) plasma enhanced chemical vapor deposition method collocation lithography corrosion process.Step 6: as shown in Fig. 2-f, arranges surface electrode layer on insulating barrier 23 surface, and surface electrode layer 24 is electrically connected with P block protective layer 22 and N contact metal layer 20 by through hole, is generally completed by electron beam evaporation process collocation lithography stripping technique.
Existing this flip LED chips, due to the restriction of lithographic accuracy, its flip LED chips structure formed also comes with some shortcomings part, and its electrical and thermal conductivity performance need further improvement.
Utility model content
The utility model, for making up the deficiencies in the prior art, provides a kind of and has good heat conductive electric conductivity and be conducive to improving the flip LED chips of LED chip light extraction efficiency.
The utility model is for reaching its object, and the technical scheme of employing is as follows:
The utility model provides the flip LED chips that a kind of light extraction efficiency high heat dispersion is good, comprise epitaxial substrate, in extension substrate top surface sequentially laminated with N-type epitaxy layer, luminescent layer, and P type epitaxial loayer, it offers shrinkage pool to described P type epitaxial loayer, and described shrinkage pool penetrates described luminescent layer downwards and extends to described N-type epitaxy layer, at described P type epitaxial loayer upper surface sequentially laminated with P contact metal layer, P block protective layer, and P surface electrode layer, and the lower surface of described P block protective layer overlaps with the upper surface of P contact metal layer, corresponding to the N-type epitaxy layer upper surface of the bottom of described shrinkage pool sequentially laminated with N contact metal layer, N surface electrode layer, and leave space between the edge of N contact metal layer and described shrinkage pool, its wall of described space is provided with insulating barrier.
Further, Existential Space between the edge adjoining the P contact metal layer of described shrinkage pool and the edge of the P type epitaxial loayer that adjoins described shrinkage pool.
Further, the distance between the edge adjoining the P contact metal layer of described shrinkage pool and the edge of the P type epitaxial loayer that adjoins described shrinkage pool is 2 ~ 10 μm.
Further, the distance between the edge of N contact metal layer and the edge of described shrinkage pool is 2 ~ 10 μm.
Concrete, P type epitaxial loayer it offers one or more described shrinkage pool.
Its circular in cross-section of described shrinkage pool or square or other shapes.
The technical scheme that the utility model provides has following beneficial effect:
1) flip LED chips that provides of the utility model; the lower surface edge of its P block protective layer overlaps with the top surface edge of P contact metal layer and is slightly less than P type epitaxial loayer; ohmic contact area is so not only made to increase; improve the conductive and heat-conductive ability of flip LED chips; the reflective area of LED chip also can be made to increase, thus improve the light extraction efficiency of chip.
2) flip LED chips that provides of the utility model; the lower surface edge of its P block protective layer overlaps with the top surface edge of P contact metal layer and is more than or equal to 2 μm (as 2 ~ 10 μm) with the distance at shrinkage pool edge; in addition; the edge of N contact metal layer and the distance at shrinkage pool edge are more than or equal to 2 μm (as 2 ~ 10 μm), are conducive to preventing P/N electrode from causing short circuit because fabrication error or metal move.
Accompanying drawing explanation
Fig. 1 is the existing method flow diagram preparing flip LED chips;
Fig. 2 a-Fig. 2 f respectively figure is the existing step schematic diagram preparing flip LED chips;
A kind of generalized section of the flip LED chips that Fig. 3 provides for the utility model;
The each figure of Fig. 4 a-Fig. 4 d is the vertical view that shrinkage pool that the utility model provides offers quantity and variform flip LED chips;
Fig. 5 is the preparation flow figure of preparation example 1;
Fig. 6-Fig. 9 respectively figure is the part steps schematic diagram of preparation example 1 preparation process;
Figure 10 is the preparation flow figure of preparation example 2;
Figure 11-Figure 14 respectively figure is the part steps schematic diagram of preparation example 2 preparation process.
Embodiment
Below in conjunction with drawings and Examples, the technical solution of the utility model is described further:
Embodiment 1 is flip LED chips embodiment.
The flip LED chips that the present embodiment provides, as shown in Figure 3, its schematic top plan view as depicted in fig. 4-a for its generalized section.This flip LED chips comprises epitaxial substrate 100, at epitaxial substrate 100 upper surface sequentially laminated with N-type epitaxy layer 101, luminescent layer 102 and P type epitaxial loayer 103.Wherein, offer shrinkage pool 500 at P type epitaxial loayer 103 upper surface, this shrinkage pool 500 penetrates luminescent layer 102 downwards and extends downward N-type epitaxy layer 101.At P type epitaxial loayer 103 upper surface sequentially laminated with P contact metal layer 201, P block protective layer 202 and P surface electrode layer 203; and; the lower surface of P block protective layer 202 and the upper surface of P contact metal layer 201 overlap, and namely the lower surface area of P block protective layer 202 is consistent with the upper surface area of P contact metal layer 201.Corresponding to the upper surface of the N-type epitaxy layer part bottom shrinkage pool 500 sequentially laminated with N contact metal layer 204, N surface electrode layer 205, and, reserve space between N contact metal layer 204 and shrinkage pool 500 bottom margin, thus form a void area around N contact metal layer 204 and N surface electrode layer 205.Insulating barrier 301 is provided with at the wall in space.Existential Space between the edge adjoining the P contact metal layer 201 of described shrinkage pool 500 and the edge of the P type epitaxial loayer 103 adjoining described shrinkage pool 500, namely P contact metal layer 201 is not laminated in the upper surface of the P type epitaxial layer portion adjoining shrinkage pool 500, preferably, the distance between the edge adjoining the P contact metal layer 201 of described shrinkage pool 500 and the edge of the P type epitaxial loayer 103 adjoining described shrinkage pool 500 is 2 ~ 10 μm.Preferably, the distance between the edge of N contact metal layer 204 and the edge of shrinkage pool 500 is 2 ~ 10 μm.
Specifically; flip LED chips shown in Fig. 3; its insulating barrier 301 is attached at N contact metal layer 204 side surface, the N-type epitaxy layer 101 be in void area is surperficial and side; and adjoin the exposed surface of the luminescent layer 102 of void area, P type epitaxial loayer 103, P contact metal layer 201 and P block protective layer 202, the side surface of part P surface electrode layer 203 that insulating barrier is also attached at part N surface electrode layer 205 side surface further and adjoins with shrinkage pool 500.
The present embodiment provide flip LED chips as shown in Figure 3 its be only an embodiment, quantity of offering wherein for shrinkage pool 500 can be one or multiple, concrete shape for shrinkage pool 500 cross section also can be diversified, can be such as square or circular etc., Fig. 4-a to Fig. 4-d shows several schematic top plan view being provided with different shrinkage pool quantity and the variform concrete flip LED chips of shrinkage pool.
The flip LED chips of the present embodiment, its epitaxial substrate 100 selects sapphire, and its N-type epitaxy layer 101 and P type epitaxial loayer 103 are the epitaxial layer of gallium nitride of doping, and its luminescent layer 102 is multi-layer quantum well structure.The material of P contact metal layer 201 is made up of one or more in Ag, Al, Ni, Pt, Au, ITO, and P contact metal layer 201 can play the effect of ohmic contact layer and reflector layer simultaneously.The material of P block protective layer 202 is made up of one or more in Ti, Al, TiW, Ni, Pt, Au.The material of insulating barrier 301 is by SiO
2, Si
3n
4, Al
2o
3, one or more compositions in PI and SOG.The material of P surface electrode layer 203 and N surface electrode layer 205 and N contact metal layer 204 is made up of one or more in Ti, Al, Cr, Ni, Pt, Au, Ag, AuSn, SnAg, SnAgCu, Sn.
The flip LED chips that the utility model provides, P contact metal layer 201 is consistent with the area coverage of P block protective layer 202 and edge is slightly less than P type epitaxial loayer 103.The flip LED chips of the present embodiment; the area of P block protective layer 202 and P contact metal layer 201 maximizes by it; on the one hand ohmic contact area is increased greatly; thus improve the conductive and heat-conductive ability of flip LED chips, make reflective area increase the light extraction efficiency improving chip further on the other hand.More, P contact metal layer 201 and edge consistent with the area coverage of P block protective layer 202 is slightly less than the top surface edge of P type epitaxial loayer 103, can prevent P/N electrode from causing short circuit due to fabrication error or metal migration.
For the ease of better understanding the flip LED chips that the utility model provides, the preparation process of several preparation embodiments to the flip LED chips that the utility model provides below is provided to be introduced, for reference.
Preparation example 1
This preparation example is the preparation example of the flip LED chips in embodiment 1, and the simple flow process of its preparation method is see Fig. 5.
In order to simplify view, do not illustrated by the step schematic diagram of the resist coating layer related to, graphical photoresist layer in the present embodiment, this is the common practise of this area, even if do not explain, those skilled in the art are also appreciated that.
Preparation example 1 is carried out in accordance with the following steps, and for ease of understanding, following steps composition graphs 6 ~ 9 and Fig. 3 are introduced:
Step 1): prepare an epitaxial wafer, described epitaxial wafer comprises an epitaxial substrate 100, and stacks gradually in the N-type epitaxy layer 101 of epitaxial substrate upper surface, luminescent layer 102 and P type epitaxial loayer 103; The P contact metal layer 201 of flood is prepared at P type epitaxial loayer 103 upper surface of epitaxial wafer; The thickness of P contact metal layer 201 is
preparation method is electron beam evaporation or magnetron sputtering; Then annealing in process is carried out to the P contacting metal of flood.
Step 2): the thickness preparing P block protective layer 202, the P block protective layer 202 of flood at P contact metal layer 201 upper surface of flood is
preparation method is electron beam evaporation or magnetron sputtering; The thickness preparing P surface electrode layer 203, the P surface electrode layer 203 of flood at P block protective layer 202 upper surface of flood is
preparation method is electron beam evaporation or magnetron sputtering.The sample cutaway view obtained after this step as shown in Figure 6.
Step 3): at the P surface electrode layer 203 upper surface coating photoresist of flood, patterned photoresist layer is obtained by photoetching process, make photoresist layer is formed porose, photoetching process specifically comprises resist coating, front roasting, exposure, development and rear these five little operations roasting; The corresponding P surface electrode layer 203 not covered by photoresist by erosion removal and corresponding P block protective layer 202 and corresponding P contact metal layer 201, thus expose corresponding P type epitaxial loayer 103 part surface;
Step 4): with step 3) in patterned photoresist layer be mask, carry out ICP dry etching, etch step 3) in the P type epitaxial loayer 103 that exposes and the luminescent layer 102 corresponded and part N-type epitaxy layer 101, make P type epitaxial loayer 103 is formed with shrinkage pool 500, and described shrinkage pool 500 penetrates luminescent layer 102 downwards and extends to N-type epitaxy layer 101; The total depth that epitaxial loayer is etched is
total depth described herein is the total depth that P type epitaxial loayer 103, luminescent layer 102 and N-type epitaxy layer 101 are etched.The sample cutaway view obtained after this step as shown in Figure 7.
Step 5): again with step 3) in patterned photoresist layer be mask, in shrinkage pool 500, prepare N contact metal layer 204 and N surface electrode layer 205, thickness is
preparation method is electron beam evaporation or magnetron sputtering; Wherein, N contact metal layer 204 and N surface electrode layer 205 stack gradually in being exposed to the N-type epitaxy layer upper surface bottom shrinkage pool 500, and N contact metal layer 204 and N surface electrode layer 205 are full of whole shrinkage pool 500; See Fig. 8.
Through step 5) after, the P surface electrode layer 203 formed, P block protective layer 202, the edge of P contact metal layer 201 and the coincident of P type epitaxial loayer 103, P surface electrode layer 203, P block protective layer 202 are all consistent with the upper surface area of P type epitaxial loayer 103 with the lower surface area coverage of P contact metal layer 201; N surface electrode layer 205 is all consistent with the upper surface area of N-type epitaxy layer shrinkage pool 500 with the lower surface area coverage of N contact metal layer 204, and P metal level is now connected with N metal level.
Step 6): at P surface electrode layer 203 and N surface electrode layer 205 upper surface resist coating, patterned photoresist layer is obtained by photoetching process, thus expose P surface electrode layer 203 part and N surface electrode layer 205 part of adjoining with described shrinkage pool 500 edge, the P surface electrode layer 203 that erosion removal exposes and the P block protective layer 202 corresponded and P contact metal layer 201, thus the P type epitaxial layer portion upper surface adjoining shrinkage pool 500 is exposed; The N surface electrode layer 205 that erosion removal exposes and the N contact metal layer 204 corresponded, make to there is space between N metal contact layer 204 and shrinkage pool 500 edge; Step 6) corrode both P block protective layer 202 and P contact metal layer 201 coincident formed afterwards; The P contact metal layer 201 formed after corrosion, the edge that itself and described shrinkage pool 500 adjoin and and the edge of P type epitaxial loayer 103 that adjoins of described shrinkage pool 500 between distance be 2 ~ 10 μm; Distance between its edge of N contact metal layer 204 formed after corrosion and the edge of described shrinkage pool 500 is 2 ~ 10 μm.See Fig. 9.
Step 7): with step 6) in patterned photoresist layer be mask, use electron beam evaporation process, in space, prepare insulating barrier 301, make insulating barrier 301 be covered in space wall, the thickness of insulating barrier is
finally remove residual photoresist.See Fig. 3.
Preparation example 2
The present embodiment is the another kind of preparation example of the flip LED chips in embodiment 1, and the simple flow process of its preparation method is see Figure 10.
In order to simplify view, do not illustrated by the step schematic diagram of the resist coating layer related to, graphical photoresist layer in the present embodiment, this is the common practise of this area, even if do not explain, those skilled in the art are also appreciated that.
Preparation example 2 is carried out in accordance with the following steps, for the ease of understanding, is introduced below in conjunction with Figure 11 ~ 14 and Fig. 3:
1) prepare an epitaxial wafer, described epitaxial wafer comprises an epitaxial substrate 100, and stacks gradually in the N-type epitaxy layer 101 of epitaxial substrate 100 upper surface, luminescent layer 102 and P type epitaxial loayer 103; The P contact metal layer 201 of flood is prepared at P type epitaxial loayer 103 upper surface of epitaxial wafer; The thickness of P contact metal layer 201 is
preparation method is electron beam evaporation or magnetron sputtering; Then annealing in process is carried out to the P contacting metal of flood.
2) the P block protective layer 202 of flood is prepared at P contact metal layer 201 upper surface of flood; The thickness of P block protective layer 202 is
preparation method is electron beam evaporation or magnetron sputtering; The generalized section of the sample obtained after this step is see Figure 11.
3) at the P block protective layer 202 upper surface resist coating of flood, patterned photoresist layer is obtained by photoetching process, make photoresist layer is formed porose, photoetching process specifically comprises resist coating, front roasting, exposure, development and rear these five little operations roasting; The corresponding P block protective layer 202 not covered by photoresist by erosion removal and corresponding P contact metal layer 201, thus expose corresponding P type epitaxial loayer 103 part surface;
4) with described patterned photoresist layer for mask, carry out ICP dry etching, etch step 3) in the P type epitaxial loayer 103 that exposes and the luminescent layer 102 corresponded and part N-type epitaxy layer 101, make P type epitaxial loayer 103 is formed with shrinkage pool 500, and described shrinkage pool 500 penetrates luminescent layer 102 downwards and extends to N-type epitaxy layer 101; The total depth that epitaxial loayer is etched is
(total depth described herein is the total depth that P type epitaxial loayer 103, luminescent layer 102 and N-type epitaxy layer 101 are etched).The sample cross-section schematic diagram formed after this step is see Figure 12.
5) with described patterned photoresist layer for mask, in described shrinkage pool 500, preparation is laminated in the N contact metal layer 204 of the N-type epitaxy layer upper surface be exposed to bottom shrinkage pool 500, and N contact metal layer 204 is full of whole shrinkage pool 500; Thickness is
preparation method is electron beam evaporation or magnetron sputtering; Can see Figure 13.
6) at P block protective layer 202, N contact metal layer 204 upper surface resist coating, obtain patterned photoresist layer by photoetching process, thus expose P block protective layer 202 part and N contact metal layer 204 part of adjoining described shrinkage pool 500 edge; The P block protective layer 202 that erosion removal exposes and P contact metal layer 201 corresponding with it, thus P type epitaxial loayer 103 portion of upper surface adjoining shrinkage pool 500 is exposed; The N contact metal layer 204 of erosion removal exposure simultaneously, makes to there is space between N contact metal layer 204 and shrinkage pool 500 edge; Step 6) in, corrode both P block protective layer 202 and P contact metal layer 201 coincident formed afterwards; The edge that the P contact metal layer 201 itself and the described shrinkage pool 500 that are formed after corrosion adjoin, and and the edge of P type epitaxial loayer 103 that adjoins of described shrinkage pool 500 between distance be 2 ~ 10 μm; Distance between described its edge of N contact metal layer 204 formed after corrosion and the edge of described shrinkage pool 500 is 2 ~ 10 μm.
7) with step 6) in patterned photoresist layer be mask, in described space, prepare insulating barrier 301, make insulating barrier be covered in space wall; The thickness of insulating barrier is
preparation method is electron beam evaporation process, finally removes residual photoresist; Can see Figure 14.
8) utilize the buffer action of insulating barrier 301, plate P surface electrode layer 203 at P block protective layer 202 upper surface, plate N surface electrode layer 205 at N contact metal layer 204 upper surface; Electrode metal layer thickness is
preparation method is electroless plating method, can see Fig. 3.
The technical solution of the utility model carries out on the basis of existing technology improving and obtaining, and do not carry out special instruction part in literary composition, is this technical staff and is appreciated that according to grasped prior art or common practise or knows, do not repeat them here.
The above, it is only preferred embodiment of the present utility model, not any pro forma restriction is done to the utility model, therefore all contents not departing from technical solutions of the utility model, according to technical spirit of the present utility model to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belong in the scope of technical solutions of the utility model.
Claims (6)
1. the flip LED chips that a light extraction efficiency high heat dispersion is good, comprise epitaxial substrate, in extension substrate top surface sequentially laminated with N-type epitaxy layer, luminescent layer, and P type epitaxial loayer, it is characterized in that, it offers shrinkage pool to described P type epitaxial loayer, and described shrinkage pool penetrates described luminescent layer downwards and extends to described N-type epitaxy layer, at described P type epitaxial loayer upper surface sequentially laminated with P contact metal layer, P block protective layer, and P surface electrode layer, and the lower surface of described P block protective layer overlaps with the upper surface of P contact metal layer, corresponding to the N-type epitaxy layer upper surface of the bottom of described shrinkage pool sequentially laminated with N contact metal layer, N surface electrode layer, and leave space between the edge of N contact metal layer and described shrinkage pool, its wall of described space is provided with insulating barrier.
2. flip LED chips according to claim 1, is characterized in that, Existential Space between the edge adjoining the P contact metal layer of described shrinkage pool and the edge of the P type epitaxial loayer that adjoins described shrinkage pool.
3. flip LED chips according to claim 2, is characterized in that, the distance between the edge adjoining the P contact metal layer of described shrinkage pool and the edge of the P type epitaxial loayer that adjoins described shrinkage pool is 2 ~ 10 μm.
4. flip LED chips according to claim 1, is characterized in that, the distance between the edge of N contact metal layer and the edge of described shrinkage pool is 2 ~ 10 μm.
5. flip LED chips according to claim 1, is characterized in that, P type epitaxial loayer it offers one or more described shrinkage pool.
6. flip LED chips according to claim 1, is characterized in that, its circular in cross-section of described shrinkage pool or square or other shapes.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104505446A (en) * | 2014-12-17 | 2015-04-08 | 晶科电子（广州）有限公司 | Flip LED (light-emitting diode) chip with high luminous efficiency and good heat radiating performance and preparation method thereof |
| CN106025010A (en) * | 2016-07-19 | 2016-10-12 | 厦门乾照光电股份有限公司 | Flip LED chip based on conductive DBR structure and manufacturing method thereof |
| CN116544321A (en) * | 2023-07-06 | 2023-08-04 | 季华实验室 | Preparation method of light-emitting chip, light-emitting chip and display panel |
-
2014
- 2014-12-17 CN CN201420807361.2U patent/CN204289502U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104505446A (en) * | 2014-12-17 | 2015-04-08 | 晶科电子（广州）有限公司 | Flip LED (light-emitting diode) chip with high luminous efficiency and good heat radiating performance and preparation method thereof |
| CN106025010A (en) * | 2016-07-19 | 2016-10-12 | 厦门乾照光电股份有限公司 | Flip LED chip based on conductive DBR structure and manufacturing method thereof |
| CN116544321A (en) * | 2023-07-06 | 2023-08-04 | 季华实验室 | Preparation method of light-emitting chip, light-emitting chip and display panel |
| CN116544321B (en) * | 2023-07-06 | 2024-04-02 | 季华实验室 | Preparation method of light-emitting chip, light-emitting chip and display panel |
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Address after: 511458 Nansha District, Guangzhou, South Ring Road, No. 33, No. Patentee after: GUANGDONG APT ELECTRONICS LTD. Address before: 511458 Nansha District, Guangzhou, South Ring Road, No. 33, No. Patentee before: APT (Guangzhou) Electronics Ltd. |