CN204272027U

CN204272027U - Oscillating circuit

Info

Publication number: CN204272027U
Application number: CN201420852169.5U
Authority: CN
Inventors: 吴艳辉; 王伟; 浦小飞
Original assignee: Shanghai Beiling Co Ltd
Current assignee: Shanghai Beiling Co Ltd
Priority date: 2014-12-23
Filing date: 2014-12-23
Publication date: 2015-04-15
Anticipated expiration: 2024-12-23

Abstract

The utility model provides a kind of oscillating circuit, for clock signal, comprising: oscillator, and it is connected between input node and output node; Oscillator-amplification circuit, it is arranged between described input node and described output node, is connected in parallel with described oscillator; Biasing resistor, it is arranged between described input node and described output node, is connected in parallel with described oscillator; Output amplifier, its input is connected to described input node, and its output exports described clock signal.Oscillating circuit of the present utility model, crystal oscillation loop and the clock signal that can obtain low-power consumption export.

Description

Oscillating circuit

Technical field

The utility model relates to a kind of oscillating circuit, the crystal oscillating circuit of particularly a kind of low-power consumption.

Background technology

Crystal oscillator has good frequency characteristic due to it, is used in a lot of chip.As shown in Figure 1, be the structural representation of oscillating circuit in prior art, the structure of this oscillating circuit is conventional Pierce oscillator circuit.

This oscillating circuit adopts inverter U0 as the amplifier of band 180 ° of phase shifts, and biasing resistor RF provides direct current biasing for the input of inverter U0, and two load capacitance C1 and C2 provide 180 ° of phase shifts, thus make circuit form stable crystal oscillation loop.180 ° of phase shifts are had between input node XIN to output node XOUT, and can amplifying signal.

Although this circuit structure is simple and easy to use, power consumption is difficult to control; Further, due to the linear zone of inverters work in the middle of reversion, make circuit power consumption larger.

The utility model aims to provide a kind of oscillating circuit of low-power consumption, can control and reduce the power consumption of oscillating circuit.

Utility model content

For this reason, the utility model provides a kind of oscillating circuit, for clock signal, comprising: oscillator, and it is connected between input node and output node; Oscillator-amplification circuit, it is arranged between described input node and described output node, is connected in parallel with described oscillator; Biasing resistor, it is arranged between described input node and described output node, is connected in parallel with described oscillator; Output amplifier, its input is connected to described input node, and its output exports described clock signal.

Further, described output amplifier comprises the first and second inverters of cascade, and described first and second inverters are CMOS inverter.

Further, described first and second inverters are connected to power supply respectively by the first and second PMOS.

Further, described oscillating circuit also comprises shaping circuit, for carrying out shaping to described clock signal.Described shaping circuit comprises the 3rd PMOS, and its drain electrode is connected to the output of described first inverter, and its grid is connected to the output of described second inverter, and its source electrode is connected to power supply.

Oscillating circuit of the present utility model, crystal oscillation loop and the clock signal that can obtain low-power consumption export.

Accompanying drawing explanation

Fig. 1 is the structural representation of oscillating circuit in prior art;

Fig. 2 is the structural representation of oscillating circuit of the present utility model;

Fig. 3 is the schematic diagram of an execution mode of inverter in Fig. 2;

Fig. 4 is the schematic diagram of another execution mode of inverter in Fig. 2;

Fig. 5 is the structural representation of an execution mode of oscillating circuit of the present utility model;

Fig. 6 is the structural representation of another execution mode of oscillating circuit of the present utility model.

Embodiment

Below in conjunction with the drawings and specific embodiments, oscillating circuit of the present utility model is described in further detail, but not as to restriction of the present utility model.

With reference to Fig. 2, be the structural representation of oscillating circuit of the present utility model, this circuit is used for clock signal.This circuit comprises connection parallel with one another and is arranged on oscillator X, biasing resistor RF and the oscillator-amplification circuit between input node XIN and output node XOUT.Wherein, oscillator-amplification circuit is inverter U0.Biasing resistor RF provides direct current biasing for the input of inverter U0, is operated in linear zone to make inverter U0.Especially, this oscillating circuit also comprises output amplifier 100, and its input is connected to input node XIN, its output clock signal.With reference to Fig. 2, this output amplifier 100 is the first inverter U1 and the second inverter U2 of cascade.Wherein, the input of the first inverter U1 is connected to input node XIN, and the output of the first inverter U1 is connected to the input of the second inverter U2, and the output of the second inverter U2 exports final clock signal.

Visible, oscillating circuit of the present utility model adopts multistage tail current to control power consumption, its first order is enlarged into the anti-phase amplification (the inverter U0 namely in Fig. 2) of Pierce oscillator circuit, and its second level and the third level are the amplification (the first inverter U1 namely in Fig. 2 and the second inverter U2) of output signal.In prior art, because the signal amplitude of output node XOUT is comparatively large, thus the signal employing XOUT carries out output amplification.And in the utility model, the input signal of output amplifier 100 is from input node XIN, the program can make the ratio that the zooms into symmetry of the amplification of inverter U0 and the first inverter U1, and the DC point of the first inverter U1 is considered on the ground without the need to crossing.Second inverter U2 still needs to provide part gain amplifier, to make the final clock signal exported along comparatively steep, thus reduces power consumption.

Owing to have employed low power dissipation design, the input signal of output amplifier 100 and the signal amplitude of input node XIN less, at this signal after the first inverter U1 amplifies, signal amplitude can close to the amplitude of power supply, amplified by the second inverter U2 again, to control the waveform outputed signal further.

Particularly, first and second inverter U1, U2 are CMOS inverter.With reference to figure 3 and Fig. 4, be two kinds of common implementations of CMOS inverter.

Inverter in Fig. 3 adopts the PMOS of common gate and NMOS tube to realize, and its common gate is the input of inverter, and PMOS is connected with the drain electrode of NMOS tube for the output of inverter, and the source electrode of PMOS is connected to power vd D, the source ground of NMOS tube.With reference to Fig. 5, in this embodiment, CMOS inverter adopts the structure in Fig. 3 to realize.

In like manner, CMOS inverter can also adopt single NMOS tube to realize, and as shown in Figure 4, its grid is as the input of inverter, and its drain electrode is the output of inverter and is connected to power vd D, its source ground.With reference to Fig. 6, in this embodiment, CMOS inverter adopts the structure in Fig. 4 to realize.

It should be noted that the second inverter U2 in output amplifier 100 cannot be realized by single NMOS tube, so that the larger analog waveform that previous stage inverter can be exported, convert the clock waveform close to low and high level to.

In order to control power consumption further, with reference to figure 5 and Fig. 6, inverter U0, U1, U2 are directly connected to power vd D, but are connected to power vd D by PMOS.As MP0, MP1 and MP2 in figure, be not only respectively inverter U0, U1, U2 and operating current is provided, also make the power consumption of place branch road be controlled.The grid of PMOS MP0, MP1 and MP2 is all connected to bias voltage Vbias.

In order to make the rising edge of the clock signal exported and trailing edge steeper, this oscillating circuit also comprises shaping circuit, carries out shaping for the clock signal exported the second inverter U2.With reference to Fig. 5 and Fig. 6, this shaping circuit is the 3rd PMOS MP3, and its drain electrode is connected to the output of the first inverter U1, and its grid is connected to the output of the second inverter U2, and its source electrode is connected to power vd D.When the rising of A point voltage, B point voltage decline, the 3rd PMOS MP3 fast conducting after critical value, draws high A point voltage, makes the voltage of B point be reduced to 0 fast; Similarly, when the decline of A point voltage, B point voltage rise, the 3rd PMOS MP3 closes, and makes A point voltage continue to decline, the rising of B point voltage.So can realize the shaping to the clock signal that the second inverter U2 exports, make its rising edge and trailing edge steeper, thus make in the time of rear class experience linear zone shorter, to reduce power consumption further.

Above embodiment is only illustrative embodiments of the present utility model, can not be used for limiting the utility model, and protection range of the present utility model is defined by the claims.Those skilled in the art can in essence of the present utility model and protection range, and make various amendment or equivalent replacement to the utility model, these are revised or be equal to replacement and also should be considered as dropping in protection range of the present utility model.

Claims

1. an oscillating circuit, for clock signal, is characterized in that, comprising:

Oscillator, it is connected between input node and output node;

Oscillator-amplification circuit, it is arranged between described input node and described output node, is connected in parallel with described oscillator;

Biasing resistor, it is arranged between described input node and described output node, is connected in parallel with described oscillator;

Output amplifier, its input is connected to described input node, and its output exports described clock signal.

2. oscillating circuit according to claim 1, is characterized in that, described output amplifier comprises the first and second inverters of cascade.

3. oscillating circuit according to claim 2, is characterized in that, described first and second inverters are CMOS inverter.

4. oscillating circuit according to claim 3, is characterized in that, described first and second inverters are connected to power supply respectively by the first and second PMOS.

5. oscillating circuit according to claim 2, is characterized in that, described oscillating circuit also comprises shaping circuit, for carrying out shaping to described clock signal.

6. oscillating circuit according to claim 5, is characterized in that, described shaping circuit comprises the 3rd PMOS, and its drain electrode is connected to the output of described first inverter, and its grid is connected to the output of described second inverter, and its source electrode is connected to power supply.