CN103199799B - A kind of power amplifier biased with technological compensa tion - Google Patents
A kind of power amplifier biased with technological compensa tion Download PDFInfo
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- CN103199799B CN103199799B CN201310135954.9A CN201310135954A CN103199799B CN 103199799 B CN103199799 B CN 103199799B CN 201310135954 A CN201310135954 A CN 201310135954A CN 103199799 B CN103199799 B CN 103199799B
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- 238000005516 engineering process Methods 0.000 abstract description 5
- 230000008859 change Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Abstract
The invention discloses a kind of power amplifier biased with technological compensa tion, it comprises control circuit, input buffer circuit, technological compensa tion biasing circuit, power-amplifier stage, output matching circuit.Control circuit is in order to control the work of whole power amplifier, input buffer circuit is in order to improve the driving force of input signal, biasing circuit is in order to provide biased to power amplifier tube, and power-amplifier stage is in order to amplify input power, and output matching circuit is in order to mate output impedance.The biasing circuit that the present invention adopts has temperature and technological compensa tion effect, ensure that the temperature that power amplifier tube is good and technology stability, there is stronger power supply rejection ability simultaneously, make power amplifier can keep linear convergent rate in the larger context, improve the linearity of power amplifier.
Description
Technical field
The present invention relates to the power amplifier in transceiver, particularly relates to a kind of power amplifier biased with technological compensa tion.
Background technology
Power amplifier is mainly used in the transmitting terminal of microwave and radio circuit.In transmitting terminal, the Main Function of power amplifier amplifies radiofrequency signal, and for the purpose of high efficiency output is high-power.A power amplifier of good performance can provide enough power to its load in the frequency range of specifying, enough gains are provided to input signal, if the signal of transmission is non-constant envelope signal, power amplifier has also needed the good linearity undistorted to ensure signal.
And the biased linearity affecting power amplifier to a great extent of power amplifier tube, because power amplifier tube threshold voltage all can change with temperature, technique, the reference voltage of common zero-temperature coefficient can not meet the offset requirements of power amplifier tube, so it is most important to invent a kind of bias-voltage generating circuit synchronously changed with power amplifier tube threshold voltage.
Summary of the invention
The object of this invention is to provide a kind of power amplifier biased with technological compensa tion.
In order to achieve the above object, present invention employs following technical scheme:
With an overall schematic for technological compensa tion current offset power amplifier, it comprises control circuit, input buffer circuit, technological compensa tion biasing circuit, power-amplifier stage, output matching circuit.Control circuit is in order to control the work of whole power amplifier, input buffer circuit is in order to improve the driving force of input signal, biasing circuit is in order to provide biased to power amplifier tube, and power-amplifier stage is in order to amplify input power, and output matching circuit is in order to mate output impedance.
Further, described technological compensa tion biasing circuit comprises a band gap reference and an operational amplifier, the output voltage of described band gap reference is connected to the reverse input end of described operational amplifier, the output of described operational amplifier is connected to the 3rd, the grid of the 4th PMOS, described 3rd, the drain electrode of the 4th PMOS is connected to first successively, one end of second resistance, the drain electrode of described 3rd PMOS is also connected to the positive input of described operational amplifier, the other end of described first resistance connects the emitter of a PNP triode, base stage and the collector electrode of described PNP triode are all connected to earth potential, the other end of described second resistance then connects the drain and gate of second NMOS tube, the source electrode of described second NMOS tube is connected to earth potential.
Further, described power-amplifier stage comprises one the 3rd NMOS tube and one the 4th NMOS tube, described 3rd, 4th NMOS tube adopts cascodes, in order to avoid puncture the described 3rd, the gate oxide of the 4th NMOS tube, the drain electrode of described 4th NMOS tube is as the output of described power-amplifier stage, earth potential is received in the drain electrode of described 3rd NMOS tube, described power-amplifier stage also comprises first of the fluctuation of the output for limiting described power-amplifier stage, second, 3rd diode, described first, second diode reverse is serially connected between the drain and gate of described 4th NMOS tube, described 3rd diode is connected between described 3rd NMOS tube and the drain electrode of the 4th NMOS tube.The second electric capacity is connected with between the grid of described 3rd, the 4th NMOS tube.
The output current of described band gap reference is connected to the current input terminal of described control circuit, the output voltage of described control circuit is connected to the control input end of described input buffer circuit, the output of described input buffer circuit connects the grid of described 3rd NMOS tube by the first electric capacity, the output of described power-amplifier stage connects the input of described output matching circuit; The input signal of described input buffer circuit is the input of the power amplifier that described band technological compensa tion is biased, and the output signal of described output matching circuit is the output of the power amplifier that described band technological compensa tion is biased.
The output of described technological compensa tion biasing circuit is connected to the grid of described 3rd NMOS tube by the 3rd resistance, because the output of described technological compensa tion biasing circuit can regulate automatically according to temperature, technique change, so the output of described technological compensa tion biasing circuit can compensate the change of described 3rd NMOS tube threshold voltage with temperature, technique, thus ensure that this pipe angle of flow is constant, make output more stable, improve the linearity of power amplifier.
Further, described is output matching circuit, employing be L-type coupling, its object mates output impedance exactly, makes power output maximum.
By the application of above-mentioned technology, tool of the present invention has the following advantages: this biasing circuit that the present invention adopts can change by temperature sensor, technique change can be responded to again, thus make corresponding adjustment, and the output offset voltage of this biasing circuit has very high Power Supply Rejection Ratio, the bias voltage that this biasing circuit produces effectively compensate for the change of power amplifier tube threshold voltage, stabilize the angle of flow of power amplifier tube, ensure that the stability of power output, improve the linearity of power amplifier.
Accompanying drawing explanation
Accompanying drawing 1 is the structural representation of the power amplifier that band technological compensa tion of the present invention is biased
Accompanying drawing 2 is the schematic diagram of control circuit of the present invention
Accompanying drawing 3 is the schematic diagram of input buffer circuit of the present invention
Accompanying drawing 4 is the schematic diagram of biasing circuit of the present invention
Accompanying drawing 5 is the schematic diagram of power-amplifier stage of the present invention
Accompanying drawing 6 is the schematic diagram of output matching circuit of the present invention
Embodiment
Below in conjunction with drawings and Examples, technology implementation process of the present invention is described further.
Fig. 1 is the overall schematic of band technological compensa tion current offset power amplifier provided by the invention, and it comprises control circuit, input buffer circuit, technological compensa tion biasing circuit, power-amplifier stage, output matching circuit.Control circuit is in order to control the work of whole power amplifier, input buffer circuit is in order to improve the driving force of input signal, biasing circuit is in order to provide biased to power amplifier tube, and power-amplifier stage is in order to amplify input power, and output matching circuit is in order to mate output impedance.Above-mentioned control circuit, input buffer circuit, biasing circuit, power-amplifier stage all adopt CMOS technology to be integrated in a chip, and output matching circuit is owing to having used large inductance, then adopt sheet to connect outward.
Figure 4 shows that the technological compensa tion biasing circuit that the present invention adopts, described technological compensa tion biasing circuit comprises a band gap reference Bandgap and operational amplifier A 1, the output voltage VBG of described band gap reference Bandgap is connected to the reverse input end of described operational amplifier A 1, the output of described operational amplifier A 1 is connected to the 3rd, 4th PMOS P3, the grid of P4, described 3rd, 4th PMOS P3, the drain electrode of P4 is connected to first successively, second resistance R1, one end of R2, the drain electrode of described 3rd PMOS P3 is also connected to the positive input of described operational amplifier A 1, the other end of described first resistance R1 connects the emitter of a PNP triode Q1, base stage and the collector electrode of described PNP triode Q1 are all connected to earth potential, the other end of described second resistance HR2 then connects the drain and gate of a second NMOS tube N2, the source electrode of described second NMOS tube N2 is connected to earth potential.
Introduce the operation principle of this biasing circuit below, the short characteristic of void of amplifier makes V2=VBG, then have
Because I2=I1, and
So
V in above formula
eBhave negative temperature coefficient, R1, R2 have positive temperature coefficient, and suitable Circuit tuning parameter can make first two of Vbias to have zero-temperature coefficient, so the change of temperature, technique is all embodied in threshold voltage V
ton.
Figure 2 shows that control circuit, the output current Ibias of described band gap reference Bandgap provides electric current for circuit, modulation signal ASK and enable signal EN is input to logical block, it exports the grid that V1 is connected to the first PMOS P1 and the first NMOS tube N1, first PMOS P1 is connected with the drain electrode of the first NMOS tube N1 and is connected to the source electrode of the second PMOS p2, and the output voltage Vctrl that the drain electrode of the second PMOS P2 and grid short circuit produce control circuit carrys out control inputs buffer circuit.
Figure 3 shows that input buffer circuit, the voltage input end of described buffer circuit is connected to the output voltage Vctrl of described control circuit, input signal Vin is connected to power-amplifier stage by what inverter, and input buffer circuit is mainly by the driving force improving input signal.
Fig. 5 is power-amplifier stage of the present invention, described power-amplifier stage comprises one the 3rd NMOS tube N3 and the 4th NMOS tube N4, described 3rd, 4th NMOS tube N3, N4 adopts cascodes, in order to avoid puncture N3, the gate oxide of N4, the drain electrode of described 4th NMOS tube N4 is as the output PA_out of described power-amplifier stage, earth potential is received in the drain electrode of described 3rd NMOS tube N3, described power-amplifier stage also comprises first of the fluctuation of the output PA_out for limiting described power-amplifier stage, second, 3rd diode D1, D2, D3, described first, second diode D1, D2 is oppositely serially connected between the drain and gate of described 4th NMOS tube N4, described 3rd diode D3 is connected between described 3rd NMOS tube N3 and the drain electrode of the 4th NMOS tube N4.The second electric capacity C2 is connected with between the grid of described 3rd, the 4th NMOS tube N3, N4.The output Vbias of described technological compensa tion biasing circuit is connected to the grid of described 3rd NMOS tube N3 by the 3rd resistance R3, due to V in Vbias expression formula
talso automatically can regulate according to temperature, technique change, so Vbias can compensate the change of described 3rd NMOS tube N3 threshold voltage with temperature, technique, thus ensure that this pipe angle of flow is constant, make output more stable, improve the linearity of power amplifier.
Fig. 6 is output matching circuit, employing be L-type coupling, its object mates output impedance exactly, makes power output maximum.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. the power amplifier be biased with technological compensa tion, it comprises control circuit, input buffer circuit, technological compensa tion biasing circuit, power-amplifier stage, output matching circuit, described control circuit is in order to control the work of whole power amplifier, described input buffer circuit is in order to improve the driving force of input signal, described biasing circuit is in order to provide biased to power amplifier tube, described power-amplifier stage is in order to amplify input power, described output matching circuit is in order to mate output impedance, it is characterized in that: described technological compensa tion biasing circuit comprises a band gap reference (Bandgap) and an operational amplifier (A1), the output voltage (VBG) of described band gap reference (Bandgap) is connected to the reverse input end of described operational amplifier (A1), the output of described operational amplifier (A1) is connected to the 3rd, 4th PMOS (P3, P4) grid, described 3rd, 4th PMOS (P3, P4) drain electrode is connected to first successively, second resistance (R1, R2) one end, the drain electrode of described 3rd PMOS (P3) is also connected to the positive input of described operational amplifier (A1), the other end of described first resistance (R1) connects the emitter of a PNP triode (Q1), base stage and the collector electrode of described PNP triode (Q1) are all connected to earth potential, the other end of described second resistance (R2) then connects the drain and gate of second NMOS tube (N2), the source electrode of described second NMOS tube (N2) is connected to earth potential.
2. the power amplifier that band technological compensa tion according to claim 1 is biased, it is characterized in that: described power-amplifier stage comprises one the 3rd NMOS tube (N3) and one the 4th NMOS tube (N4), described 3rd, 4th NMOS tube (N3, N4) cascodes is adopted, the drain electrode of described 4th NMOS tube (N4) is as the output (PA_out) of described power-amplifier stage, earth potential is received in the drain electrode of described 3rd NMOS tube (N3), described power-amplifier stage also comprises first of the fluctuation of the output (PA_out) for limiting described power-amplifier stage, second, 3rd diode (D1, D2, D3), described first, second diode (D1, D2) between the drain and gate being oppositely serially connected in described 4th NMOS tube (N4), described 3rd diode (D3) is connected between described 3rd NMOS tube (N3) and the drain electrode of the 4th NMOS tube (N4), the second electric capacity (C2) is connected with between the grid of described 3rd, the 4th NMOS tube (N3, N4).
3. the power amplifier that band technological compensa tion according to claim 2 is biased, it is characterized in that: the output (Vbias) of described technological compensa tion biasing circuit is connected to the grid of described 3rd NMOS tube (N3) by the 3rd resistance (R3), the output current (Ibias) of described band gap reference (Bandgap) is connected to the current input terminal of described control circuit, the output voltage (Vctrl) of described control circuit is connected to the control input end of described input buffer circuit, the output (PA_in) of described input buffer circuit connects the grid of described 3rd NMOS tube (N3) by the first electric capacity (C1), the output (PA_out) of described power-amplifier stage connects the input of described output matching circuit, the input of the power amplifier that the input signal (Vin) of described input buffer circuit is biased for described band technological compensa tion, the output of the power amplifier that the output signal (Vout) of described output matching circuit is biased for described band technological compensa tion.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310135954.9A CN103199799B (en) | 2013-04-19 | 2013-04-19 | A kind of power amplifier biased with technological compensa tion |
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| CN201310135954.9A CN103199799B (en) | 2013-04-19 | 2013-04-19 | A kind of power amplifier biased with technological compensa tion |
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| CN103199799A CN103199799A (en) | 2013-07-10 |
| CN103199799B true CN103199799B (en) | 2015-12-09 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104158498B (en) * | 2014-07-22 | 2017-01-11 | 江苏星宇芯联电子科技有限公司 | Low-noise amplifier with compensation bias circuit |
| CN106374852B (en) * | 2015-07-20 | 2019-11-08 | 瑞昱半导体股份有限公司 | Driver |
| US10978111B1 (en) | 2019-12-05 | 2021-04-13 | Winbond Electronics Corp. | Sense amplifier circuit with reference voltage holding circuit for maintaining sense amplifier reference voltage when the sense amplifier operates under standby mode |
| CN111277234B (en) * | 2020-04-10 | 2023-06-02 | 重庆百瑞互联电子技术有限公司 | Power amplifier |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101090272A (en) * | 2007-07-05 | 2007-12-19 | 复旦大学 | Mixed digital pulse duration modulater suitable for digital power supply controller |
| CN101777374A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Readout amplifier with process and current compensation |
| CN102882471A (en) * | 2012-09-14 | 2013-01-16 | 苏州锐控微电子有限公司 | Complementary metal oxide semiconductor (CMOS) process-based high-accuracy on-chip clock oscillator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7154329B2 (en) * | 2004-12-16 | 2006-12-26 | M/A-Com, Inc. | Method and apparatus for compensating amplifier output for temperature and process variations |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101090272A (en) * | 2007-07-05 | 2007-12-19 | 复旦大学 | Mixed digital pulse duration modulater suitable for digital power supply controller |
| CN101777374A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Readout amplifier with process and current compensation |
| CN102882471A (en) * | 2012-09-14 | 2013-01-16 | 苏州锐控微电子有限公司 | Complementary metal oxide semiconductor (CMOS) process-based high-accuracy on-chip clock oscillator |
Non-Patent Citations (2)
| Title |
|---|
| A Common-Gate Switched,0.9W Class-E Power Amplifier with 41% PAE in 0.25um CMOS;Changsik Yoo,etc;《Solid-State Circuits》;20010531;第36卷(第5期);第56-57页 * |
| 一种新型自适应偏置线性功率放大器;吴拓,等;《微电子学与计算机》;20091130;第26卷(第11期);第5-8页 * |
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