CN109889165B - Amplifier with adjustable output common-mode voltage - Google Patents

Abstract

The invention discloses an output common-mode voltage adjustable amplifier, which comprises a self-adaptive current bias stage, a common-mode voltage adjusting circuit and a self-bias load amplifier; the self-bias load amplifier is used for forming a virtual ground point between the two NMOS tubes, providing a grid bias voltage for the virtual ground point and providing gain; the self-adaptive current bias stage clamps one end of a resistor to reference voltage by using an amplifier, and when the power supply voltage changes, the variable quantity of the power supply voltage is totally reflected on the resistor and is converted into the variable quantity of the bias current; the residual current of the reference current source after being pulled by the bias current flows through a load resistor in the common mode voltage regulating circuit to form self-adaptive voltage drop, so that the output common mode voltage regulation is realized. The invention can adjust the magnitude of the output common-mode voltage, obviously improve the drain-source voltage of the tail current source of the post-stage circuit under the low-voltage design, improve the circuit performance, and is suitable for the application occasions such as the programmable gain amplifier under the low-voltage and low-power consumption, and the like.

Description

An Amplifier with Adjustable Output Common-Mode Voltage

technical field

The invention relates to an amplifier with adjustable output common-mode voltage, belonging to the technical field of programmable gain amplifiers.

Background technique

In the radio frequency receiving system, the programmable gain amplifier is an important part of the wireless communication module, which is mainly used to expand the dynamic range of the received signal to improve the overall performance of the receiving chain. It adjusts the amplification gain of the signal according to the strength of the input signal, so that the amplitude of the output signal is constant, so as to ensure that the receiver can correctly demodulate the received signal.

In order to make the output signal amplitude constant, one of the methods is to introduce a master-slave structure to obtain a constant transconductance. For this reason, the power consumption level of the programmable gain amplifier occupies a considerable share in the receive chain. In order to realize the low power consumption of the overall receiving circuit, with the progress of the technology, a lower power supply voltage is adopted for design. However, under low voltage, the performance of the tail current source of the next stage circuit is affected due to the high output common-mode voltage.

In a traditional differential amplifier, when the input common-mode level is constant, the output common-mode voltage cannot be adaptively adjusted as the power supply voltage changes. In a programmable gain amplifier, in order to obtain a small change in gain with temperature, a master-slave structure is often used to obtain a constant transconductance, which requires error sampling at the output of the self-biased load amplifier. In the case of low voltage, when the common-mode voltage of the output terminal of the self-biased load amplifier is high, the source-to-drain voltage of the tail current source of the error sampling circuit is small, so that the normal operation of the circuit cannot be guaranteed.

Contents of the invention

The technical problem to be solved by the present invention is to overcome the problem of high common-mode voltage in low-voltage and low-power Adapt to adjust the size of the output common-mode voltage. It is suitable for applications such as programmable gain amplifiers under low voltage and low power consumption.

The present invention specifically adopts the following technical solutions to solve the above technical problems:

An adjustable output common-mode voltage amplifier, including an adaptive current bias stage, a common-mode voltage regulation circuit, and a self-biased load amplifier; the self-biased load amplifier is used to form a virtual point between two NMOS tubes And provide gate bias voltage for it, provide gain and multiplex the load resistance with the common mode voltage regulation circuit at the same time; The adaptive current bias stage uses the amplifier to clamp one end of the resistance to the reference voltage, when the power supply voltage changes The amount of change is all reflected in the resistance and correspondingly converted into the amount of bias current change; after the reference current source in the common-mode voltage regulation circuit is drawn by the bias current, the remaining current flows through the load in the common-mode voltage regulation circuit The resistors form an adaptive voltage drop for output common-mode voltage regulation.

Further, as a preferred technical solution of the present invention: the adaptive current bias stage includes a first amplifier, a first resistor, a first NMOS transistor, and a second NMOS transistor; wherein, the reference voltage is connected to the negative Input terminal, the positive input terminal of the first amplifier is connected to the negative terminal of the first resistor, and the output terminal of the first amplifier is connected to the gate of the first NMOS transistor; the source of the first NMOS transistor is connected to the ground and the drain is connected to the first The negative pole of the resistor; the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, the source of the second NMOS transistor is grounded and the drain is connected to the negative pole of the reference current source; the positive pole of the first resistor is connected to the power supply connected.

Further, as a preferred technical solution of the present invention: the common-mode voltage regulation circuit includes a reference current source, a second resistor, and a third resistor; the positive terminal of the reference current is connected to a power supply, and the negative terminals of the reference current are respectively It is connected to the negative terminal of the second resistor and the negative terminal of the third resistor; the positive terminals of the second resistor and the third resistor are respectively connected to a self-biased load amplifier.

Further, as a preferred technical solution of the present invention: the self-biased load amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein, the The gate of the third PMOS transistor is connected to the feedback voltage and the source is connected to the power supply, and the drain of the third PMOS transistor is respectively connected to the source of the first PMOS transistor and the source of the second PMOS transistor; the gate of the first PMOS transistor The pole is connected to the positive terminal of the input voltage, and the drain of the first PMOS transistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the common mode voltage regulation circuit and the source is grounded; the second PMOS transistor The gate of the second PMOS transistor is connected to the negative terminal of the input voltage, and the drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, and the fourth NMOS transistor The source is grounded.

The present invention adopts above-mentioned technical scheme, can produce following technical effect:

The output common-mode voltage adjustable amplifier of the present invention, because the self-adaptive current bias stage uses the amplifier to clamp one end of the resistance to the reference voltage, when the power supply voltage changes, the variation of the power supply voltage is all reflected on the resistance, and correspondingly converted into The amount of bias current variation; the remaining current after the reference current source is pulled by the bias current flows through the amplifier load to form an adaptive voltage drop, which realizes the adjustable output common-mode voltage. This circuit uses an amplifier to fix one end of the resistor at a reference potential. When the power supply voltage becomes smaller, the voltage drop across the resistor decreases, which means that the current flowing through the resistor decreases. Due to the virtual short and virtual break characteristics of the amplifier, the current cannot flow through the input terminal of the amplifier, so it all flows through the biased first NMOS transistor MN1, which means that the mirror biased second NMOS transistor MN2 draws less current from the reference current source, and the amplifier load There are more voltage drops on the resistors, so that the output common-mode voltage is lower under the condition of low power supply voltage, and it is easier to cascade with the lower-level error sampling circuit.

Therefore, the amplifier of the present invention can convert the change of the power supply voltage into the change of the bias current, thereby adjusting the size of the output common-mode voltage, significantly improving the drain-source voltage of the tail current source of the subsequent stage circuit under the low-voltage design, and improving the circuit performance. Performance; the present invention solves the problem that the error sampling circuit tail current source cannot work normally due to the high output common-mode voltage of the master-level self-bias load amplifier in the master-slave structure in the low-voltage and low-power programmable gain amplifier PGA link. Therefore, the present invention is suitable for applications such as programmable gain amplifiers under low voltage and low power consumption.

Description of drawings

FIG. 1 is a circuit diagram of an amplifier with an adjustable output common-mode voltage in the present invention.

Fig. 2 is a graph showing the variation of gain with temperature when the amplifier of the present invention is applied to a programmable gain amplifier.

Fig. 3 is a graph showing the variation of the gain of the programmable gain amplifier chain with temperature according to the present invention.

detailed description

Embodiments of the present invention will be described below in conjunction with the accompanying drawings.

As shown in Fig. 1, the present invention has designed a kind of output common-mode voltage adjustable amplifier, comprises adaptive current bias stage, common-mode voltage regulation circuit and self-biased load amplifier; Described adaptive current bias stage is responsible for The variation of the power supply voltage is converted into the variation of the bias current; the common-mode voltage regulation circuit indirectly converts the current and voltage of the bias current; the self-biased load amplifier is responsible for providing gain. Specifically, the self-biased load amplifier is used to form a virtual point between two NMOS transistors and provide a gate bias voltage for it, and at the same time provide gain and multiplex a load resistance with a common-mode voltage regulation circuit; the self-biased load amplifier The adaptive current bias stage uses an amplifier to clamp one end of the resistor to the reference voltage, and when the power supply voltage changes, the variation of the power supply voltage is all reflected on the resistor and correspondingly converted into a variation of the bias current; the common-mode voltage regulation circuit After the reference current source is drawn by the bias current, the remaining current flows through the load resistance in the common-mode voltage regulation circuit to form an adaptive voltage drop, thereby realizing the regulation of the output common-mode voltage.

Specifically, the adaptive current bias stage includes a first amplifier A1, a first resistor R1, a first NMOS transistor MN1, and a second NMOS transistor MN2; wherein, the reference voltage is connected to the negative input terminal of the first amplifier A1, and the first The positive input terminal of the amplifier A1 is connected to the negative terminal of the first resistor R1, and the output terminal of the first amplifier A1 is connected to the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is connected to the ground and the drain is connected to the first The negative pole of the resistor R1; the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, the source of the second NMOS transistor MN2 is grounded and the drain is connected to the negative pole of the reference current source; the first resistor The positive pole of R1 is connected to the power supply.

The common-mode voltage regulation circuit includes a reference current source, a second resistor R2, and a third resistor R3; the positive end of the reference current is connected to the power supply, and the negative end of the reference current is connected to the negative end of the second resistor R2, the third resistor R2, and the third resistor R2 respectively. The negative terminals of the resistor R3 are connected; the positive terminals of the second resistor R2 and the third resistor R3 are respectively connected to the self-biased load amplifier, that is, the positive terminal of the second resistor R2 is connected to the first PMOS in the self-biased load amplifier The drain of the transistor MP1; the positive end of the third resistor R3 is connected to the drain of the second PMOS transistor MP2 in the self-biased load amplifier.

The self-biased load amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a third NMOS transistor MN3, and a fourth NMOS transistor MN4; wherein, the gate of the third PMOS transistor MP3 The feedback voltage is connected and the source is connected to the power supply, and the drain of the third PMOS transistor MP3 is respectively connected to the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2; the gate of the first PMOS transistor MP1 is connected to the input The positive terminal of the voltage, and the drain of the first PMOS transistor MP1 is connected to the drain of the third NMOS transistor MN3, the positive terminal of the second resistor R2 is connected to the drain of the third NMOS transistor MN3 and the drain of the first PMOS transistor MP1 connected; the gate of the third NMOS transistor MN3 is connected to the negative terminal of the second resistor R2 in the common-mode voltage regulation circuit, and the source of the third NMOS transistor MN3 is grounded; the gate of the second PMOS transistor MP2 is connected to the input voltage negative terminal, and the drain of the second PMOS transistor MP2 is connected to the drain of the fourth NMOS transistor MN4, the positive end of the third resistor R3 is connected to the drain of the fourth NMOS transistor MN4 and the drain of the second PMOS transistor MP2 connected, and the negative end of the third resistor R3 is connected to the negative end of the second resistor R2; the gate of the fourth NMOS transistor MN4 is connected to the gate of the third NMOS transistor MN3, and the source of the fourth NMOS transistor MN4 grounded.

The operating principle of the amplifier of the present invention is: the self-biased load amplifier forms a virtual point between the third NMOS transistor MN3 and the fourth NMOS transistor MN4 and provides a gate bias voltage for it, and at the same time provides Gain and multiplex the second resistor R2 and the third resistor R3 of the load with the common-mode voltage regulation circuit; the self-adaptive current bias stage clamps one end of the first resistor R1 to Reference voltage, when the power supply voltage changes, the variation of the power supply voltage is all reflected on the first resistor R1, and correspondingly converted into the variation of the bias current; in view of the extremely large input impedance of the amplifier, the bias current all flows through the first NMOS Tube MN1. The first and second NMOS transistors MN1 and MN2 are connected in a current mirror mirroring method, so the bias current is finally reflected on the second NMOS transistor MN2. The remaining current after the reference current source in the common-mode voltage regulation circuit is pulled by the bias current flows through the load resistors R2 and R3 in the common-mode voltage regulation circuit to form an adaptive voltage drop. If the power supply voltage is high, the voltage drop on the load resistors R2 and R3 is small, and the output common-mode voltage is high; if the power supply voltage is low, the voltage drop on the load resistors R2 and R3 is large, and the output common-mode voltage is low. Thus, the function of output common-mode voltage adjustable is realized.

The circuit uses the first amplifier A1 to fix one end of the first resistor R1 at the reference potential. When the power supply voltage becomes smaller, the voltage drop across the resistor decreases, which means that the current flowing through the resistor decreases. Due to the virtual short and virtual break characteristics of the amplifier, the current cannot flow through the input terminal of the amplifier, so it all flows through the biased first NMOS transistor MN1, which means that the mirror biased second NMOS transistor MN2 draws less current from the reference current source, and the amplifier load There are more voltage drops on the resistors R2 and R3, so that the output common-mode voltage is lower under the condition of low power supply voltage, and it is easier to cascade with the lower-level error sampling circuit.

As shown in Figure 2, it is a graph showing that the low-voltage, low-power output common-mode voltage adjustable amplifier of this embodiment is applied to a programmable gain amplifier as a function of temperature, and its power supply voltage is 700mv; it can be seen from the figure , in the temperature range of -40 ℃ ~ 80 ℃, the single-stage operational amplifier gain variation is only 0.1dB.

As shown in Figure 3, it is a curve diagram of the gain of the amplifier in this embodiment applied to the programmable gain amplifier chain as a function of temperature. Under the power supply voltage of 700mv, the gain variation of the entire programmable gain amplifier chain is only more than 0.5dB. .

From the above, it can be seen that the innovation of the present invention is mainly embodied in the adaptive current bias stage and common-mode voltage regulation. The output common-mode voltage adjustable amplifier proposed by the present invention converts the change of the power supply voltage into the change of the bias current, thereby adjusting the size of the output common-mode voltage, and significantly improving the drain-source of the tail current source of the rear-stage circuit under low-voltage design voltage, improving the performance of the circuit. Therefore, the present invention is suitable for applications such as programmable gain amplifiers under low voltage and low power consumption.

The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and can also be made without departing from the gist of the present invention within the scope of knowledge possessed by those of ordinary skill in the art. Variations.

Claims (2)

1. A kind of output common-mode voltage adjustable amplifier is characterized in that, comprises adaptive current bias stage, common-mode voltage regulation circuit and self-biased load amplifier; Described self-biased load amplifier is used in two NMOS A virtual point is formed between the transistors and a gate bias voltage is provided for it, while providing gain and multiplexing the load resistor with the common-mode voltage regulation circuit; the adaptive current bias stage uses an amplifier to clamp one end of the resistor to a reference voltage, when When the power supply voltage changes, the variation of the power supply voltage is all reflected in the resistance and correspondingly converted into the variation of the bias current; the remaining current after the reference current source in the common-mode voltage regulation circuit is drawn by the bias current flows through the common-mode The load resistance in the voltage regulation circuit forms an adaptive voltage drop to realize output common-mode voltage regulation; Wherein, the adaptive current bias stage includes a first amplifier (A1), a first resistor (R1), a first NMOS transistor (MN1), and a second NMOS transistor (MN2); wherein, the reference voltage is connected to the first amplifier ( The negative input terminal of A1), the positive input terminal of the first amplifier (A1) is connected to the negative terminal of the first resistor (R1), and the output terminal of the first amplifier (A1) is connected to the gate of the first NMOS transistor (MN1); The source of the first NMOS transistor (MN1) is grounded and the drain is connected to the negative electrode of the first resistor (R1); the gate of the second NMOS transistor (MN2) is connected to the gate of the first NMOS transistor (MN1), The source of the second NMOS transistor (MN2) is grounded and the drain is connected to the negative pole of the reference current source; the positive pole of the first resistor (R1) is connected to the power supply; Wherein, the self-biased load amplifier includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a third NMOS transistor (MN3), and a fourth NMOS transistor (MN4); Wherein, the gate of the third PMOS transistor (MP3) is connected to the feedback voltage and the source is connected to the power supply, and the drain of the third PMOS transistor (MP3) is connected to the source of the first PMOS transistor (MP1) and the second PMOS transistor respectively. The sources of (MP2) are connected; the gate of the first PMOS transistor (MP1) is connected to the positive input voltage terminal, and the drain of the first PMOS transistor (MP1) is connected to the drain of the third NMOS transistor (MN3); The gate of the third NMOS transistor (MN3) is connected to the common-mode voltage regulation circuit and the source is grounded; the gate of the second PMOS transistor (MP2) is connected to the negative terminal of the input voltage, and the drain of the second PMOS transistor (MP2) The pole is connected to the drain of the fourth NMOS transistor (MN4); the gate of the fourth NMOS transistor (MN4) is connected to the gate of the third NMOS transistor (MN3), and the source of the fourth NMOS transistor (MN4) is grounded . 2. The output common-mode voltage adjustable amplifier according to claim 1 is characterized in that: the common-mode voltage regulation circuit includes a reference current source, a second resistor (R2), and a third resistor (R3); the reference current The positive end of the reference current is connected to the power supply, and the negative end of the reference current is respectively connected to the negative end of the second resistor (R2) and the negative end of the third resistor (R3); the second resistor (R2) and the third resistor (R3) The positive terminals of each are connected to a self-biased load amplifier.

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