CN204244064U - Eliminate drive circuit and the Switching Power Supply thereof of short circuit conducting - Google Patents
Eliminate drive circuit and the Switching Power Supply thereof of short circuit conducting Download PDFInfo
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- CN204244064U CN204244064U CN201420724059.0U CN201420724059U CN204244064U CN 204244064 U CN204244064 U CN 204244064U CN 201420724059 U CN201420724059 U CN 201420724059U CN 204244064 U CN204244064 U CN 204244064U
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- inverter
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- driving tube
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Abstract
The utility model discloses a kind of drive circuit and the Switching Power Supply thereof of eliminating short circuit conducting.With the Switching Power Supply eliminating short circuit on-state drive circuit, comprise the drive circuit of inlet circuit, circuit of output terminal, pulse-width modulation signal generating circuit and elimination short circuit conducting, the drive circuit eliminating short circuit conducting to comprise on the first NOR gate, the first inverter, the second inverter, the 3rd inverter, described first driving tube pipe NMOS tube under pipe PMOS, the first NAND gate, the 4th inverter, the 5th inverter, hex inverter and the first driving tube.The drive circuit of the elimination short circuit conducting utilizing the utility model to provide can eliminate driving tube short circuit conducting.
Description
Technical field
The utility model relates to drive circuit, particularly relates to the drive circuit for Switching Power Supply.
Background technology
The chance of drive circuit top tube and down tube ON time overlap is there will be in Switching Power Supply running, at this moment have big current and directly flow to ground from driving pipe and the lower pipe of driving through input voltage, form short circuit conducting phenomenon, burn out driving tube, in order to eliminate this phenomenon, just devise the drive circuit eliminating short circuit conducting.
Summary of the invention
The utility model is intended to solve the deficiencies in the prior art, provides a kind of drive circuit of the elimination short circuit conducting for Switching Power Supply.
With the Switching Power Supply eliminating short circuit on-state drive circuit, comprise the drive circuit of inlet circuit, circuit of output terminal, pulse-width modulation signal generating circuit and elimination short circuit conducting:
Described inlet circuit connects input voltage;
Described circuit of output terminal is that obtained voltage is exported;
Described pulse-width modulation signal generating circuit produces pulse-width signal;
The drive circuit of described elimination short circuit conducting is to eliminate driving tube top tube and down tube short circuit conducting.
The drive circuit of described elimination short circuit conducting to comprise on the first NOR gate, the first inverter, the second inverter, the 3rd inverter, described first driving tube pipe NMOS tube under pipe PMOS, the first NAND gate, the 4th inverter, the 5th inverter, hex inverter and the first driving tube:
The pwm signal that described in one input termination of described first NOR gate, pulse-width modulation signal generating circuit exports, under the output of hex inverter described in another input termination and described first driving tube, the grid of pipe NMOS tube, exports the input of the first inverter described in termination;
The output of the first NOR gate described in the input termination of described first inverter, exports the input of the second inverter described in termination;
The output of the first inverter described in the input termination of described second inverter, exports the input of the 3rd inverter described in termination;
The output of the second inverter described in the input termination of described 3rd inverter, exports the grid of pipe PMOS on an input of the first NAND gate described in termination and described first driving tube;
On described first driving tube, the grid of pipe PMOS connects the output of described 3rd inverter and an input of described first NAND gate, the bridge heap that source electrode connects described input circuit exports, and drain electrode connects the drain electrode of pipe NMOS tube under the catching portion of described input circuit and the primary coil of transformer and described first driving tube;
One input termination of described first NAND gate connects the pwm signal of described pulse-width modulation signal generating circuit output, on the output of the 3rd inverter described in another input termination and described first driving tube, the grid of pipe PMOS, exports the input of the 4th inverter described in termination;
The output of the first NAND gate described in the input termination of described 4th inverter, exports the input of the 5th inverter described in termination;
The output of the 4th inverter described in the input termination of described 5th inverter, exports the input of hex inverter described in termination;
The output of the 5th inverter described in the input termination of described hex inverter, exports the grid of pipe NMOS tube under an input of a NOR gate described in termination and described first driving tube;
Under described first driving tube, the grid of pipe NMOS tube connects the output of described hex inverter and an input of described first NOR gate, source ground, drain electrode connects the drain electrode of pipe PMOS on the catching portion of described input circuit and the primary coil of transformer and described first driving tube.
When the pwm signal that described pulse-width modulation signal generating circuit exports is high level, described first NOR gate exports as low level, again through described first inverter, described second inverter, described 3rd inverter three inverters drive, the grid arriving pipe PMOS on described first driving tube is high level, close pipe PMOS on described first driving tube, this signal also needs through described first NAND gate, 4th inverter, 5th inverter, these four gate delay times of hex inverter just can reach the grid of pipe NMOS tube under described first driving tube, the signal arriving the grid of pipe NMOS tube under described first driving tube is high level, make pipe NMOS tube conducting under described first driving tube, this conducting pipe PMOS on described first driving tube occurs after closing after four gate delay time, avoid the ON time of pipe PMOS on described first driving tube completely, pipe conducting simultaneously up and down would not be made like this, eliminate short circuit conducting.
When the pwm signal that described pulse-width modulation signal generating circuit exports is low level, described first NAND gate exports as high level, again through described 4th inverter, described 5th inverter, described hex inverter three inverters drive, arriving the grid of pipe NMOS tube under described first driving tube is low level, close pipe NMOS tube under described first driving tube, this signal also needs through described first NOR gate, first inverter, second inverter, this four gate delay times of 3rd inverter just can reach the grid of pipe PMOS on described first driving tube, the signal arriving the grid of pipe PMOS on described first driving tube is low level, make pipe PMOS conducting on described first driving tube, this conducting pipe NMOS tube under described first driving tube occurs after closing after four gate delay time, avoid the ON time of pipe NMOS tube under described first driving tube completely, pipe conducting simultaneously up and down would not be made like this, eliminate short circuit conducting.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the Switching Power Supply of the drive circuit with elimination short circuit conducting of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model content is further illustrated.
With the Switching Power Supply eliminating short circuit on-state drive circuit, as shown in Figure 1, comprise inlet circuit 100, circuit of output terminal 200, pulse-width modulation signal generating circuit 300 and eliminate the drive circuit 400 of short circuit conducting:
Described inlet circuit 100 connects input voltage;
Described circuit of output terminal 200 is that obtained voltage is exported;
Described pulse-width modulation signal generating circuit 300 produces pulse-width signal;
The drive circuit 400 of described elimination short circuit conducting is to eliminate driving tube top tube and down tube short circuit conducting.
The drive circuit 400 of described elimination short circuit conducting to comprise on the first NOR gate 401, first inverter 402, second inverter 403, the 3rd inverter 404, described first driving tube pipe NMOS tube 410 under pipe PMOS 405, first NAND gate 406, the 4th inverter 407, the 5th inverter 408, hex inverter 409 and the first driving tube:
The pwm signal that described in one input termination of described first NOR gate 401, pulse-width modulation signal generating circuit 300 exports, under the output of hex inverter 409 described in another input termination and described first driving tube, the grid of pipe NMOS tube 410, exports the input of the first inverter 402 described in termination;
The output of the first NOR gate 401 described in the input termination of described first inverter 402, exports the input of the second inverter 403 described in termination;
The output of the first inverter 402 described in the input termination of described second inverter 403, exports the input of the 3rd inverter 404 described in termination;
The output of the second inverter 403 described in the input termination of described 3rd inverter 404, exports the grid of pipe PMOS 405 on an input of the first NAND gate 406 described in termination and described first driving tube;
On described first driving tube, the grid of pipe PMOS 405 connects the output of described 3rd inverter 404 and an input of described first NAND gate 406, the bridge heap that source electrode connects described input circuit 100 exports, and drain electrode connects the drain electrode of pipe NMOS tube 410 under the described catching portion of input circuit 100 and the primary coil of transformer and described first driving tube;
One input termination of described first NAND gate 406 connects the PWM letter of described pulse-width modulation signal generating circuit 300 output
Number, on the output of the 3rd inverter 404 described in another input termination and described first driving tube, the grid of pipe PMOS 405, exports the input of the 4th inverter 407 described in termination;
The output of the first NAND gate 406 described in the input termination of described 4th inverter 407, exports the input of the 5th inverter 408 described in termination;
The output of the 4th inverter 407 described in the input termination of described 5th inverter 408, exports the input of hex inverter 409 described in termination;
The output of the 5th inverter 408 described in the input termination of described hex inverter 409, exports the grid of pipe NMOS tube 410 under an input of a NOR gate 401 described in termination and described first driving tube;
Under described first driving tube, the grid of pipe NMOS tube 410 connects the output of described hex inverter 409 and an input of described first NOR gate 401, source ground, drain electrode connects the drain electrode of pipe PMOS 405 on the described catching portion of input circuit 100 and the primary coil of transformer and described first driving tube;
When the pwm signal that described pulse-width modulation signal generating circuit 300 exports is high level, described first NOR gate 401 exports as low level, again through described first inverter 402, described second inverter 403, described 3rd inverter 404 3 inverters drive, the grid arriving pipe PMOS 405 on described first driving tube is high level, close pipe PMOS 405 on described first driving tube, this signal also needs through described first NAND gate 406, 4th inverter 407, 5th inverter 408, these four gate delay times of hex inverter 409 just can reach the grid of pipe NMOS tube 410 under described first driving tube, the signal arriving the grid of pipe NMOS tube 410 under described first driving tube is high level, make pipe NMOS tube 410 conducting under described first driving tube, this conducting pipe PMOS 405 on described first driving tube occurs after closing after four gate delay time, avoid the ON time of pipe PMOS 405 on described first driving tube completely, pipe conducting simultaneously up and down would not be made like this, eliminate short circuit conducting.
When the pwm signal that described pulse-width modulation signal generating circuit 300 exports is low level, described first NAND gate 406 exports as high level, again through described 4th inverter 407, described 5th inverter 408, described hex inverter 409 3 inverters drive, arriving the grid of pipe NMOS tube 410 under described first driving tube is low level, close pipe NMOS tube 410 under described first driving tube, this signal also needs through described first NOR gate 401, first inverter 402, second inverter 403, this four gate delay times of 3rd inverter 404 just can reach the grid of pipe PMOS 405 on described first driving tube, the signal arriving the grid of pipe PMOS 405 on described first driving tube is low level, make pipe PMOS 405 conducting on described first driving tube, this conducting pipe NMOS tube 410 under described first driving tube occurs after closing after four gate delay time, avoid the ON time of pipe NMOS tube 410 under described first driving tube completely, pipe conducting simultaneously up and down would not be made like this, eliminate short circuit conducting.
Claims (1)
1. with the Switching Power Supply eliminating short circuit on-state drive circuit, comprise the drive circuit of inlet circuit, circuit of output terminal, pulse-width modulation signal generating circuit and elimination short circuit conducting, it is characterized in that the drive circuit of described elimination short circuit conducting to comprise on the first NOR gate, the first inverter, the second inverter, the 3rd inverter, described first driving tube pipe NMOS tube under pipe PMOS, the first NAND gate, the 4th inverter, the 5th inverter, hex inverter and the first driving tube:
The pwm signal that described in one input termination of described first NOR gate, pulse-width modulation signal generating circuit exports, under the output of hex inverter described in another input termination and described first driving tube, the grid of pipe NMOS tube, exports the input of the first inverter described in termination;
The output of the first NOR gate described in the input termination of described first inverter, exports the input of the second inverter described in termination;
The output of the first inverter described in the input termination of described second inverter, exports the input of the 3rd inverter described in termination;
The output of the second inverter described in the input termination of described 3rd inverter, exports the grid of pipe PMOS on an input of the first NAND gate described in termination and described first driving tube;
On described first driving tube, the grid of pipe PMOS connects the output of described 3rd inverter and an input of described first NAND gate, the bridge heap that source electrode connects described input circuit exports, and drain electrode connects the drain electrode of pipe NMOS tube under the catching portion of described input circuit and the primary coil of transformer and described first driving tube;
One input termination of described first NAND gate connects the pwm signal of described pulse-width modulation signal generating circuit output, on the output of the 3rd inverter described in another input termination and described first driving tube, the grid of pipe PMOS, exports the input of the 4th inverter described in termination;
The output of the first NAND gate described in the input termination of described 4th inverter, exports the input of the 5th inverter described in termination;
The output of the 4th inverter described in the input termination of described 5th inverter, exports the input of hex inverter described in termination;
The output of the 5th inverter described in the input termination of described hex inverter, exports the grid of pipe NMOS tube under an input of a NOR gate described in termination and described first driving tube;
Under described first driving tube, the grid of pipe NMOS tube connects the output of described hex inverter and an input of described first NOR gate, source ground, drain electrode connects the drain electrode of pipe PMOS on the catching portion of described input circuit and the primary coil of transformer and described first driving tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420724059.0U CN204244064U (en) | 2014-11-27 | 2014-11-27 | Eliminate drive circuit and the Switching Power Supply thereof of short circuit conducting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420724059.0U CN204244064U (en) | 2014-11-27 | 2014-11-27 | Eliminate drive circuit and the Switching Power Supply thereof of short circuit conducting |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204244064U true CN204244064U (en) | 2015-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420724059.0U Expired - Fee Related CN204244064U (en) | 2014-11-27 | 2014-11-27 | Eliminate drive circuit and the Switching Power Supply thereof of short circuit conducting |
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| Country | Link |
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| CN (1) | CN204244064U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110677021A (en) * | 2019-09-23 | 2020-01-10 | 北京时代民芯科技有限公司 | Output drive circuit of anti ground bounce noise |
| WO2021007737A1 (en) * | 2019-07-15 | 2021-01-21 | 华为技术有限公司 | Detection circuit and sensor |
-
2014
- 2014-11-27 CN CN201420724059.0U patent/CN204244064U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021007737A1 (en) * | 2019-07-15 | 2021-01-21 | 华为技术有限公司 | Detection circuit and sensor |
| CN110677021A (en) * | 2019-09-23 | 2020-01-10 | 北京时代民芯科技有限公司 | Output drive circuit of anti ground bounce noise |
| CN110677021B (en) * | 2019-09-23 | 2021-01-08 | 北京时代民芯科技有限公司 | Output drive circuit of anti ground bounce noise |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150401 Termination date: 20151127 |